CN101769988A - Chip debugging method, system and debugging module - Google Patents
Chip debugging method, system and debugging module Download PDFInfo
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- CN101769988A CN101769988A CN200810246880A CN200810246880A CN101769988A CN 101769988 A CN101769988 A CN 101769988A CN 200810246880 A CN200810246880 A CN 200810246880A CN 200810246880 A CN200810246880 A CN 200810246880A CN 101769988 A CN101769988 A CN 101769988A
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Abstract
The invention provides a chip debugging method, which comprises the following steps that: a debugging module receives infusion instructions and corresponding infusion points sent by a MCU, and caches infusion data input to the infusion points into a write data register of the debugging module; and when the infusion data cached into the write data register reach a predetermined bit value, the debugging module inputs the cached infusion data to the infusion points, and simultaneously sends a clock enabling signal to a clock module to start the clock of the infusion points during infusing. The MCU realizes the logic control of the debugging module in the chip debugging method by configuring a register of the debugging module through an APB bus, and infusion and capture modes are simple and flexible.
Description
Technical field
The present invention relates to the integrated circuit (IC) design technical field, particularly a kind of chip adjustment method, system and chip debugging module.
Background technology
Along with the integrated level and the complexity of chip are more and more higher, the debugging in the chip design also becomes increasingly complex, and the purpose of debugging will determine that not only fault has appearred in chip, also will find out the reason of fault.Under debugging mode, the designer can pour into data in the debugged system with controllable mode, from predetermined grabbing several somes data is read afterwards again, thereby detects the state of debugged system.But along with improving constantly of chip design level, as popularizing of SOC technology such as (System on Chip, SOC (system on a chip)), the quantity that point is counted in the filling in the debugged system also gets more and more, and the kind of irritating several points also becomes increasingly complex.Because different fillings is counted point and may be needed different transmission modes, debugging module may mate by the clock when irritating several somes operate as normal fully in addition.Therefore in the prior art, in order to realize pouring into of data, a plurality of debugging modules can be set in chip count point with different fillings and mate, these debugging modules can take the chip area of preciousness undoubtedly, raise the cost.In addition, the workload that a plurality of debugging modules also can increase the designer is set, increases the design cycle of chip.
As shown in Figure 1, be the structural drawing of a kind of chip debug circuit in the prior art.As can be seen from the figure, debugging module and MCU (Micro Controller Unit, micro-control unit) links to each other by APB (Advanced Peripheral BUS, advanced peripheral bus), and directly control debugging module by MCU debugged system is irritated number and grabs number.Debugging module is counted point with a plurality of fillings and is grabbed several points by MUX (Multiplexer, multi-way switch) and links to each other.As MCU during to the data register configuration data of debugging module, because MCU clock period only can be disposed the data of 8bit, therefore need in debugging module, carry out buffer memory, when after the data that are cached to 32bit in the debugging module data of this 32bit being circulated in the debugged system.Debugged like this system needs four clock period can receive that pours into data, and this and the normal work clock of debugged system do not match, and not only effect is debugged in influence, but also the workload can increase the designer and debug the time.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves the defective that existing chip debugging scheme can't be mated with the operate as normal clock of debugged system.
For achieving the above object, one aspect of the present invention proposes a kind of chip adjustment method, may further comprise the steps: debugging module receives that micro-control unit MCU sends pours into instruction and corresponding filling is counted a little, and will import that described filling counts point pour into metadata cache in the write data register of described debugging module; When buffer memory in the write data register described pours into data when reaching predetermined bit value, described debugging module pours into data with buffer memory described and imports described filling and count in the point, simultaneously to clock module tranmitting data register enable signal when irritating number, to open the clock that point is counted in described filling.
As an embodiment of said method of the present invention, described predetermined bit value can be 32bit.
As an embodiment of said method of the present invention, described debugging module can link to each other by advanced peripheral bus APB bus with described MCU, and information and the described data that pour into that point is counted in described filling send to described debugging module by described MCU by described APB bus.
As an embodiment of said method of the present invention, said method also comprises: thus described debugging module is resolved several points of grabbing of grabbing number instruction and correspondence that the APB bus is obtained described MCU transmission; Described debugging module is grabbed number according to described several points of grabbing of grabbing number instruction and correspondence, simultaneously grab the number instruction and produce and read enable signal the data in the described storer being read into the read data register in the described debugging module, and make the address of described storer add 1 according to described; Described debugging module receives reading instruction of described MCU transmission, and the data in the described read data register are offered described MCU.
As an embodiment of said method of the present invention, said method also comprises: described debugging module is resolved the start address that described APB bus is obtained reading of data from described storer.
As an embodiment of said method of the present invention, said method also comprises: described debugging module is resolved described APB bus and is obtained and grab number by addresses, is that the described number described debugging module when the address of grabbing stops to grab number in the current address of described storer.
As an embodiment of said method of the present invention, said method also comprises: described debugging module and a plurality of fillings are counted point and are grabbed several points and link to each other.
The present invention also proposes a kind of chip debug system on the other hand, comprise MCU, the debugging module that links to each other with described MCU, the debugged system that links to each other with described debugging module, and the clock module that clock is provided for described debugging module and described debugged system, at least one is irritated at several and links to each other with described debugging module in the wherein said debugged system, described MCU, be used to dispose the event registers of described debugging module to send the instruction of filling number to described debugging module, and indicate the several points of filling, and will pour into the write data register that data deposit described debugging module in; Described debugging module, be used for pouring into data when reaching predetermined bit value write data register buffer memory described, write data register buffer memory described poured into data imports the filling that described event registers indicates and count in the point, simultaneously to described clock module tranmitting data register enable signal when irritating number, to open the clock that point is counted in described filling.
As an embodiment of said system of the present invention, described predetermined bit value can be 32bit.
As an embodiment of said system of the present invention, described MCU links to each other by the APB bus with described debugging module, and described MCU is configured the register in the described debugging module by described APB bus.
An embodiment as said system of the present invention, said system also comprise with described debugged system at least one grabs the storer that several points and described debugging module all link to each other, in described debugging module and the described debugged system described at least one grab several points and also link to each other; Described storer is used to preserve the data of grabbing several somes extractings from described; Described MCU also is used for grabbing the number instruction by the number register of grabbing of the described debugging module of described APB bus configuration with transmission, indicates corresponding several points of grabbing simultaneously; Described debugging module, also be used for described grab that number register indicates described grabbed several points and grab number, instruct generation to read enable signal according to the described number of grabbing simultaneously so that the data in the described storer are read in the read data register, and make the address of described storer add 1, and after receiving reading instruction that described MCU sends, the data in the described read data register are offered described MCU.
As an embodiment of said system of the present invention, described MCU also is used for disposing the initial address register of described debugging module to indicate the start address from described storer reading of data to described debugging module.
As an embodiment of said system of the present invention, described MCU, what also be used to dispose described debugging module is describedly to indicate described debugging module to stop to grab number when grabbing number by the address by address register with the current address at described storer.
As an embodiment of said system of the present invention, described debugging module is counted point by multi-way switch MUX and described debugged intrasystem a plurality of fillings and is grabbed several points and link to each other with a plurality of.
Further aspect of the present invention also proposes a kind of debugging module, comprise event registers, write data register, clock enable signal generation module and irritate the digital-to-analogue piece, described event registers is used to preserve MCU and counts a little by the instruction of filling number and the corresponding filling of described APB bus configuration; The write data register is used for the pour into data of the described MCU of buffer memory by described APB bus transmission; Described clock enable signal generation module is used for pouring into data when reaching predetermined bit value write data register buffer memory described, produces the clock enable signal to open the clock that point is counted in described filling when the filling number; Described filling digital-to-analogue piece is used for pouring into data when reaching predetermined bit value write data register buffer memory described, write data register buffer memory described is poured into data import the indicated described filling of described event registers and count a little.
As an embodiment of the above-mentioned debugging module of the present invention, described predetermined bit value can be 32bit.
An embodiment as the above-mentioned debugging module of the present invention also comprises the APB bus interface that links to each other with the APB bus.
An embodiment as the above-mentioned debugging module of the present invention, described debugging module also comprises grabs number register, grabs the digital-to-analogue piece and reads the enable signal generation module, the described number register of grabbing is used to preserve the grab several points of grabbing number instruction and correspondence of described MCU by described APB bus configuration; The described digital-to-analogue piece of grabbing is used for described grab that number register indicates described grabbed several points and grab number; The described enable signal generation module of reading is used for grabbing number instruction and producing and read enable signal the data of storer are read in the read data register according to described, and makes the address of described storer add 1.
As an embodiment of the above-mentioned debugging module of the present invention, described debugging module also comprises initial address register, is used for preserving the start address from described storer reading of data of described MCU by described APB bus configuration.
An embodiment as the above-mentioned debugging module of the present invention, described debugging module also comprises by address register, be used to preserve described MCU and count by the address by grabbing of described APB bus configuration, the described digital-to-analogue piece of grabbing is that the described number of grabbing stops to grab number in the current address of described storer when the address.
The logic control of debugging module is in the present invention realized by the register of APB bus configuration debugging module by MCU, irritates number and grabs several mode simple and flexible.And the present invention controls clock module by the clock enable signal that debugging module produces, make it irritate the clock of several points in when irritating number, opening debugged system, make input clock and debugged system mate fully at the operate as normal clock, debugging efficiency not only can be improved, but also chip area can be reduced.In addition, the present invention also can control the number of grabbing of debugging module, not only can select different several points of grabbing, also can select to grasp the data volume of data, and after debugging module is receiving to grab the number instruction, can produce and read enable signal accordingly, data in the storer are read in the register in the debugging module, thereby offered MCU receiving after MCU reads instruction, further improve debugging efficiency.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the structural drawing of a kind of chip debug circuit in the prior art;
Fig. 2 is the synoptic diagram of APB bus timing;
Fig. 3 is the chip adjustment method process flow diagram of one embodiment of the invention;
Sequential chart when Fig. 4 irritates number for debugging module;
Fig. 5 grabs sequential chart when several for debugging module;
Fig. 6 is the chip debug system structural drawing of one embodiment of the invention;
Fig. 7 is an one embodiment of the invention debugging module structural drawing.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
The present invention mainly is, by the clock enable signal that debugging module produces clock module is controlled, make it irritate the clock of several points in only when irritating number, opening debugged system, make input clock and debugged system mate at the operate as normal clock, debugging efficiency not only can be improved, but also chip area can be reduced.
In addition, as a preferred embodiment of the present invention, grab when several by debugging module at MCU, debugging module is read enable signal accordingly receiving can produce after grabbing number instruction, data in the storer are read in the register in the debugging module, thereby offer MCU receiving after MCU reads instruction, further improved debugging efficiency.Further, need not in the present invention existing MCU is made a change, all logic controls to debugging module all can be realized by the register of APB bus configuration debugging module by MCU, irritate number and grab several mode simple and flexible.
In order clearer understanding to be arranged to the present invention, below at first the APB bus among the present invention is simply introduced, but need to prove that following embodiment of the present invention be that example describes with the APB bus only is in order to make the present invention clearer, and do not mean that the present invention only can realize by the APB bus, also can link to each other between MCU and the debugging module, for example I by other buses
2C bus etc.; the interface of its bus and order etc. can change when only using other buses to link to each other; but these change application did not influence of the present invention; those skilled in the art can combine with thought of the present invention according to the distinctive interface of these other buses or order the present invention is applied to other interfaces, so the variation of these buses all should be included within protection scope of the present invention.
As shown in table 1 below, be the interface synoptic diagram of APB bus interface on the debugging module.MCU controls debugging module by the APB bus, the register of configuration debugging module, and simultaneously debugging module is resolved information such as the instruction that obtains MCU and data by resolving the APB bus.As shown in Figure 2, be the synoptic diagram of APB bus timing.
Table 1
| Paddr (address) | ??8 | ??I |
| Pwdata (write data) | ??8 | ??I |
| Prdata (read data) | ??8 | ??O |
| Psel (selection) | ??1 | ??I |
| Pwrite (write signal) | ??1 | ??I |
| Penable (enable signal) | ??1 | ??I |
Debugging module not only has above-mentioned interface in the present invention, also needs to have following table 2 described interfaces, shown in its corresponding function also sees table.
Table 2
| ??clkena | ??1 | ??O | The clock enable signal makes pouring into the time control clock module of data |
| ??demodulate_xxx_data_strb | ??1 | ??O | Pour into the data useful signal that certain irritates several points, resolve by the APB bus and get |
| ??demodulate_xxx_data | ??N | ??O | Pour into the data that certain irritates several points, send into by the APB bus and irritate several points |
| ??xxx_xxx_data_strb | ??1 | ??I | Grasp the useful signal that certain grabs several point data |
| ??xxx_xxx_data | ??N | ??I | Grasp the data that certain grabs several points, read by the APB bus |
To be that example specifically describes with the APB bus below, but need the APB bus that is to use of explanation once more only to be one embodiment of the present of invention, the present invention also can use other buses.
As shown in Figure 3, chip adjustment method process flow diagram for one embodiment of the invention, comprise debugging module in this embodiment, coupled MCU and debugged system, and the clock module that clock is provided for debugging module and debugged system, debugging module is irritated several points by in MUX and the debugged system at least one and is grabbed several points with at least one and link to each other, and wherein debugging module links to each other with MCU by the APB bus.In order clearer understanding to be arranged to this embodiment, can be simultaneously with reference to Fig. 4 and Fig. 5, the sequential chart of Fig. 4 during for debugging module filling number, Fig. 5 grabs sequential chart when several for debugging module.This embodiment may further comprise the steps:
Step S301, MCU sends the filling that pours into instruction and correspondence to debugging module and counts a little.Wherein, in this embodiment, MCU controls debugging module by the APB bus, more specifically, MCU is configured the register in the debugging module by the APB bus, for example, the incident in the debugging module (case) register is configured, this event registers is represented the incident that will debug, irritates number indication and corresponding filling and counts a little.
Step S302, MCU will pour into data and write write data register (data_write) in the debugging module.
Step S303, when buffer memory in the write data register pour into data when reaching predetermined bit value, debugging module is counted the corresponding filling of data input that pours into of buffer memory in the point, simultaneously to clock module tranmitting data register enable signal when irritating number, just to open the clock of the several points of filling.Particularly, suppose that MCU once only can dispose the data of 8bit, and predetermined bit value be 32bit, then debugging module need wait until that the data that pour into of buffer memory reach that ability pours into to debugged system when being scheduled to the bit value.Predetermined bit value described herein is determined that by debugged system for example, debugged system needs 32bit, then should predetermined bit value can be made as 32bit, if debugged system needs 16bit, then should predetermined bit value can be made as 16bit.Simultaneously with reference to figure 4, debugging module produces the useful signal (apb_din_strb) that pours into data, and data in buffer is poured into data (apb_din) as what count to the corresponding filling of debugged system that point pours into.Because MCU once only can dispose the data of 8bit, therefore need 4 cycles could produce one and pour into data (apb_din), in order to be complementary with debugged system operate as normal clock, debugging module also needs to produce clock enable signal (clkena) among the present invention, makes clock module only open the clock that this irritates several points when irritating number.Therefore when not irritating number, this irritates several points is idle like this, and the data that pour into of its input are with the clock coupling of its operate as normal for irritating several points.Wherein, need to prove, debugging module can be resolved in several ways and be produced the useful signal (apb_din_strb) that pours into data, particularly, for example, referring to APB bus timing shown in Figure 2, debugging module just can learn by the parsing of pwrite, psel, three control signals of penable and paddr address wire whether MCU is joining number to write data register, and hence one can see that when can join and enough required pour into data (promptly reaching predetermined bit value), thereby parsing obtains pouring into the useful signal of data.
As the preferred embodiments of the present invention, debugging module of the present invention is counted the function except having above-mentioned filling, also has the several functions of grabbing of simple and flexible.Debugging module can go out to grab accordingly the number instruction and grab several points etc. according to the Command Line Parsing that MCU exchanges the die trial block register in the present invention, for MCU, still be at configuration register still like this as prior art, and debugging module can deposit corresponding data of grabbing several points in the read data register (data_read) of debugging module in according to the number instruction of grabbing that is resolved in the present invention, thereby MCU can directly take the data in this read data register away, further improve debugging efficiency, specifically see following steps for details.
Step S304, debugging module resolve the APB bus to obtain several points of grabbing of grabbing number instruction and correspondence that MCU sends.Particularly, the number of grabbing in the MCU configuration debugging module begins register (start), and the indication debugging module begins to grab number and indicates grabs several points accordingly.
Step S305, debugging module is grabbed number according to grabbing number instruction and corresponding several points of grabbing, simultaneously grab the number instruction and produce and read enable signal the data in the storer being read in the read data register in the debugging module, and make the address of described storer add 1 according to described.Particularly, with reference to shown in Figure 5, suppose that the clock of APB bus is 30MHz in this embodiment, the clock of debugging module is 60MHz, debugging module can produce according to pwrite, psel, three control signals of penable and paddr address wire and read enable signal (apb_read), more specifically, for example pwrite=0, psel=1, penable=1, and paddr produces when being the address of read data register (data_read) and reads enable signal (apb_read).Equally; debugging module also can be resolved in several ways and be obtained reading enable signal (apb_read) in this embodiment; if and the bus difference between debugging module and the MCU; analysis mode also can change, and what need explanation once more is that these variations all should be included within protection scope of the present invention in not breaking away from above-mentioned thought range of the present invention.
Step S306, debugging module offers MCU receiving reading instruction of MCU transmission with the data in the read data register, and MCU just can in time obtain it and grab several results like this.In the last example as shown in fig. 5, the enable signal (apb_read) of reading in the debugging module is two cycles, when first cycle, debugging module is read into the data of storing in the storer in the read data register (data_read) in the debugging module, and makes the address of storer add 1; Can just the data that just deposit read data register in be read away at second period MCU.
As a kind of optimal way of the present invention, MCU also can send to debugging module by the address with grabbing number, and debugging module stops to grab number in the current address of storer for grabbing when number ends the address.Particularly, can indicate debugging module to stop to grab number in several ways,, surpass certain address size post debugging module from the storer current address and stop to grab number as indication address stored length in storer.In the present invention, can dispose realizing in the debugging module by MCU by address register (length).
On the basis of above embodiment, as another optimal way of the present invention, MCU also can send to debugging module with the several start addresses of grabbing in storer, and this grabs the address of several start addresses for beginning when storer is read data.Particularly, can realize by the initial address register (addr_start) that MCU disposes in the debugging module.
From above-mentioned explanation as can be seen, MCU can be to grabbing the flexible configuration that number begins register (start), ends address register (length) and initial address register (addr_start), thereby realize grabbing several modes more flexibly, make the commissioning staff can obtain the data of oneself wanting fully according to the demand of oneself.
As shown in Figure 6, chip debug system structural drawing for one embodiment of the invention, comprise MCU100, the debugging module 200 that links to each other with MCU 100, the debugged system 300 that links to each other with debugging module 200, and, there is at least one to irritate several points in the wherein debugged system 300 and grabs at several with at least one and link to each other with debugging module 200 for debugging module 200 and debugged system 300 provide the clock module 400 of clock.MCU 100 is used to dispose the event registers of debugging module 200 and irritates the numbers instruction to send to debugging module 200, and indicates and irritate several points, and will pour into the write data register that data deposit debugging module 200 in.Debugging module 200 is used for pouring into data when reaching predetermined bit value at the write data register buffer memory, the filling that data incoming event register indicates that pours into of write data register buffer memory is counted in the point, simultaneously to clock module 400 tranmitting data register enable signals when irritating number, to open the clock of irritating several points.Wherein, predetermined bit value can be provided with according to the needs of debugged system, for example can be 32bit.
As one embodiment of the present of invention, MCU 100 links to each other by the APB bus with debugging module 200, and MCU is configured the register in the debugging module by the APB bus.Equally, MCU 100 also can link to each other by other buses with debugging module 200, contains but other buses also should be protection domain of the present invention.
As one embodiment of the present of invention, said system also comprise with debugged system 300 in grab the storer 500 that several points and debugging module 200 all link to each other.Storer 500 is used to preserve from grabbing the data that several points grasp.MCU 100 also is used for grabbing the number instruction by the number register of grabbing of APB bus configuration debugging module 200 with transmission, indicates corresponding several points of grabbing simultaneously.Debugging module 200 also is used for grabbing number to grabbing several points of grabbing that number register indicates, read enable signal so that the data in the storer are read in the read data register according to grabbing number instruction generation simultaneously, and make the address of storer 500 add 1, and after receiving reading instruction that MCU 100 sends, the data in the read data register are offered MCU100.
As one embodiment of the present of invention, MCU 100 also is used to dispose the initial address register of debugging module 200 and/or by address register, initial address register is used for to the start address of debugging module 200 indications from storer 500 reading of data; Debugging module 200 stops to grab number in the current address of storer 500 for grabbing when number ends the address.
As one embodiment of the present of invention, debugging module 200 is counted point by MUX and debugged intrasystem a plurality of fillings and is grabbed several points and link to each other with a plurality of.
Wherein, as shown in Figure 7, be one embodiment of the invention debugging module structural drawing, this debugging module 200 comprises event registers 211, write data register 212, clock enable signal generation module 220 and irritates digital-to-analogue piece 230.Event registers 211 is used to preserve MCU 100 and counts a little by the instruction of filling number and the corresponding filling of APB bus configuration.Write data register 212 is used for the pour into data of buffer memory MCU 100 by the transmission of APB bus.Clock enable signal generation module 220 be used for write data register 212 buffer memorys pour into data when reaching predetermined bit value, produce the clock enable signal when irritating number, to open the clock of the several points of filling.Irritate digital-to-analogue piece 230 be used for write data register 212 buffer memorys pour into data when reaching predetermined bit value, the data incoming event register 211 indicated fillings that pour into of write data register 212 buffer memorys are counted a little.Wherein, debugging module 200 also comprises the APB bus interface 240 that links to each other with the APB bus.
As a preferred embodiment of the invention, debugging module 200 also comprises grabs number register 213 and read data register 214 and grabs digital-to-analogue piece 250, reads enable signal generation module 260.Grab number register 213 and be used to preserve the grab several points of grabbing number instruction and correspondence of MCU 100 by the APB bus configuration.Grabbing digital-to-analogue piece 250 is used for grabbing number to grabbing several points of grabbing that number register 213 indicates.Read enable signal generation module 260 and be used for producing and reading enable signal the data of storer 500 are read in the read data register 214, and make the address of storer 500 add 1 according to grabbing number instruction.
As the preferred embodiments of the present invention, debugging module 200 also comprises initial address register 215 and/or ends address register 216.Initial address register 215 is used for preserving the start address from storer 500 reading of data of MCU 100 by the APB bus configuration.Be used to preserve MCU 100 by address register 216 and count by the address, grab digital-to-analogue piece 250 and stop to grab number when number ends the address for grabbing in the current address of storer 500 by grabbing of APB bus configuration.
The logic control of debugging module is in the present invention realized by the register of APB bus configuration debugging module by MCU, irritates number and grabs several mode simple and flexible.And the present invention controls clock module by the clock enable signal that debugging module produces, make it irritate the clock of several points in when irritating number, opening debugged system, make input clock and debugged system mate fully at the operate as normal clock, debugging efficiency not only can be improved, but also chip area can be reduced.In addition, the present invention also can control the number of grabbing of debugging module, not only can select different several points of grabbing, also can select to grasp the data volume of data, and after debugging module is receiving to grab the number instruction, can produce and read enable signal accordingly, data in the storer are read in the register in the debugging module, thereby offered MCU receiving after MCU reads instruction, further improve debugging efficiency.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (20)
1. a chip adjustment method is characterized in that, may further comprise the steps:
Debugging module receives that micro-control unit MCU sends pours into instruction and corresponding filling is counted a little, and will import that described filling counts point pour into metadata cache in the write data register of described debugging module;
When buffer memory in the write data register described pours into data when reaching predetermined bit value, described debugging module pours into data with buffer memory described and imports described filling and count in the point, simultaneously to clock module tranmitting data register enable signal when irritating number, to open the clock that point is counted in described filling.
2. chip adjustment method as claimed in claim 1 is characterized in that, described predetermined bit value is 32bit.
3. chip adjustment method as claimed in claim 1, it is characterized in that, described debugging module links to each other by advanced peripheral bus APB bus with described MCU, and information and the described data that pour into that point is counted in described filling send to described debugging module by described MCU by described APB bus.
4. chip adjustment method as claimed in claim 3 is characterized in that, also comprises:
Thereby described debugging module is resolved the APB bus and is obtained several points of grabbing of grabbing number instruction and correspondence that described MCU sends;
Described debugging module is grabbed number according to described several points of grabbing of grabbing number instruction and correspondence, simultaneously grab the number instruction and produce and read enable signal the data in the described storer being read into the read data register in the described debugging module, and make the address of described storer add 1 according to described;
Described debugging module receives reading instruction of described MCU transmission, and the data in the described read data register are offered described MCU.
5. chip adjustment method as claimed in claim 4 is characterized in that, also comprises:
Described debugging module is resolved the start address that described APB bus is obtained reading of data from described storer.
6. chip adjustment method as claimed in claim 4 is characterized in that, also comprises:
Described debugging module is resolved described APB bus and is obtained and grab number by addresses, is that the described number described debugging module when the address of grabbing stops to grab number in the current address of described storer.
7. chip adjustment method as claimed in claim 4 is characterized in that, also comprises: described debugging module and a plurality of fillings are counted point and are grabbed several points and link to each other.
8. chip debug system, it is characterized in that, comprise MCU, the debugging module that links to each other with described MCU, the debugged system that links to each other with described debugging module, and for described debugging module and described debugged system provide the clock module of clock, at least one is irritated at several and links to each other with described debugging module in the wherein said debugged system
Described MCU, the event registers that is used to dispose described debugging module is irritated the number instruction to send to described debugging module, and indicates and irritate several points, and will pour into the write data register that data deposit described debugging module in;
Described debugging module, be used for pouring into data when reaching predetermined bit value write data register buffer memory described, write data register buffer memory described poured into data imports the filling that described event registers indicates and count a little, simultaneously to described clock module tranmitting data register enable signal when irritating number, to open the clock that point is counted in described filling.
9. chip debug system as claimed in claim 8 is characterized in that, described predetermined bit value is 32bit.
10. chip debug system as claimed in claim 8 is characterized in that, described MCU links to each other by the APB bus with described debugging module, and described MCU is configured the register in the described debugging module by described APB bus.
11. chip debug system as claimed in claim 10, it is characterized in that, also comprise with described debugged system at least one grabs the storer that several points and described debugging module all link to each other, in described debugging module and the described debugged system described at least one grab several points and also link to each other;
Described storer is used to preserve the data of grabbing several somes extractings from described;
Described MCU also is used for grabbing the number instruction by the number register of grabbing of the described debugging module of described APB bus configuration with transmission, indicates corresponding several points of grabbing simultaneously;
Described debugging module, also be used for described grab that number register indicates described grabbed several points and grab number, instruct generation to read enable signal according to the described number of grabbing simultaneously so that the data in the described storer are read in the read data register, and make the address of described storer add 1, and after receiving reading instruction that described MCU sends, the data in the described read data register are offered described MCU.
12. chip debug system as claimed in claim 11 is characterized in that, described MCU also is used for disposing the initial address register of described debugging module to indicate the start address from described storer reading of data to described debugging module.
13. chip debug system as claimed in claim 11, it is characterized in that, described MCU, what also be used to dispose described debugging module is describedly to indicate described debugging module to stop to grab number when grabbing number by the address by address register with the current address at described storer.
14. chip debug system as claimed in claim 8 is characterized in that, described debugging module is counted point by multi-way switch MUX and described debugged intrasystem a plurality of fillings and is grabbed several points and link to each other with a plurality of.
15. a debugging module is characterized in that, comprises event registers, write data register, clock enable signal generation module and irritates the digital-to-analogue piece,
Described event registers is used to preserve the filling number instruction of MCU configuration and the filling of correspondence is counted a little;
The write data register is used for the data that pour into that the described MCU of buffer memory sends;
Described clock enable signal generation module is used for pouring into data when reaching predetermined bit value write data register buffer memory described, produces the clock enable signal to open the clock that point is counted in described filling when the filling number;
Described filling digital-to-analogue piece is used for pouring into data when reaching predetermined bit value write data register buffer memory described, write data register buffer memory described is poured into data import the indicated described filling of described event registers and count a little.
16. debugging module as claimed in claim 15 is characterized in that, described predetermined bit value is 32bit.
17. debugging module as claimed in claim 15 is characterized in that, also comprises the APB bus interface that links to each other with the APB bus.
18. debugging module as claimed in claim 17 is characterized in that, also comprises grabbing number register, grab the digital-to-analogue piece and reading the enable signal generation module,
The described number register of grabbing is used to preserve the grab several points of grabbing number instruction and correspondence of described MCU by described APB bus configuration;
The described digital-to-analogue piece of grabbing is used for described grab that number register indicates described grabbed several points and grab number;
The described enable signal generation module of reading is used for grabbing number instruction and producing and read enable signal the data of storer are read in the read data register according to described, and makes the address of described storer add 1.
19. debugging module as claimed in claim 18 is characterized in that, also comprises initial address register, is used for preserving the start address from described storer reading of data of described MCU by described APB bus configuration.
20. debugging module as claimed in claim 18, it is characterized in that, comprise also by address register, be used to preserve described MCU and count by the address that the described digital-to-analogue piece of grabbing is that the described number of grabbing stops to grab number in the current address of described storer when the address by grabbing of described APB bus configuration.
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| CN103246584A (en) * | 2012-02-14 | 2013-08-14 | 苏州澜起微电子科技有限公司 | Chip structure of system-on-chip and method for storing debug information |
| CN103744009A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Serial transmission chip test method, serial transmission chip test system and integrated chip |
| CN105808396A (en) * | 2016-03-04 | 2016-07-27 | 浙江大华技术股份有限公司 | Chip debugging device, debugging method and SOC (System of Chip) chip system |
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| CN101154184A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | JTAG debugging method for microcontroller |
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| CN109408433A (en) * | 2018-10-08 | 2019-03-01 | 北京理工大学 | A kind of interface arrangement and working method suitable for specific integrated circuit debugging |
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| CN113868070A (en) * | 2021-09-23 | 2021-12-31 | 山东云海国创云计算装备产业创新中心有限公司 | Debugging method, system, storage medium and equipment for SD card controller |
| CN113868070B (en) * | 2021-09-23 | 2023-08-25 | 山东云海国创云计算装备产业创新中心有限公司 | SD card controller debugging method, system, storage medium and device |
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