CN101639516B - Data processing method, controller and system - Google Patents
Data processing method, controller and system Download PDFInfo
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- CN101639516B CN101639516B CN 200810029897 CN200810029897A CN101639516B CN 101639516 B CN101639516 B CN 101639516B CN 200810029897 CN200810029897 CN 200810029897 CN 200810029897 A CN200810029897 A CN 200810029897A CN 101639516 B CN101639516 B CN 101639516B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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Abstract
The embodiment of the invention discloses a data processing method, a controller and a system. The processing system comprises a JTAG loading controller, an interrupt controller and a processor, wherein the JTAG loading controller is used for executing the transmitting and receiving of JTAG data, and sending an interrupt request to the interrupt controller according to the transmitting and receiving conditions of the JTAG data to finish the continuous processing of the transmitting and receiving of the JTAG data; the interrupt controller is used for responding the interrupt request from the JTAG loading controller, and sending the interrupt request to the processor; and the processor is used for processing the interrupt request sent by the interrupt controller, and processing the JTAG data when the JTAG loading controller receives and transmits the JTAG data. Because the processor processes the JTAG data when the JTAG loading controller receives and transmits the JTAG data, the continuous processing of the transmitting and receiving of the JTAG data is realized, and the JTAG processing efficiency is improved.
Description
Technical field
The present invention relates to the electron device mechanics of communication, relate in particular to a kind of data processing method, controller and system.
Background technology
(Joint Test Action Group, JTAG) technology mainly are in order to solve high complexity, highly integrated chip and printed circuit board (PCB) (Printed Circuit Board, test problem PCB) to propose JTAG the earliest.
Along with the development of JTAG technology, the JTAG technology makes the JTAG technology be used widely in the good performance of aspects such as product test, product maintenance upgrading, localization of fault.The JTAG technology itself is based on serial line interface, so treatment effeciency is the key index of this technology, yet no matter existing special-purpose JTAG processing apparatus or other processing apparatus are at handling property, still on the cost of application, does not have advantage.
The technical scheme that the special-purpose JTAG processing apparatus of existing employing is realized, (Central Processing Unit, CPU) mode realizes mainly to be to use special chip+professional central processing unit.
Special chip provides corresponding interface, and realizes the transmitting-receiving of JTAG data under the control of business CPU, specifically such as, business CPU is responsible for calculation process by the JTAG data of special chip transmission, and with the JTAG data distributing handled to special chip; Special chip is then realized JTAG data stream and string conversion, and the input of the test reset in the control jtag interface (Test Reset, TRST), test pattern is selected (Test Mode Select, TMS), test data input (Test Data Input, TDI) and test data output (Test Data Output, TDO), test clock (Test Clock, TCK) transmitting-receiving of data.
As shown in Figure 1, the mode of operation that special chip is handled the JTAG data is: business CPU is finished the computing of the JTAG data that will send, JTAG data such as TMS, TDI are write the special chip corresponding address, special chip starts transmission and receives the TDO data, business CPU is waited for the special chip processing at this moment, finishes dealing with until special chip.After special chip was finished dealing with, after business CPU was fetched the data that receive, computing needed the data that send next time, and the data that computing is finished are write the corresponding address of special chip, started JTAG operation next time.Cycling is successively finished until operation.
In realizing process of the present invention, the inventor finds, in the whole operation process, as shown in Figure 1, it is that serial hockets with the transmitting-receiving of JTAG data stream that business CPU is handled (as the data transmit-receive of CPU), after CPU sends the JTAG data, must wait for that the data transmit-receive operation of special chip and outside jtag interface finishes, just can carry out CPU operation next time, like this, the data transmit-receive that has caused special chip is discontinuous, and the JTAG treatment effeciency is low.
Summary of the invention
Technical matters to be solved by this invention is, provides a kind of JTAG treatment effeciency high data processing method, controller and system.
On the one hand, embodiments of the invention provide a kind of disposal system, and described disposal system comprises processor processor, interruptable controller and JTAG loading control; Wherein, described JTAG loading control is used for carrying out transmission and the reception of described JTAG data, and sends interrupt request to finish the continuous processing of described JTAG data transmit-receive according to transmission and the reception condition of described JTAG data to described interruptable controller; Described interruptable controller is used for response from the interrupt request of described JTAG loading control, and described interrupt request is sent to described processor; Described processor for the treatment of the interrupt request of described interruptable controller transmission, and when described JTAG loading control carries out the JTAG data transmit-receive, carries out described JTAG data operation and handles;
Wherein, described JTAG loading control comprises:
Processing and control element (PCE) is used for from described processor receiving control information, and carries out described JTAG data when handling according to described control information at described processor, controls the continuous processing of described JTAG data transmit-receive;
Data storage cell is used for storage JTAG data;
The condition monitoring unit is used for the treatment state of the JTAG data of the described data storage cell storage of monitoring, and reports or shield the relevant treatment state according to configuration to described interruptable controller;
The sequential control interface links to each other with described data storage cell, the JTAG data that be used for to realize described data storage cell storage and external series data alternately.
On the other hand, embodiments of the invention provide a kind of JTAG loading control, and it comprises: processing and control element (PCE) is used for carrying out the JTAG data when handling according to the control information of described processor at described processor, the continuous processing of control JTAG data transmit-receive; Data storage cell is used for the corresponding JTAG data of storage under the control of described processing and control element (PCE); The condition monitoring unit is used for the treatment state of the JTAG data of the described data storage cell storage of monitoring, and reports or shield the relevant treatment state according to configuration to described interruptable controller; The sequential control interface, the JTAG data that be used for to realize described data storage cell storage and external series data alternately.
On the other hand, embodiments of the invention also provide a kind of data processing method of disposal system, described disposal system comprises above-mentioned processor and JTAG loading control, described method comprises: when described processor carries out the JTAG data transmit-receive at described JTAG loading control, carry out the JTAG data operation and handle; When idle storage space is arranged in described processor detects described JTAG loading control, then the JTAG data that described processor has been finished dealing with store the storage space storage of described free time into, otherwise described processor is proceeded the calculation process of JTAG data;
Described method also comprises:
Described JTAG loading control carries out the JTAG data according to the control of described processor and receives and dispatches continuously;
When described JTAG loading control carries out the transmission of JTAG data, when described JTAG loading control has idle storage space, obtain and store the JTAG data that described processor has been finished dealing with from described processor.
In embodiments of the present invention, because processor is when described JTAG loading control carries out the JTAG data transmit-receive, carrying out described JTAG data operation handles, because processor speed is generally faster than the speed of the data transmit-receive of JTAG loading control, like this, just guaranteed that the JTAG loading control carries out the continuity of data transmit-receive, improved the efficient that JTAG handles.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is that existing C PU handles and JTAG data stream timing diagram;
Fig. 2 is a composition synoptic diagram of the disposal system in the embodiment of the invention;
Fig. 3 is that MCU handles and JTAG data stream timing diagram in the embodiment of the invention;
Fig. 4 is the composition synoptic diagram of the embodiment of the JLC among Fig. 2;
Fig. 5 is the composition synoptic diagram of the embodiment of the register module in the data storage cell among Fig. 4;
Fig. 5 a is the composition synoptic diagram of a specific embodiment of the processing and control element (PCE) among Fig. 2;
Fig. 6 is the composition synoptic diagram of the embodiment of the cache module in the data storage cell among Fig. 4;
Fig. 6 a is the composition synoptic diagram of another specific embodiment of the processing and control element (PCE) among Fig. 2;
Fig. 7 is JTAG external interface TDI under the TMS automatic send mode in the embodiment of the invention, TMS, TCK sequential fiting relation figure;
Fig. 8 is another composition synoptic diagram of the embodiment of the cache module in the data storage cell in the embodiment of the invention;
Fig. 8 a is cache module in the embodiment of the invention and a kind of composition synoptic diagram of processing and control element (PCE);
Fig. 9 is another composition synoptic diagram of the disposal system in the embodiment of the invention;
Figure 10 is the application scenarios synoptic diagram of the disposal system in the embodiment of the invention;
Figure 11 is a schematic flow sheet of the data processing method of the disposal system in the embodiment of the invention;
Figure 12 is that the present invention is a schematic flow sheet that interrupts handling in the data processing method of the disposal system in the example;
Figure 13 is the schematic flow sheet of the inner MCU of disposal system and JLC compounding practice in the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
In the prior art, when realizing the JTAG technology, because when special chip carries out data transmit-receive, CPU can not walk abreast carries out processing such as data transmit-receive, computing, make that CPU sends the JTAG data after, must wait for that transmit operation finishes, just can carry out next operation, this has influenced the treatment effeciency of JTAG greatly, for this reason, JTAG loading control (JTAG Loader Controller, technology JLC) have been proposed to comprise in a kind of disposal system in the embodiment of the invention.
As shown in Figure 2, the disposal system that provides in the embodiment of the invention comprises processor 1, interruptable controller 2 and JLC3.
Described disposal system can be to be integrated in the same chip in embodiments of the present invention, as be integrated into system on a slice (Systems on Chip, SOC), or processor and interrupt handler are integrated on the same chip, JLC then realizes with another chip.
Wherein, described processor 1 is used for interruptable controller 2 and JLC 3 are controlled, and when JLC 3 carries out data transmit-receive, carries out the JTAG data synchronously and handle.Described processor 1 can for micro-control unit (Micro Controller United, MCU).
Described interruptable controller 2 is used for response from the interrupt request of described JLC 3, and described interrupt request is sent to described processor 1 processing.
Described JLC 3, be used for the control according to described processor 1, realize transmission and the reception of JTAG data, send interrupt request according to transmission and the reception condition of described JTAG data to described interruptable controller 2, and the continuous processing when realizing the JTAG data transmit-receive, reaching TCK does not have etc. pending.Because the processing speed of processor 1 will be higher than the data transmit-receive speed of JLC3, so when JLC3 finished a last data transmit-receive, next data that processor 1 is finished dealing with had been ready to and can have been received and dispatched by JLC3, therefore, for JLC3, its data transmit-receive can be realized carrying out continuously.It is the mode of the parallel processing of similar Fig. 3.
Simultaneously, because JLC 3 is integrated in the disposal system, so the data address bus between JLC1 and the processor 1 is the bus of chip internal, its bus efficiency also will be with respect to the bus efficiency height of chip chamber.
As shown in Figure 4, JLC 3 comprises: condition monitoring unit 30, processor interface 32, processing and control element (PCE) 34, data storage cell 36 and sequential control interface (Serial Timing Control) 38.
Processing and control element (PCE) 34, link to each other with described processor interface 32, be used for by processor interface 32 from described processor receiving control information, and carry out the JTAG data when handling according to described control information at described processor, the continuous processing of control JTAG data transmit-receive.Wherein, described control information can comprise: processor to the release of this processing and control element (PCE) 34 enable, interconnected, sending mode, state report mode and relevant configuration information etc. arbitrarily for TCK frequency, outer chains.
Comprise two kinds of patterns when wherein, described data storage cell 36 carries out the data storage: register mode and cache mode.
Pattern one: when being register mode, data storage cell 36 comprises register module 360, and this register module 360 is used for by register mode, the corresponding JTAG data of storage under the control of described processing and control element (PCE) 34.
According to the difference of preserving data, as shown in Figure 5, register module 360 specifically can comprise: TMS register 3600 is used for the TMS data that the described processor interface 32 of storage sends; Test data register 3602 is used for storage input/output test data (being TDI, TDO); TCK register 3604 is for the relevant information of storage test clock signals, as the number of NOP TCK; Register module also can further comprise: reseting register 3606 is used for storage TRST signal.
Wherein, but the transmission data length flexible configuration in the test data register 3602.The value of TRST in the reseting register 3606 can directly be reacted the level signal of external interface TRST.The NOP TCK number of numerical value for needing to send in the TCK register 3604.When sending NOP TCK, the state of the coherent signal interface of other registers all keeps laststate constant.
Then corresponding, in pattern once, shown in Fig. 5 a, processing and control element (PCE) 34 comprises: register mode control module 340, the JTAG data that this register mode control module 340 is used for the described processor 1 of control directly write to corresponding register, and after writing end, enable the transmission of corresponding data, or be used for the JTAG data that control sequential control interface 38 receives and store corresponding register into.
Wherein, the TMS that stores in the register and TDI signal can independently send, and when sending wherein any one, other states remain unchanged.Last TDI and TMS need cooperate when sending on for chain, and special-purpose TMS, TDI register group are provided, and guarantee last TDI bit and first bit of afterbody TMS totally one TCK transmission.Then register module 360 also comprises special register group 3608, the data when being used for storage TMS and TDI cooperation transmission; Shown in Fig. 5 a, processing and control element (PCE) 34 also comprises common position processing module 342, be used for when the TMS on the data chain and TDI cooperation transmission, utilizing the data of described special register group 3608 storages that last bit of described TDI and first bit of described TMS are sent in same test clock.
Pattern one is mainly used in for the JTAG operational transformation frequent, and processor participates in the fitness height, and the short situation of JTAG data length, owing to adopted the relevant data of register-stored, makes that operation is more flexible under this pattern, and can adapt to complex process.
Pattern two: when being cache mode, data storage cell 36 comprises cache module 362, is used for by cache mode the corresponding JTAG data of storage under the control of described processing and control element (PCE) 34.
As shown in Figure 6, concrete, described cache module can further comprise begin chain submodule 3620, is used for the begin chain TMS of storage JTAG scan chain; Last-of-chain submodule 3622 is for the last-of-chain TMS of storage JTAG scan chain; At least two cache sub-module 3624 are used for the TDI that the described processor 1 of storage sends, or storage is by the TDO of described sequential control interface 38 receptions.
Wherein, according to the configuring condition to described JTAG scan chain begin chain TMS and last-of-chain TMS, cache mode can be divided into the manual sending mode of TMS automatic send mode and TMS again:
In the TMS automatic send mode, after processor disposes the TMS_H (begin chain TMS) and TMS_L (last-of-chain TMS) of storage in begin chain submodule 3620 and the last-of-chain submodule 3622 for the first time, processor only need be deposited corresponding TDI value in the cache sub-module and get final product, when carrying out the transmitting-receiving of follow-up JTAG chain, do not need to change the Configuration Values of begin chain TMS and last-of-chain TMS, the each TDI value that only needs in the change buffer memory of processor, thus processor operations reduced.
Fig. 7 is under the TMS automatic send mode, in the cache sub-module, and JTAG external interface TDI, TMS, TCK sequential fiting relation figure.After begin chain TMS was sent completely, the TDI that stores in the cache sub-module began to send.When sending to last bit TDI, last-of-chain TMS and last bit TDI be the position altogether, namely sends under a TCK simultaneously, as being total to shown in the position among the figure.Send in other positions, divide equally exploitation between TMS, the TDI and send, and at non-delivery time, state keeps.
In the manual sending mode of TMS, when sending data, all need begin chain TMS in the manual configuration buffer memory and the value of last-of-chain TMS, cache sub-module still sends according to TMS automatic mode mode at every turn.When this kind pattern application scenarios mainly was JTAG chain overlength, single JTAG length can't be finished TMS situation from movingly the time greater than single buffer storage length.Guarantee the strand continuity of operation by this kind mode, improve treatment effeciency.
Accordingly, pattern two times, shown in Fig. 6 a, described processing and control element (PCE) 34 comprises: cache mode control module 344, the TDI that is used for the described processor 1 of control is written to corresponding cache sub-module, and is writing the transmission that finishes the back enable data, after the data chain in described cache sub-module is sent completely, enable to send next data chain of storing in the cache sub-module of non-NULL, and the TDO that can control by described sequential control interface 38 receptions is stored in the idle cache sub-module.Certainly, described processing and control element (PCE) 34 can both comprise cache mode control module 344, also can comprise register mode control module 340 simultaneously and be total to position processing module 342.
So, under the control of processing and control element (PCE) 34, when idle buffer memory is arranged among the JLC, even JLC is during receiving and dispatching, the data that processor can be finished computing are filled up to remaining cache, as shown in Figure 8, wherein, Boundary represents cache sub-module, in TDI data among the Boundary 0 send, this moment, other Boundary was idle condition, and processor can be filled in the TDI data in remaining idle Boundary, filled in to enable this Boundary after finishing and send sign.After JLC was sent completely a Boundary, automatic sequence sent the Boundary of non-NULL.By this kind mode, can be so that during buffer memory sent, processor can be handled the TDO data that correlation reception is arrived, and the transmission of preparing next frame TDI data, send executed in parallel thereby make processor handle with the JTAG data.
Receiving the TDO data in the process of transmitting can leave among the Boundary of correspondence position transmission, in addition arbitrarily in the buffer memory data when sending, the TDI data can keep the value after the last operation, therefore processor only need be changed corresponding location revision, do not need one by one the address to fill in, thereby reduce the data-moving between processor and JLC, improve interactive efficiency.
When cache mode was applied to JTAG loading Flash, meeting directly be guided to processor by IO with the Flash write signal in a lot of the application,, was cooperated and controlled according to disposition by processor, reduced the JTAG data chain number that needs transmission, thereby improved the efficient of upgrading.This IO is commonly referred to DirectWe (DW).Because this operation is to intert at JTAG chain afterbody, therefore when independent IO control, CPU needs singly to wait for that chain issues and finish that processing DW will inevitably influence two JTAG data interchain continuity of operation like this.
In the embodiment of the invention, shown in Fig. 8 a, provide the cache module 362 that comprises the DW module for this reason.DW module 3628 is used for storage DW attribute, and described DW attribute is as a configuration attribute of corresponding JTAG data chain.Under manual mode, this DW is by the processor processing controls.
In order to carry out automatic mode control to DW, the embodiment of the invention also provides the processing and control element (PCE) that comprises DW control module 346.DW control module 346 is used for after the transmission of the data of JTAG described in buffer memory chain finishes, according to described DW attribute and next bar data chain synchronized transmission respective pulses.
Under the DW automatic mode, DW is as configuration attribute of this JTAG data chain, this scan chain data of configuration disposes this DW attribute simultaneously in cache module at every turn, after this JTAG data chain transmission finishes in the cache module, DW can send respective pulses (pulse width is configurable) according to the configuration level automatically, and with next bar chain synchronized transmission, do not need processor to participate in, thereby reached the Complete Continuity of many chains of JTAG operation.
As shown in Figure 9, send for carrying out register mode and cache mode, and the disposal system composition synoptic diagram that can carry out automatic DW pattern control, wherein, the signal link among the figure between the part of module does not show.Wherein, interruptable controller specifically can be vectorial interruptable controller (VIC); Processor interface can be processor peripheral bus interface (Peripheral Bus Interface).Register module comprises: model selection register (abbreviating TMS among the figure as), input-output register (abbreviating TDI_TDO among the figure as), clock register (abbreviating TCK among the figure as) and reseting register (abbreviating TRST among the figure as).Cache module comprises: begin chain submodule and last-of-chain submodule (being shown TMS_H and TMS_T among the figure), n cache sub-module (be Boundary 0 among the figure ..., Boundary n) and DW module (abbreviating DW among the figure as).Simultaneously, the sequential control interface has also been illustrated the data type of input and output, wherein n among the figure
*Be expressed as n group jtag interface, every group includes TRST, TMS, TDI, TCK, TDO.
As shown in figure 10, then be the application scenarios of the SOC in the embodiment of the invention.Adopt SOC to realize the disposal system of the embodiment of the invention, FE is network interface among the figure, realizes with far-end/near-end webmaster mutual.BSC is boundary scan cell (Boundary Scan Cell).MPU is the master control business CPU, realizes the storage of JTAG service data, transmission, safeguards.Universal serial bus is realized SOC and master control communication.BSC is boundary scan cell, and Board is different service board, and SOC is responsible for finishing JTAG and handles operation, and the return result.
The veneer loading of upgrading, fault diagnosis, the JTAG data file of interconnected test etc., by far-end background net management or near-end maintaining terminal downloads in the master control veneer storage medium, when needs carry out JTAG upgrading, test operation, master control borad issues related command and gives in requisition for the veneer of handling (i.e. Board among the figure 0, ..., Board n) Nei Bu SOC, trigger this SOC and start the associative operation processing, SOC returns to master control with data and the operating result of finishing in the operating process, and master control reports webmaster again.
In the entire process process, SOC is the center of JTAG data processing operation, does not need master control to participate in, and master control only is responsible for data and is sent the collection and treatment result.Be about to JTAG calculation process center and move down into each node, be distributed arithmetic, support multinode to carry out JTAG simultaneously and handle operation, thus efficient when improving a plurality of veneers and operating simultaneously.
From the above embodiment of the present invention as can be seen, in disposal system, comprise JLC, and by the cooperate processing of JLC with processor, make when disposal system is handled the JTAG data, can realize the continuous processing of JLC test clock, reaching TCK does not have the transmitting-receiving of wait, has improved the JTAG data processing efficiency.
Simultaneously, as shown in figure 11, also provide a kind of data processing method in the embodiment of the invention, this method comprises:
1101, processor is controlled JLC, makes described JLC can carry out the continuous processing of JTAG data, and reaching TCK does not have the transmitting-receiving of wait.Described JTAG data are stored and are received and dispatched with the form of data chain.
1102, processor is when described JLC carries out data transmit-receive, carrying out the JTAG data synchronously handles, when idle storage space is arranged in described processor detects described JLC, then the JTAG data that described processor has been finished dealing with store the storage space storage of described free time into, otherwise described processor is proceeded the processing of JTAG data.
Wherein, 1101 and 1102 can be that sequencing is carried out, and can be synchronous execution also, and step 1101 specifically can be:
1, processor is configured described JLC.Wherein, this configuration can be that processor is JLC configuration begin chain TMS and last-of-chain TMS and other relevant control informations etc., and JLC can be under the situation that processor does not participate in after finishing this configuration like this, finish and outside jtag interface between data transmit-receive.
2, JLC is after finishing the transmitting-receiving of current data chain, if described JLC also has other data chains to be received and dispatched, then described JLC proceeds the transmitting-receiving of corresponding data according to described configuration.
As shown in figure 12, the data processing method in the embodiment of the invention also comprises the process of handling interrupt:
1201, JLC finishes current data chain transmitting-receiving back generation interrupt request.
1202, processor will according to the interrupt request that reports
The JTAG data of having handled are sent to described JLC.
Among the step B, the processing that processor is proceeded the JTAG data comprises: processor obtains the TDI that receives from the outside among the JLC, and described TDI is handled.
As Figure 13, be the schematic flow sheet of disposal system internal processor (as MCU) in the embodiment of the invention with the JLC compounding practice.
As the inner JTAG operating process of the described disposal system of this figure, have three parts: interrupt processing, MCU processing, JLC processing.Interrupt handling and realize communication between JLC and MCU, in time the JLC operational circumstances is reported MCU.MCU is responsible for computing JTAG service data, and configuration JLC module, issues and the data that receive JLC.JLC is responsible for going here and there continuously and bi-directional conversion sends and receive the JTAG data.Handle by cooperating between the three, it is parallel to realize that MCU and JLC handle, and finally reaches outside output JTAG traffic continuity.
Specifically describe as follows to flow process shown in Figure 13:
1301, MCU at first needs JLC is configured, and enables JLC and can carry out the JTAG data transmit-receive;
1302, after the JLC configuration is finished, MCU sends the transmitting-receiving control command to it, control JLC begins to carry out the JTAG data transmit-receive, then JLC carries out data transmit-receive according to corresponding flow process: check 1302.1, whether buffer memory has the data that will receive and dispatch, 1302.2, if having then and carry out the I/O of JTAG data by the sequential control interface, 1302.3, finish data at JLC by the sequential control interface and send the back and produce transmitting-receiving and finish signal.Need to prove that when the sequential control interface was received and dispatched, data transmit-receive carried out synchronously, specifically can be referring to the relevant criterion of JTAG.
MCU carries out the JTAG data according to the situation continued that interrupts and handles after having issued JLC transmitting-receiving control command:
1303, the interrupt handler transmitting-receiving of sending according to JLC is finished signal and is produced and be sent completely interruption to MCU, simultaneously release mark;
1304, MCU is filled into the data of having finished dealing with in the JLC buffer memory according to above-mentioned sign;
1305, the buffer memory of the JLC of MCU whether judge by the free time;
1306, if JLC does not have free buffer, then MCU proceeds the data processing, and waits for next interrupt request in the back of finishing dealing with;
1307, if JLC has free buffer, then MCU is filled into data in the idle buffer memory, inserts in the MCU data and proceeds other data after finishing and handle or interrupt handling.
Do not show in this flow process that MCU obtains the process of the TDO data of need handling from JLC, be appreciated that before this process is handled these TDO data in MCU and carry out.
From to the description of the above embodiment of the present invention as can be seen, when JLC carries out data transmit-receive, MCU can obtain the pending JTAG data that JLC receives from the outside simultaneously, and the JTAG data are handled, realized the continuous processing of JLC, reaching TCK does not have the transmitting-receiving of wait, has improved the JTAG data processing efficiency.
Device embodiment described above only is schematic, wherein said unit as the separating component explanation can or can not be physically to separate also, the parts that show as the unit can be or can not be physical locations also, namely can be positioned at a place, perhaps also can be distributed on a plurality of network element.Can select wherein some or all of module to realize the purpose of present embodiment scheme according to the actual needs.Those of ordinary skills namely can understand and implement under the situation of not paying performing creative labour.
Through the above description of the embodiments, those skilled in the art can be well understood to each embodiment and can realize by the mode that software adds essential general hardware platform, can certainly pass through hardware.Based on such understanding, the part that technique scheme contributes to prior art in essence in other words can embody with the form of software product, this computer software product can be stored in the computer-readable recording medium, as ROM/RAM, magnetic disc, CD etc., comprise that some instructions are with so that a computer equipment (can be personal computer, server, perhaps network equipment etc.) carry out the described method of some part of each embodiment or embodiment.
Above-described embodiment does not constitute the restriction to this technical scheme protection domain.Any at above-mentioned embodiment spirit and principle within do modification, be equal to and replace and improvement etc., all should be included within the protection domain of this technical scheme.
Claims (14)
1. disposal system, described disposal system comprises processor and interruptable controller, it is characterized in that, described disposal system also comprises the JTAG loading control;
Wherein, described JTAG loading control is used for carrying out transmission and the reception of described JTAG data, and sends interrupt request to finish the continuous processing of described JTAG data transmit-receive according to transmission and the reception condition of described JTAG data to described interruptable controller;
Described interruptable controller is used for response from the interrupt request of described JTAG loading control, and described interrupt request is sent to described processor;
Described processor for the treatment of the interrupt request of described interruptable controller transmission, and when described JTAG loading control carries out the JTAG data transmit-receive, carries out described JTAG data operation and handles;
Wherein, described JTAG loading control comprises:
Processing and control element (PCE) is used for from described processor receiving control information, and carries out described JTAG data when handling according to described control information at described processor, controls the continuous processing of described JTAG data transmit-receive;
Data storage cell is used for storage JTAG data;
The condition monitoring unit is used for the treatment state of the JTAG data of the described data storage cell storage of monitoring, and reports or shield the relevant treatment state according to configuration to described interruptable controller;
The sequential control interface links to each other with described data storage cell, the JTAG data that be used for to realize described data storage cell storage and external series data alternately.
2. disposal system as claimed in claim 1 is characterized in that, described data storage cell comprises:
Register module is used for the data by register mode storage JTAG.
3. disposal system as claimed in claim 2 is characterized in that, described register module comprises:
The TMS register is used for the TMS data that the described processor interface of storage sends;
Test data register is for the test data of storage input and output;
The TCK register, the relevant information that is used for storing test clock;
Described processing and control element (PCE) comprises: the register mode control module, the JTAG data that are used for the described processor of control directly write to corresponding register, and make described JTAG data be in the state that can send after writing end, or the JTAG data that receive for control sequential control interface store corresponding register into.
4. disposal system as claimed in claim 2 is characterized in that,
Described register module also comprises the special register group, TMS and TDI data when being used for storage TMS and TDI cooperation transmission;
Described processing and control element (PCE) also comprises common position processing module, be used for when the TMS on the data chain and TDI cooperation transmission, utilizing the data of described special register group storage that last bit of described TDI and first bit of described TMS are sent in same test clock.
5. disposal system as claimed in claim 1 is characterized in that, described data storage cell comprises:
Cache module is used for by cache mode, storage JTAG data under the control of described processing and control element (PCE), and described JTAG data are stored with JTAG data chain form.
6. disposal system as claimed in claim 5 is characterized in that, described cache module comprises:
The begin chain submodule is for the begin chain TMS of storage JTAG scan chain;
The last-of-chain submodule is for the last-of-chain TMS of storage JTAG scan chain;
At least two cache sub-module are used for the TDI that the described processor of storage sends, or storage is by the TDO of described sequential control interface reception.
7. disposal system as claimed in claim 6 is characterized in that, described processing and control element (PCE) also comprises:
The cache mode control module, the TDI that is used for the described processor of control is written to corresponding cache sub-module, and after writing end, make described TDI be in the state that to send, after TDI data chain in described cache sub-module is sent completely, enable to send next data chain of storing in the cache sub-module of non-NULL, and the TDO that can control by described sequential control interface reception is stored in the idle cache sub-module.
8. disposal system as claimed in claim 6 is characterized in that, described cache module also comprises:
The DW module is used for storage DW attribute, and described DW attribute is a configuration attribute of corresponding JTAG data.
Described processing and control element (PCE) also comprises: the DW control module is used for after the transmission of the data of JTAG described in buffer memory chain finishes, according to described DW attribute and next bar data chain synchronized transmission respective pulses.
9. as each described disposal system in the claim 1 to 8, it is characterized in that described disposal system is integrated on the same chip.
10. the data processing method of a disposal system is characterized in that, described disposal system is the system as claimed in claim 1, and described method comprises:
When described processor carries out the JTAG data transmit-receive at described JTAG loading control, carry out described JTAG data operation and handle;
When idle storage space is arranged in described processor detects described JTAG loading control, then the JTAG data that described processor has been finished dealing with store the storage space storage of described free time into, otherwise described processor is proceeded the calculation process of described JTAG data;
Described method also comprises:
Described JTAG loading control carries out the JTAG data according to the control of described processor and receives and dispatches continuously;
When described JTAG loading control carries out the transmission of JTAG data, when described JTAG loading control has idle storage space, obtain and store the JTAG data that described processor has been finished dealing with from described processor.
11. method as claimed in claim 10 is characterized in that, the step that described processor is controlled described JTAG loading control comprises:
Described processor is configured described JTAG loading control.
12. method as claimed in claim 11 is characterized in that, described processor is configured described JTAG loading control and comprises:
Described processor disposes begin chain TMS and the last-of-chain TMS in the described JTAG loading control.
13. method as claimed in claim 10 is characterized in that, described method also comprises:
The JTAG data that the interrupt request that described processor produces according to described JTAG loading control will have been handled are sent to described JTAG loading control.
14. method as claimed in claim 10 is characterized in that, the step that described JTAG loading control carries out the continuous transmitting-receiving of JTAG data according to the control of described processor comprises:
Described JTAG loading control obtains configuration information from described processor, and is configured according to described configuration information;
Described JTAG loading control is after finishing described JTAG data transmit-receive, if described JTAG loading control also has other JTAG data to be received and dispatched, then described JTAG loading control is proceeded the transmitting-receiving of JTAG data according to described configuration, and described JTAG data are received and dispatched with data chain form.
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| CN102014008A (en) * | 2010-12-29 | 2011-04-13 | 华为技术有限公司 | Data disaster-tolerant method and system |
| CN103077051B (en) * | 2012-12-28 | 2015-09-30 | 华为技术有限公司 | load processing circuit, method and system |
| CN114036097B (en) * | 2021-10-09 | 2024-03-01 | 中国航空工业集团公司洛阳电光设备研究所 | Domestic FPGA logic online upgrading method for improving maintenance of photoelectric product |
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| US20040123193A1 (en) * | 2002-12-23 | 2004-06-24 | Gass Lawrence H. | Method and apparatus for enhanced parallel port JTAG interface |
| JP2006189305A (en) * | 2005-01-05 | 2006-07-20 | Ricoh Co Ltd | Boundary scan test circuit |
| CN101162438A (en) * | 2006-10-10 | 2008-04-16 | 北京中电华大电子设计有限责任公司 | Regulating technology of built-in processor |
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| CN1191532C (en) * | 2001-01-18 | 2005-03-02 | 深圳市中兴集成电路设计有限责任公司 | Synchronous serial ports controller |
| KR100707297B1 (en) * | 2005-12-01 | 2007-04-12 | (주)알파칩스 | Jtag test apparatus using system bus |
| CN101097242B (en) * | 2006-06-27 | 2010-04-21 | 中兴通讯股份有限公司 | Boundary scan testing controller and testing method thereof |
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| US20040123193A1 (en) * | 2002-12-23 | 2004-06-24 | Gass Lawrence H. | Method and apparatus for enhanced parallel port JTAG interface |
| JP2006189305A (en) * | 2005-01-05 | 2006-07-20 | Ricoh Co Ltd | Boundary scan test circuit |
| CN101162438A (en) * | 2006-10-10 | 2008-04-16 | 北京中电华大电子设计有限责任公司 | Regulating technology of built-in processor |
| CN101193326A (en) * | 2007-04-24 | 2008-06-04 | 中兴通讯股份有限公司 | Automatic testing device and method for multi-JTAG chain |
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