CN116187236A

CN116187236A - FPGA prototype verification system and method

Info

Publication number: CN116187236A
Application number: CN202310467217.2A
Authority: CN
Inventors: 刘洪锦; 田斌; 冯勇; 李猛
Original assignee: Taichu Wuxi Electronic Technology Co ltd
Current assignee: Taichu Wuxi Electronic Technology Co ltd
Priority date: 2023-04-27
Filing date: 2023-04-27
Publication date: 2023-05-30
Anticipated expiration: 2043-04-27
Also published as: CN116187236B

Abstract

The invention discloses an FPGA prototype verification system and method, wherein the system comprises: the system comprises a host and an FPGA hardware board, wherein an XDMA module, a control module, a PE module, a force accumulation module, a force write-back module, a 2-selection-1 module and a BRAM control module which are sequentially connected are arranged on the FPGA hardware board, and the force write-back module and the 2-selection-1 module are both connected with a first BRAM module; the invention provides a stable verification system environment by utilizing the FPGA hardware board card, and avoids repeated development of a plurality of systems.

Description

FPGA prototype verification system and method

Technical Field

The invention relates to the technical field of FPGA prototype verification, in particular to an FPGA prototype verification system and method.

Background

In the development process of the integrated circuit chip, various IP cores (Intellectual Property core) are used, wherein the IP cores can be commercial authorized IP or modules designed by developers. Before streaming, these IP cores need to use some effective method to detect if the logic and function of the design are correct, i.e. to perform verification of the IP. The verification methods which are commonly used at present comprise software UVM simulation, hardware simulator, FPGA prototype verification and the like. Among the digital chip verification means, the FPGA prototype verification technology is most suitable for chip software and hardware collaborative function verification.

The FPGA prototype verification platform can provide the real physical interface and hardware environment necessary for debugging the chip software, which cannot be provided by the logic function simulation and formal verification. Compared with a hardware accelerator, the software of the FPGA prototype verification platform runs an order of magnitude faster. Local or some interface logic codes can run according to the frequency which is closer to the real chip, so that the debugging time of software running and the period of verification iteration are greatly shortened, and meanwhile, the parallel development and verification of software and hardware is possible. In view of this, how to design an FPGA prototype verification platform, saving IP development time is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention provides an FPGA prototype verification system which is used for designing an FPGA prototype verification platform and saving IP development time.

In order to achieve the above effects, the technical scheme of the invention is as follows:

an FPGA prototype verification system comprising: the system comprises a host and an FPGA hardware board, wherein an XDMA module, a control module, a PE module, a force accumulation module, a force write-back module, a 2-selection-1 module and a BRAM control module which are sequentially connected are arranged on the FPGA hardware board, and the force write-back module and the 2-selection-1 module are both connected with a first BRAM module; wherein, the liquid crystal display device comprises a liquid crystal display device,

the XDMA module is used for realizing the conversion of the hardware board communication protocol of the host and the FPGA;

the control module is used for receiving and analyzing the control instruction sent by the host computer and controlling the operation of the PE module;

the PE module is used for receiving the control instruction analyzed by the control module and calculating output information Force; the Force information Force is forces between dynamic particles and static particle pairs in three directions of a space coordinate axis X, Y, Z, and the forces are respectively expressed by fx, fy and fz;

the Force accumulation module is used for accumulating the Force information Force of the static particles with the same serial number in the PE module to obtain the Force accumulation Force of the static particles with the same serial number, accumulating the Force information Force of the dynamic particles with the same serial number to obtain the Force accumulation Force of the dynamic particles with the same serial number, and transmitting the Force accumulation Force of the static particles and the Force accumulation Force of the dynamic particles to the Force writing back module;

the force write-back module is used for reading the static particle initial force and the dynamic particle initial force from the first BRAM module according to the address of the write-back force, obtaining a first resultant force after adding the static particle initial force and the static particle accumulation force, obtaining a second resultant force after adding the dynamic particle initial force and the dynamic particle accumulation force, and writing the first resultant force and the second resultant force back to the first BRAM module;

the 2-out-of-1 module is used for realizing the read access control of the force write-back module and the host to the first BRAM module in different time periods, and preventing read data collision;

the BRAM control module is used for performing read-write control on the first BRAM module; the first BRAM module is used for storing Force information Force.

It will be appreciated that the FPGA-based prototype may be an IP block, sub-module system, or even a functionally complete hardware representation of a complete SoC. The prototype of the FPGA in the present invention is a processing unit (PE module, processing Element) in the molecular dynamics project. The main differences of different IPs are represented in a control module and a test program, so that repeated debugging of an XDMA module, a first BRAM module, a second BRAM module, an AXI bus and the like is avoided. The comprehensive and layout wiring speeds are high, and the designer can adjust the design in time.

Furthermore, the host is provided with a Shell program and a test program, and an XDMA driver is arranged in the test program.

Further, the PE module is connected with a second BRAM module, where the second BRAM module is a ROM memory and is used for storing an initialization test configuration file and test input data of the PE module.

Further, the test program, the XDMA driver, the XDMA module, the first BRAM module, the second BRAM module and the BRAM control module are provided by the Siberian official; the Shell program, the control module, the force accumulation module, the force write-back module and the 2-1 selection module are designed and realized by a user.

Further, the specific working process of the control module is as follows: the control module receives and analyzes a control instruction sent by the host through PCIE, and if the control instruction is written into the first register, the 0 th bit of corresponding data represents a starting command signal, and the 1 st bit represents a resetting command signal; if it is the second register that is written, the lower 16 bits of the corresponding data represent the number of dynamic and static particle pairs sent to the PE module.

Further, the input/output interface signals of the force accumulation module are:

a first input signal representing a serial number of the static particles in the box;

a second input signal representing a sampled signal;

a third input signal representing the serial number of the dynamic particles in the box;

a fourth input signal representing Force information Force; the forces fx, fy and fz in the X axis, Y axis and Z axis directions between the static particles and the dynamic particles calculated by the PE module;

a fifth input signal representing a cassette valid signal for initiating operation of the force accumulation module;

a sixth input signal representing a force valid signal for indicating that the forces fx, fy, fz are valid;

a first output signal representing the accumulated Force information Force;

a second output signal representing positional information of the static/dynamic particles in the cassette;

a third output signal representing box number information;

a fourth output signal, which indicates that the writing of static particle Force information Force is effective;

a fifth output signal, which indicates that the write dynamic particle Force information Force is valid;

wherein the second input signal comprises:

the number of static particles and the number of dynamic particles;

the box number where the static particle is located is used for calculating the initial position of Force information Force corresponding to the static particle in the second BRAM module according to the box number where the static particle is located;

the box number where the dynamic particle is located is used for calculating the initial position of Force information Force corresponding to the dynamic particle in the second BRAM module according to the box number where the dynamic particle is located;

further, the working process of the force accumulation module is as follows: according to the serial number of the static particles in the box, force information Force and the number of the static particles, carrying out Force accumulation on the static particles in a set first accumulator to obtain static particle accumulation Force;

according to the serial number of the dynamic particles in the box, force information Force and the number of the dynamic particles, carrying out Force accumulation on the dynamic particles in a set second accumulator to obtain dynamic particle accumulation Force; the static particle accumulation force and the dynamic particle accumulation force are selected through a set first data selector, and then a first output signal is output to a force writing back module; and the box number where the static particles are positioned and the box number where the dynamic particles are positioned are selected by a set second data selector and then output a second output signal and a third output signal to the force writing back module.

Further, the first accumulator and the second accumulator are accumulation registers, and after the force accumulation of the first accumulator and the second accumulator is completed, static particle accumulation force is output firstly, namely the output result of the first accumulator, and then dynamic particle accumulation force is output, namely the output result of the second accumulator.

Further, the force write-back module comprises a FIFO module and an adder, and the working process is as follows: and reading address information and Force information Force to be written back from a preset FIFO module, reading static particle initial Force and dynamic particle initial Force from a first BRAM module according to the address information, adding the static particle initial Force and static particle accumulation Force to obtain a first resultant Force, adding the dynamic particle initial Force and the dynamic particle accumulation Force to obtain a second resultant Force, and writing the first resultant Force and the second resultant Force back to a space corresponding to the same address of the first BRAM module.

An FPGA prototype verification method includes the following steps:

step 1: the host writes the number of the dynamic particle pairs and the static particle pairs into the control module, and designates the number of the particle pairs to be tested;

step 2: the host writes a starting command into the control module, and the control module sends the received starting command to the PE module;

step 3: the PE module receives a starting command, acquires the number of dynamic particles and static particle pairs from the control module, and starts operation;

step 4: the Force accumulation module accumulates Force information Force of static particles with the same serial number in the PE module to obtain static particle accumulation Force under the same serial number, accumulates Force information Force of dynamic particles with the same serial number to obtain dynamic particle accumulation Force under the same serial number, and transmits the static particle accumulation Force and the dynamic particle accumulation Force to the Force write-back module;

step 5: the force writing back module reads out the initial static particle force and the initial dynamic particle force from the first BRAM module, adds the initial static particle force and the accumulated static particle force to obtain a first resultant force, adds the initial dynamic particle force and the accumulated dynamic particle force to obtain a second resultant force, and writes the first resultant force and the second resultant force back to the first BRAM module;

step 6: the host reads the first resultant force and the second resultant force from the first BRAM module through the BRAM control module.

Compared with the prior art, the technical scheme of the invention has the beneficial effects that:

the invention provides a stable verification system environment by utilizing the FPGA hardware board development platform, thereby avoiding repeated development of a plurality of systems; a plurality of IPs share a prototype verification system;

compared with software simulation and hardware accelerators, the running speed of the FPGA prototype verification system is several orders of magnitude faster; local or some interface logic codes can run according to the frequency which is closer to the real chip, so that the debugging time of software running and the period of verification iteration are greatly shortened, and meanwhile, the development and verification parallelism of software and hardware is possible;

the IP development time is saved, the IP is fast in verification speed of the FPGA prototype verification platform, and the IP debugging time of design software is reduced.

Drawings

The drawings are for illustrative purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

FIG. 1 is a schematic diagram of an FPGA prototype verification system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a control module according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a force accumulation module according to an embodiment of the present invention;

FIG. 4 is a waveform diagram of input/output signals of a force accumulation module according to an embodiment of the present invention;

FIG. 5 is a state diagram of a force accumulation module provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of a force write-back module provided by an embodiment of the present invention;

fig. 7 is a flowchart of an IP prototype verification method according to an embodiment of the present invention.

Detailed Description

Before describing the embodiments of the present application, the following definitions are first given for the relative terms referred to in the embodiments of the present application:

prototypes, in software development, a prototype is a basic, practical model of a product or data system, typically part of the structure of a development program for demonstration purposes. In the System Development Lifecycle (SDLC), a prototype model needs to be designed, i.e. a basic version of the system is built and tested, and modifications are repeated if necessary until a complete and acceptable prototype is achieved.

Direct memory access (DMA, direct Memory Access), which is a function provided by some computer bus architecture, enables data to be sent directly from an attached device (e.g., disk drive) to the memory of a computer motherboard.

XDMA, network structure of multicast stream media transmission, can realize low cost multipoint access.

AXI (Advanced eXtensible Interface) is a bus protocol that is directed to high performance, high bandwidth, low latency on-chip buses.

Xilinx (seiling) is a worldwide leading supplier of programmable logic complete solutions.

Example 1

For ease of understanding, referring to fig. 1, an embodiment of an FPGA prototype verification system provided by the present invention includes: the system comprises an (X86) host and an FPGA hardware board, wherein an XDMA module, a control module, a PE module, a force accumulation module, a force write-back module, a 2-selection-1 module and a BRAM control module which are sequentially connected are arranged on the FPGA hardware board, and the force write-back module and the 2-selection-1 module are both connected with a first BRAM module; wherein, the liquid crystal display device comprises a liquid crystal display device,

the XDMA module is a PCIE DMA transmission IP encapsulated by Xilinx and is used for realizing the conversion of a host and FPGA hardware board card communication protocol;

the control module is connected with an AXI Lite bus of the XDMA module and is used for receiving and analyzing a control instruction sent by the host computer and controlling the operation of the PE module;

the PE module (Processing Element, processing unit) is a molecular dynamics calculation unit and is used for receiving a control instruction analyzed by the control module and calculating output information Force; the Force information Force is forces between dynamic particles and static particle pairs in three directions of a space coordinate axis X, Y, Z, and the forces are respectively expressed by fx, fy and fz;

wherein, particles with different serial numbers do not carry out force accumulation;

the BRAM control module is used for performing read-write control on a first BRAM module of the AXI bus interface;

the first BRAM module is a dual-port RAM memory and is used for storing Force information Force.

It should be noted that, the FPGA hardware board card adopts FPGA VCU128, and the internal modules are all IP implemented in the FPGA, including the IP provided by Xilinx authority and the IP of RTL (register transfer level circuit) code design. The particles refer to atoms or molecules used in the test, and are classified into static particles and dynamic particles according to states, and the number of the static particles and the dynamic particles is arbitrary.

Specifically, the host is provided with a Shell program and a test program, and an XDMA driver is arranged in the test program.

Specifically, the PE module is connected with a second BRAM module, where the second BRAM module is a ROM memory and is used to store an initialization test configuration file and test input data of the PE module.

Specifically, the test program, the XDMA driver, the XDMA module, the first BRAM module, the second BRAM module and the BRAM control module are provided by the Siberian official; the Shell program, the control module, the force accumulation module, the force write-back module and the 2-1 selection module are designed and realized by a user.

As shown in fig. 2, the control module receives and parses a control instruction sent by the host through PCIE, and if the control instruction is to write into the first register, bit 0 of the corresponding data represents a start command signal, and bit 1 represents a reset command signal; if it is the second register that is written, the lower 16 bits of the corresponding data represent the number of dynamic and static particle pairs sent to the PE module.

It should be noted that, the FPGA on-chip memory mainly includes LUTRAM and BRAM. BRAM is a block memory with a minimum unit of 36Kbits or 20Kbits, and has a moderate overall capacity, and is suitable for medium capacity memories.

The embodiment also provides an FPGA prototype verification method, as shown in fig. 7, including the following steps:

step 6: the host reads the first resultant force and the second resultant force from the first BRAM module through the BRAM control module; and further, whether the first resultant force and the second resultant force are consistent with expected values of software simulation or not can be compared.

Example 2

Specifically, the description of the embodiment will be given with reference to specific embodiments on the basis of embodiment 1, so as to further demonstrate the technical effects of the present embodiment. The method comprises the following steps:

the verification flow of the FPGA prototype verification test is as follows:

the host machine is powered off, the FPGA hardware board card is inserted into the PCIE slot of the host machine, the USB cable and the power line are connected, the FPGA hardware board card is powered on, and the host machine is powered on;

starting a vivado comprehensive tool by a host to generate a bit file; downloading the bit file to the FPGA hardware board card through the USB;

restarting a host, and identifying PCIE equipment; after starting the host, inserting an xdma. Ko driver;

viewing the identified PCIE devices and inserted drivers using lspci-vv-sxx:xx commands; and running a test script program.

In this embodiment, the console for the host test is designed to:

an XDMA driver, a test program and a shell program (script) are arranged on the host; the XDMA driver (XDMA. Ko) and the test program (reg_rw, dma_from_dev, dma_to_dev) can download source codes from the Xilinx official and compile the source codes; the reg_rw command realizes the reading and writing operation of the host computer on the register on the FPGA hardware board card; the dmafromdev command realizes batch reading of data (DMA reading) from the FPGA hardware board card by the host; the dmato dev command enables the host to write data in batches (DMA write) to the FPGA hardware board.

The control module and the memory space of the FPGA hardware board card can be accessed by using the test program command provided by the Xilinx; by writing shell scripts and combining the test commands, the test verification process of the PE module is realized; the test flow is as follows:

1) Resetting PCIE: firstly removing PCIE equipment corresponding to the FPGA hardware board card, then rescanning, identifying PCIE equipment corresponding to the FPGA hardware board card again, and distributing PCIE space; the operation can identify PCIE equipment without restarting the host after re-programming the FPGA hardware board (generally, the address space of PCIE is allocated when the host is started);

2) Resetting the PE module: writing 1 into the 1 st bit of the first register, and resetting the PE module; after 1 second, clearing reset; initializing a second BRAM module: writing initial data to a force address space in a second BRAM;

3) Writing the number of particle pairs to be tested into a second register;

4) And (3) starting a test: writing 0 into the 0 th bit of the first register, and then writing 1 to generate a rising edge waveform, and starting PE module test operation;

5) Recovering test results: reading data from a force address space in the second BRAM module and writing the data into a set file;

6) Comparing the test results with expected data: the diff command is used to compare the test results with expected data, which is the result of the software test run.

Example 3

In this embodiment, as shown in fig. 3, the input/output interface signals of the force accumulation module are:

a first input signal representing a serial number of the static particles in the box; if 32 particles are stored in each box at maximum, each particle has a serial number in the box, the value range is 1-32, and the number of the particles with the same serial number is any number; according to the sequence number, the relative position of Force information Force corresponding to the particle in the second BRAM module can be obtained;

a second input signal representing the sampled signal (i.e. a combined signal), wherein:

the second input signal [6:0] represents the number of static particles;

the second input signal [13:7] represents the number of dynamic particles;

the second input signal [22:14] represents a box number where the static particle is located, and is used for calculating the initial position of Force information Force corresponding to the static particle in the second BRAM module according to the box number where the static particle is located;

the second input signal [31:23] represents a box number where the dynamic particle is located, and is used for calculating the initial position of Force information Force corresponding to the dynamic particle in the second BRAM module according to the box number where the dynamic particle is located;

a first output signal representing the accumulated Force information Force;

a third output signal representing box number information;

specifically, according to the serial number of the static particles in the box, force information Force and the number of the static particles, carrying out Force accumulation of the static particles in a set first accumulator to obtain static particle accumulation Force;

The first accumulator and the second accumulator are accumulation registers, and after the force accumulation of the first accumulator and the second accumulator is finished, static particle accumulation force is output. The box number information is the box number where the dynamic particles are located and the box number where the static particles are located.

In this embodiment, as shown in fig. 4, clk is an input signal in the waveform diagram of the input/output signal of the force accumulation module, which represents a system clock signal; a low level and a high level together represent a clock cycle, and the horizontal axis represents the time sequence. The other signals are all inputs or outputs relative to the system clock signal clk, being asserted on the rising edge (from low to high) of the system clock signal clk;

at time t0, when the box valid signal is valid at high level, the sampling signal (second input signal) is valid; for example, the sampling value is 0x3223, corresponding to:

sampling signal [6:0] =3;

sampling signal [13:7] =4;

sampling signal [22:14] =8;

sampling signal [31:23] =6;

at time t1, when the force effective signal is effective, the first accumulator and the second accumulator respectively accumulate static particle force and dynamic particle force; d0 to d3 of the Force information Force input signal input corresponds to the Force between the No. 1 static particle and the No. 1 to 4 dynamic particle, d4 to d7 corresponds to the Force between the No. 2 static particle and the No. 1 to 4 dynamic particle, and d8 to d11 corresponds to the Force between the No. 3 static particle and the No. 1 to 4 dynamic particle; the force accumulation results are as follows:

force after static particle 1 accumulation: fs0=d0+d1+d2+d3

Force after accumulation of static particles 2: fs1=d4+d5+d6+d7

Force after accumulation of static particles 3: fs2 = d8+ d9+ d10+ d11

Force after accumulation of dynamic particle 1: f0=d0+d4+d8

Force after accumulation of dynamic particles 2: f1=d1+d5+d9

Force after accumulation of dynamic particles 3: f2=d2+d6+d10

Force added by dynamic particle 4: f3=d3+d7+d11.

After the Force accumulation is completed, at the time t2, outputting static particle Force information Force effectively, namely outputting the forces fs 0-fs 2 of the static particles; outputting forces ff 0-ff 3 of the dynamic particles at the time t 3; the cassette number and the position number of the particle in the cassette are followed, respectively, when the Force information Force is output.

In this embodiment, as shown in the force accumulation module state diagram of fig. 5, wherein,

s0 state: waiting for receiving the box valid signal, and entering a next state S1 if the box valid signal is valid;

s1 state: waiting for a force effective signal, and entering an S2 state if the force effective signal is effective;

s2 state: performing force accumulation operation until the last force is accumulated (last=1), wherein the accumulated force is respectively stored in a static particle accumulation force register array and a dynamic particle accumulation force register array, and the subscript of the arrays is assigned to 0 in an S0 state;

s3 state: outputting static particle accumulation force;

s4 state: outputting a dynamic particle accumulation force;

s5, state: the end jumps back to the S0 state.

In this embodiment, as shown in fig. 6, the force write-back module includes a FIFO (First In First Out first-in first-out buffer) module, an adder, and the force to be written back and the related information thereof are stored in the FIFO module for buffering, and the working process is as follows: reading address information addr and Force information Force to be written back from a preset FIFO module, reading first data rdata from a first BRAM module according to the address information addr, adding static particle initial Force and static particle accumulation Force to obtain a first resultant Force, adding dynamic particle initial Force and dynamic particle accumulation Force to obtain a second resultant Force (namely second data wdata), and writing the first resultant Force and the second resultant Force back to a space corresponding to the same address addr of the first BRAM module;

wherein the first data rdata represents the static particle initial force and the dynamic particle initial force read out from the first BRAM module.

It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.

Claims

1. An FPGA prototype verification system, comprising: the system comprises a host and an FPGA hardware board, wherein an XDMA module, a control module, a PE module, a force accumulation module, a force write-back module, a 2-selection-1 module and a BRAM control module which are sequentially connected are arranged on the FPGA hardware board, and the force write-back module and the 2-selection-1 module are both connected with a first BRAM module; wherein, the liquid crystal display device comprises a liquid crystal display device,

2. The FPGA prototype verification system as claimed in claim 1, wherein said host is provided with a Shell program and a test program, and an XDMA driver is provided in the test program.

3. The FPGA prototype-verification system as claimed in claim 2, wherein said PE module is connected to a second BRAM module, said second BRAM module being a ROM memory for storing an initialization test configuration file and test input data of the PE module.

4. A FPGA prototype verification system according to claim 3, wherein said test program, XDMA driver, XDMA module, first BRAM module, second BRAM module, BRAM control module are provided by the siren authority; the Shell program, the control module, the force accumulation module, the force write-back module and the 2-1 selection module are designed and realized by a user.

5. The FPGA prototype verification system as claimed in claim 1, wherein said control module specifically works as: the control module receives and analyzes a control instruction sent by the host through PCIE, and if the control instruction is written into the first register, the 0 th bit of corresponding data represents a starting command signal, and the 1 st bit represents a resetting command signal; if it is the second register that is written, the lower 16 bits of the corresponding data represent the number of dynamic and static particle pairs sent to the PE module.

6. The FPGA prototype verification system as claimed in claim 1, wherein said force accumulation module input/output interface signals are:

a second input signal representing a sampled signal;

a first output signal representing the accumulated Force information Force;

a third output signal representing box number information;

wherein the second input signal comprises: the number of static particles and the number of dynamic particles;

and the box number where the dynamic particle is positioned is used for calculating the initial position of the Force information Force corresponding to the dynamic particle in the second BRAM module according to the box number where the dynamic particle is positioned.

7. The FPGA prototype verification system as claimed in claim 6, wherein said force accumulation module operates as: according to the serial number of the static particles in the box, force information Force and the number of the static particles, carrying out Force accumulation on the static particles in a set first accumulator to obtain static particle accumulation Force;

8. The FPGA prototype-verification system as claimed in claim 7, wherein said first accumulator and said second accumulator are accumulation registers, and after the force accumulation of said first accumulator and said second accumulator is completed, the static particle accumulation force is output, i.e. the output result of said first accumulator, and then the dynamic particle accumulation force is output, i.e. the output result of said second accumulator.

9. The FPGA prototype verification system as claimed in claim 8, wherein said force write back module comprises a FIFO module, an adder, and the working process is: and reading address information and Force information Force to be written back from a preset FIFO module, reading static particle initial Force and dynamic particle initial Force from a first BRAM module according to the address information, adding the static particle initial Force and static particle accumulation Force to obtain a first resultant Force, adding the dynamic particle initial Force and the dynamic particle accumulation Force to obtain a second resultant Force, and writing the first resultant Force and the second resultant Force back to a space corresponding to the same address of the first BRAM module.

10. The FPGA prototype verification method is characterized by comprising the following steps of: