CN104811259B - A kind of satellite communication frequency deviation verification method - Google Patents
A kind of satellite communication frequency deviation verification method Download PDFInfo
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- CN104811259B CN104811259B CN201510127543.4A CN201510127543A CN104811259B CN 104811259 B CN104811259 B CN 104811259B CN 201510127543 A CN201510127543 A CN 201510127543A CN 104811259 B CN104811259 B CN 104811259B
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Abstract
The present invention relates to a kind of satellite communication frequency deviation verification method, belongs to special IC verification technique field.The method is for the frequency deviation module in satellite communication baseband chip, architecture of the popular OVM verification methodologies as checking system with current integrated circuit verification, to incorporate wherein based on transaction validation technology, Coverage- Driven verification technique and based on the verification technique that asserts, and associative simulation is carried out with C algorithm models, realize automation contrast and continuous simulation, verification efficiency is improved, shortens proving period.This verification method achieves the functional verification of satellite communication baseband chip frequency deviation module, improves the verification efficiency of frequency deviation module, it is possible to play considerable effect in the success of the disposable flow of satellite communication baseband chip.
Description
Technical field
The invention belongs to special IC verification technique field, is related to a kind of satellite communication frequency deviation verification method.
Background technology
In asic chip development process, the time required for functional verification often accounts for the 70% of whole chip development time
More than, the abstract level for often designing is higher, and design is simpler, but the design leak for producing simultaneously but may be more, such as
Fruit is the defect on framework, then the infringement to chip is even more imponderable, therefore the functional simulation checking before flow
For whole verification process is exactly the most important thing.
The functional verification technology for being currently based on emulation mainly has following three kinds：Transaction based verification technology, based on cover
Rate drive verification technique, based on the verification technique that asserts.Technology based on affairs mainly will by transaction validation model TVM
The other information of transaction-level is converted into the signal level digital information required for authentication module, and drives it in test module with complete
The functional verification of tested module in pairs, it is with transaction validation model TVM (Transaction Verification Model)
For core, transaction validation model is by being converted into the signal level that tape test design is wanted by existing transaction-level test case
Information, this verification method need not formulate specific agreement, it is only necessary to define the transmission direction of signal, with fine
Durability, but when the function of design to be measured is differed, the interface type of needs and quantity may be differed, at this moment
Need multiple different checking models to meet checking demand.During functional verification, coverage rate is to weigh to have verified whether
A standby major criterion, and through whole verification process.It is exactly to pass through in checking based on the verification technique of Coverage- Driven
During the function coverage of module to be measured and code coverage information are carried out counting and then judging module to be measured whether just
Really feasible, and an important indicator in formulating as the demonstration plan for instructing next step.But this verification technique needs fixed
Adopted functional coverage point, and whether the covering point that defines is complete is accomplished by having certain understanding to module to be measured, with design scale
With the continuous improvement of complexity, functional coverage point is also more and more, and this is accomplished by constantly having carried out to covering point in the verification
The kind demand to meet design and checking.Mainly asserted come quick fixed by insertion in design to be measured based on the checking that asserts
The method of the mistake in the design of position is improving the efficiency of checking.But external function attribute of this verification technique to test module
Verification efficiency improve less, be only applicable to the function of validation test inside modules, and the verification technique driven based on clock
Dynamic, therefore it is also not suitable for the functional verification of the design module unrelated with clock.
Content of the invention
In view of this, it is an object of the invention to provide a kind of satellite communication frequency deviation verification method, the method is for satellite
Frequency deviation module in communications baseband chip, with current integrated circuit verification, popular OVM verification methodologies are checking system
The architecture of system, will be incorporated based on transaction validation technology, Coverage- Driven verification technique and based on the verification technique that asserts
Wherein, and with C algorithm models associative simulation is carried out, realizes automation contrast and continuous simulation, improve verification efficiency, shorten checking
Cycle.
For reaching above-mentioned purpose, the present invention provides following technical scheme：
A kind of satellite communication frequency deviation verification method, comprises the following steps：
Step one：Using in OVM verification methodologies, tree structure is built basic as the architecture of whole checking system
Checking system framework；In OVM tree structures, each OVC (Open Verification Component) component is the section in tree
Point, these OVC components include Environment, Agent, Monitor, Driver, Sequencer, Reference,
Scoreboard etc., the node that wherein sets are divided into father node and child node again, can be with sound in the OVC components representated by father node
OVC components representated by bright newly-built child node realize checking assembly as its built-in variable by this method for controlling layer by layer
In co-ordination.
Step 2：Transaction-level data item (item) is defined according to the functional character of satellite communication chip frequency deviation module, this
A little transaction-level data item are realized by the class in System Verilog checking language, can be defined if there are specific demand many
Individual Transaction Information item, to facilitate follow-up checking work, needs exist for defining two Transaction Information items, and one is used for transmitting frequency deviation
The parameter configuration of module, a use automate the output data required for contrast, i.e. self-inspection later.
Step 3：According to the port signal of frequency deviation module, defining interface interface, it is easy to checking system and to be measured sets
Communication between meter, reduces the possibility of signal connection error.
Step 4：As the variable of DPI transmission needs two definition for matching, one is System Verilog,
One is C language, therefore according to frequency deviation module port signal, on the premise of C algorithms are not changed, by the configuration in C algorithms
Parameter Switch, into the data type for verifying correspondence mappings relation in language with System Verilog, is that DPI below is called and done
Prepare.
Step 5：According to frequency deviation functions of modules feature, storehouse, definition is created as desired in Driver or Monitor
Covering group and covering point, and instantiate.
Step 6：The top layers of whole checking system are designed, in the definition that top layers need to realize global variable, clock clk
Generation, C algorithms DPI statement, mutual between the example between checking system and design to be measured, checking system and design to be measured
Even, the startup of the initial work of design to be measured and checking system.
Step 7：Test case is added according to checking target, is oriented and random test.
Further, in step 5, supervision and check are needed if there are specific sequential, can increase and assert and detected.
The beneficial effects of the present invention is：Compared with traditional checking system or method, this method is with OVM verification methods
Basic framework of the tree structure in for checking system, and the verification method of some current main flows is incorporated, including based on thing
The verification method of business, the verification method based on Coverage- Driven and based on verification method that asserts etc., it is achieved that satellite communication
The functional verification of baseband chip frequency deviation module, improves the verification efficiency of frequency deviation module, it is possible in satellite communication baseband chip
Disposable flow success in play considerable effect.
Description of the drawings
In order that the purpose of the present invention, technical scheme and beneficial effect are clearer, the present invention provides drawings described below and carries out
Explanation：
Fig. 1 is the OVM tree structure figures in the present invention in checking system；
Fig. 2 is checking system Organization Chart in the present invention；
Fig. 3 is checking system execution flow chart in the present invention.
Specific embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described in detail.
Fig. 1 is the OVM tree structure figures in the present invention in checking system, as shown in the figure：
With the frequency deviation module verification system of the tree structure of OVM with apparent subordinate relation, during this is to checking system
Transaction Information transmission management critically important, reasonably can arrange in tree structure as between the OVC components of node
Data transfer.Here node is divided into two kinds, father node and child node, can state one or more child nodes in father node
Representative OVC components and as built-in variable, so realized between each OVC components by progressive method
Co-ordination, enables whole checking system rationally effectively to run.OVC components in OVM tree structures specifically built
Journey is as follows：
1., as shown in Figure 1 in whole OVM tree structures figure, Env is top by all of OVC component integrations to
Rise, in Env, it is necessary first to which child node is stated, this OVC component representated by a little byte point include Agent,
Reference, Scoreboard, due to needing the configuration for carrying out some parameters to frequency deviation module to be measured in checking system, and
And frequency deviation checking system needs, when running, detection that frequency deviation module operation result is exercised supervision, so needing two difference agent.
Secondly need to state the FIFO that OVM places are carried in Env, and these OVC components are coupled together by FIFO, connected mode
Carried out by the specific port of OVM, allow them to carry out normal transaction-level communication.
2. when Env structure after the completion of, need to carry out pattern configurations to Agent, need in Agent to Driver,
Sequencer, Monitor and the desired port of transaction-level data transfer are defined statement, when checking system needs to produce
Or send frequency deviation module startup optimization needed for data when, Agent is configured to ACTIVE patterns, it is right to complete in this mode
The example of Sequencer and Driver, now Monitor be in off working state, when need capture frequency deviation module output knot
During fruit, Agent is configured to PASSIVE patterns, Monitor modules can be instantiated in this mode, be row when checking system is transported
The output result of monitoring frequency deviation module to be measured is laid the groundwork.After this instantiation work for completing these child nodes, it is necessary to root
According to the pattern of the Agent for being configured, it is connected on Interface interfaces, checking system is carried out with frequency deviation module
The interaction of normal data.
3. Agent for the pattern of ACTIVE when, need to carry out frequency deviation module to be measured the configuration of some parameters and
The initial work of data, these are all carried out by Driver.Therefore, need to transmit in OVC components in Driver
Transaction level information be converted into the required level or pulse signal of frequency deviation module, these level or pulse signal need
Meet the timing requirements of frequency deviation module to be measured, can normally drive frequency deviation module to be measured, this part pass through one
A little task go to realize.Meanwhile, some functional coverage groups can be added in the assembly to being input to the parameter sum of frequency deviation module
Count according to covering point is carried out.
4. parameter configuration data and calculating data required for whole checking system is all produced by Sequence, when
When Driver needs data, transaction-level request of data can be sent to Sequencer, Sequencer will pass through to drive after receiving
Sequence produces data, and after producing the data required for these, then Sequencer this bridge passes it to Driver.
Multiple Sequence can be designed in whole checking system, different Sequence can produce different excited datas to treating
The frequency deviation module of survey, Sequence can be by the grand transaction-levels to determine generation such as ovm_do of OVM or ovm_do_with
The content of data.
5.Monitor is primarily used to the output for monitoring frequency deviation module, and the output result of collection is sent by port
To the comparison that Scoreboard carries out result, thus in the module firstly the need of by Interface interfaces to frequency to be measured
The output result of module partially is collected, and this process needs to be carried out according to the timing requirements of frequency deviation module, may otherwise cause
The result that collects is incorrect, secondly after the operation result for collecting frequency deviation module, as these operating structures are all signal levels
Information, therefore need to convert thereof into the transaction level information required for checking system, the above process can pass through
Task goes to complete.
6. reference model Reference is the model for simulating frequency deviation module to be measured, therefore it needs and frequency deviation module phase
Same input, is completed and frequency deviation module identical calculating process by these inputs, and the result of calculating is sent to
Scoreboard.So first having to the port interacted with Agent and Scoreboard, the transmission of transaction level information is carried out, when
After checking system starts, under the agent patterns of ACTIVE, driver can use the intrinsic function of OVM, by the data of transaction-level
Reference is sent to by port and participates in calculating, after reference completes to calculate, result is being sent to by port
Scoreboard.Secondly, in the part, reference model can be that SystemVerilog writes, or other senior languages
Speech is write, it is preferred that C or C++, because only have C and C++ be embedded into by DPI being at present based on
In the checking system of SystemVerilog checking language, after completing the collaboration test of frequency deviation module and reference model to be measured, need
The result calculated in reference model is converted into transaction level information.
7. checking system is gone to judge frequency by the result that Scoreboard contrast Monitor and Reference are sended over
Whether the design of module partially is reasonable, therefore similarly needs to define two port acceptance from Monitor and Reference respectively
Affairs DBMS, needs to export comparison result after the result of frequency deviation module to be measured and reference model has been compared, and correct needs are just
True conclusion, if mistake, needs the debug in the data write file that will be stored in top layer array, to next step
Help is provided.
After completing in OVM tree structures a design of OVC components, as shown in Figure 2, in addition it is also necessary to whole checking system other
Module be designed perfect, including in checking system transmit transaction information definition, the definition of Interface interfaces, such as
What adds in the verification covers point, and the Top-layer Design Method of whole checking system, testing example design etc., and which specifically designs
Method is as follows：
1. the definition of transaction information：Affairs Transaction are the matchmakers of data transfer between OVC components in checking system
It is situated between, these affairs are all to be derived from ovm_sequence_item class libraries, including all of intrinsic function and variable.Frequency deviation is verified
In system, need to define two Transaction affairs, parameter configuration and a sampled point for being used for transmitting frequency deviation module
Data, a use realize automation contrast, i.e. output data required for self-inspection later.Wherein, first affairs
Transaction, that is, the affairs for being used for transmitting configuration parameter are all by the generation that produces in Sequence and pack, and are generating
Need to require to go to carry out appropriate constraint to the transaction information for producing with the algorithm according to frequency deviation module during the transaction information of this class.
Equations of The Second Kind affairs are produced in Reference, are converted into by the data message of the frequency deviation module by collection in Reference
Equations of The Second Kind transaction information is simultaneously sent to Scoreboard and carries out Data Comparison.
2. the definition of interface and the design of top layer：Interface Interface directly can be carried out according to the port of frequency deviation module
The part in language with regard to Interface definition is verified in definition, the method for definition with reference to SystemVerilog.Entirely verifying
The top layer of system needs the definition for realizing global variable, the generation of clock clk, the DPI statements of C algorithm models, interface
Interconnection, the initial work of frequency deviation module and checking system between the instantiation of interface, checking system and frequency deviation module
The startup of system and the statement of array, the array are used for storing frequency deviation module each run desired data.
3. test case is write：Test case in checking system is all derived from ovm_test class libraries, can in design
The design of base class base_test is first completed, such can equally be derived from ovm_test, OVM trees are mainly completed in this base class
The decision of the time run by the instantiation work of shape checking framework and functional simulation, the latter can go to realize by task.?
When designing specific test case, it is only necessary to which deriving subclass from base_test base class just can be with, but in each subclass
It is first produced by which checking scene, that is, checking system to need acquiescence Sequence for confirming Sequencer
Class transaction information.
4. the design and the design that asserts of point are covered：In whole frequency deviation checking system, it is to sentence whether complete to cover point
A whether complete major criterion of disconnected frequency deviation module verification, create covering group when must strictly with the institute according to frequency deviation module
The function of realizing is needed to go to define the content in covering group, the intersection between covering and multiple functions including individual feature is covered
Lid.According to the actual requirements, the configuration of frequency deviation module will can be joined in Driver or Monitor in embedded for covering group OVC components
Number and output result carry out function coverage collection.If have particular requirement to the sequential of frequency deviation module port signal, can be
Add in Interface in checking in system and assert whether the sequential to judge signal meets the requirements, specific design can basis
Assertion technology in the port sequential of frequency deviation module to be measured and systemVerilog checking language.
After completing the component design required for above checking system, whole checking system just normally can be run, checking system
It is as shown in Figure 3 that system executes flow process.Test case is produced by OVM_TETSNAME, and is instantiated and is completed OVM tree architectures, and root
According to the OVC components representated by each node in tree structure instantiation and component between connection procedure, these processes are all
Intrinsic function build () that carried by OVM places and connect () are completing.The startup of whole checking system can pass through
Makefile scripts go to complete, the compiling, operation including checking system and frequency deviation module to be measured.
Finally illustrate, preferred embodiment above is only unrestricted in order to technical scheme to be described, although logical
Cross above preferred embodiment to be described in detail the present invention, it is to be understood by those skilled in the art that can be
In form and various changes are made to which in details, without departing from claims of the present invention limited range.
Claims (3)
1. a kind of satellite communication frequency deviation verification method, it is characterised in that：Comprise the following steps：
Step one：Using in OVM verification methodologies, tree structure builds basic checking as the architecture of whole checking system
System framework；
Step 2：Transaction-level data item is defined according to the functional character of satellite communication chip frequency deviation module；
Step 3：According to the port signal of frequency deviation module, defining interface interface, be easy to checking system and design to be measured it
Between communication, reduce signal connection error possibility；
Step 4：According to frequency deviation module port signal, on the premise of C algorithms are not changed, the configuration parameter in C algorithms is changed
Into the data type for verifying correspondence mappings relation in language with System Verilog, it is that DPI below is called and prepared；
Step 5：According to frequency deviation functions of modules feature, storehouse is created as desired in Driver or Monitor, definition is covered
Group and covering point, and instantiate；
Step 6：The top layers of whole checking system are designed, in the definition that top layers need to realize global variable, the product of clock clk
Raw, DPI statements of C algorithms, between the instantiation between checking system and design interface to be measured, checking system and design to be measured
The startup of interconnection, the initial work of design to be measured and checking system；
Step 7：Test case is added according to checking target, is oriented and random test.
2. a kind of satellite communication frequency deviation verification method according to claim 1, it is characterised in that：In step 2, according to
The functional character of satellite communication chip frequency deviation module defines transaction-level data item (item), and these transaction-level data item pass through
Class in System Verilog checking language can define multiple Transaction Information items according to real needs, with convenient realizing
Follow-up checking work；Need exist for defining two Transaction Information items, a parameter configuration for being used for transmitting frequency deviation module,
One use automates the output data required for contrast, i.e. self-inspection later.
3. a kind of satellite communication frequency deviation verification method according to claim 1, it is characterised in that：In step 5, if
There is specific sequential to need supervision and check, can increase and assert and detected.
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| CN101527917A (en) * | 2008-03-04 | 2009-09-09 | 上海摩波彼克半导体有限公司 | Circuit structure of digital baseband chip on mobile equipment for realizing digital authentication |
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