CN109948306B

CN109948306B - Integrated simulation system

Info

Publication number: CN109948306B
Application number: CN201910366068.4A
Authority: CN
Inventors: 沈佑良
Original assignee: Wuxi Xijie Microelectronics Co ltd
Current assignee: Wuxi Xijie Microelectronics Co ltd
Priority date: 2019-05-05
Filing date: 2019-05-05
Publication date: 2024-02-02
Anticipated expiration: 2039-05-05
Also published as: CN109948306A

Abstract

The invention provides an integrated simulation system, which comprises a computer, an FPGA digital circuit module, a plurality of simulation modules, a chip program memory, a user simulation program memory and a user test port, wherein the FPGA digital circuit module is used for storing a plurality of simulation modules; the computer is connected with the FPGA digital circuit module, and the FPGA digital circuit module is respectively connected with the chip program memory, the user simulation program memory and the user test port; each simulation module is arranged in a chip in a streaming manner and is respectively connected with the FPGA digital circuit module; the FPGA digital circuit module is used for realizing a digital logic circuit of the simulation chip; the simulation modules are used for realizing the simulation part circuit of the simulation chip. For simulation of a plurality of actual chips, the simulation system can be realized only by using one set of simulation system, multiple streaming is not needed, and the streaming cost and risk are reduced.

Description

Integrated simulation system

Technical Field

The invention relates to the technical field of chip simulation, in particular to an integrated simulation system.

Background

In the traditional simulation system based on the simulation chip, one simulation chip is corresponding to one actual chip, and a plurality of actual chips are needed to simulate, so that not only is very expensive film-flowing cost needed, but also a very long film-flowing period is needed, and a design company is also required to bear a certain film-flowing risk, thereby being unfavorable for the rapid popularization of the chips.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide an integrated simulation system, which can realize the simulation of a plurality of actual chips by using one set of simulation system without multiple streaming, thereby reducing the streaming cost and risk. The technical scheme adopted by the invention is as follows:

an integrated simulation system comprises a computer, an FPGA digital circuit module, a plurality of simulation modules, a chip program memory, a user simulation program memory and a user test port;

the computer is connected with the FPGA digital circuit module, and the FPGA digital circuit module is respectively connected with the chip program memory, the user simulation program memory and the user test port; each simulation module is arranged in a chip in a streaming manner and is respectively connected with the FPGA digital circuit module;

the FPGA digital circuit module is used for realizing a digital logic circuit of the simulation chip; the simulation modules are used for realizing the simulation part circuit of the simulation chip.

Further, the simulation modules comprise a GPIO simulation module, an LVD reset simulation module, an external crystal oscillator simulation module, a comparator simulation module, an ADC simulation module and an EEPROM simulation module.

Further, the chip program memory is used for storing a chip circuit program for realizing the simulation chip logic circuit.

Further, the user simulation program memory is used for storing a user simulation program for realizing the function of the simulation chip.

Further, the chip program memory adopts a power-down memory.

Further, the user emulation program memory employs a power-down volatile memory.

Further, when the actual chip is simulated, the circuit program of the actual chip is downloaded to the chip program memory from the computer, the internal logic connection of the simulated chip is realized through the FPGA digital circuit module, and the simulation result is output from the user test port;

the simulation chip comprises an FPGA digital circuit module, a plurality of simulation modules, a chip program memory and a user simulation program memory in the simulation system.

The invention has the advantages that:

1) Compared with a pure FPGA-based simulation system, the simulation system provided by the invention can simulate the circuit function which cannot be simulated by the FPGA after the simulation module is streamed, and has more accurate simulation results.

2) For simulation of a plurality of actual chips, the simulation system does not need to flow the chips for a plurality of times, greatly reduces the cost and risk of flow the chips, and is more convenient to use.

Drawings

FIG. 1 is a schematic diagram of the structural composition of the present invention.

Detailed Description

The invention will be further described with reference to the following specific drawings and examples.

As shown in fig. 1, the integrated simulation system provided by the invention comprises a computer 1, an FPGA digital circuit module 2, a plurality of simulation modules 3, a chip program memory 4, a user simulation program memory 5 and a user test port 6;

the computer 1 is connected with the FPGA digital circuit module 2 through a USB circuit, and the FPGA digital circuit module 2 is respectively connected with the chip program memory 4, the user simulation program memory 5 and the user test port 6; each simulation module 3 is arranged in a chip in a streaming manner and is respectively connected with the FPGA digital circuit module 2;

the FPGA digital circuit module 2 is used for realizing a digital logic circuit of the simulation chip; the plurality of simulation modules 3 are used for realizing a simulation part circuit of a simulation chip;

the simulation modules 3 comprise GPIO simulation modules, LVD reset simulation modules, external crystal oscillator simulation modules, comparator simulation modules, ADC simulation modules and EEPROM simulation modules;

the chip program memory 4 is used for storing a chip circuit program, and the chip circuit program realizes a logic circuit of a simulation chip, for example, the FPGA digital circuit module 2 is respectively connected with a GPIO simulation module, an external crystal oscillator simulation module and an ADC simulation module; the chip program memory 4 adopts a FLASH memory which can be memorized when power is lost;

the user simulation program memory 5 is used for storing a user simulation program, and the user simulation program realizes the functions of a simulation chip, such as a signal sampling program or a PWM signal control program of a driving motor; the user simulation program memory 5 employs a power-down volatile memory, such as SRAM;

the invention integrates the simulation modules of the plurality of chips and then flows the chips, thereby greatly reducing the cost of the flow chips and simulating the plurality of chips; each simulation module 3 is realized by a corresponding hardware circuit, and the simulation modules are integrated and then flow together to form a chip, so that simulation of various actual chips can be supported;

for example, the actual chips needing simulation include an A chip, a B chip, a C chip and a D chip; the chip A resource is GPIO+LVD reset+external crystal oscillator; the chip B resources are GPIO+LVD reset+external crystal oscillator+comparator; the C chip resource is GPIO+LVD reset+external crystal oscillator+ADC; the D chip resource is GPIO+LVD reset+external crystal oscillator+EEPROM;

when the A chip is simulated, the circuit program of the A chip is downloaded to the chip program memory 4 from the computer 1, and the internal logic connection of the simulation chip is realized through the FPGA digital circuit module 2, for example, the FPGA digital circuit module 2 is connected with the GPIO simulation module, the LVD reset simulation module and the external crystal oscillator simulation module; the FPGA digital circuit module 2 is a field programmable gate array, and can realize the field change of a circuit according to a program; in the simulation system, the FPGA digital circuit module 2, the plurality of simulation modules 3, the chip program memory 4 and the user simulation program memory 5 can be regarded as a simulation chip with changeable internal circuits and chip resources; the simulation result is output from the user test port 6. And the simulation can be carried out on the chip B, the chip C and the chip D in the same way.

Some terms related to the present invention are explained as follows:

GPIO-general purpose input/output port.

LVD reset-low voltage sense reset.

ADC- -analog-to-digital conversion.

FPGA-field programmable gate array.

Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.

Claims

1. The integrated simulation system is characterized by comprising a computer (1), an FPGA digital circuit module (2), a plurality of simulation modules (3), a chip program memory (4), a user simulation program memory (5) and a user test port (6);

the computer (1) is connected with the FPGA digital circuit module (2), and the FPGA digital circuit module (2) is respectively connected with the chip program memory (4), the user simulation program memory (5) and the user test port (6); each simulation module (3) is arranged in a chip in a streaming manner and is respectively connected with the FPGA digital circuit module (2);

the FPGA digital circuit module (2) is used for realizing a digital logic circuit of the simulation chip; the simulation modules (3) are used for realizing simulation part circuits of a simulation chip;

the simulation modules (3) comprise GPIO simulation modules, LVD reset simulation modules, external crystal oscillator simulation modules, comparator simulation modules, ADC simulation modules and EEPROM simulation modules;

the chip program memory (4) is used for storing a chip circuit program for realizing the simulation chip logic circuit;

the user simulation program memory (5) is used for storing a user simulation program for realizing the function of the simulation chip;

the chip program memory (4) adopts a power-down memory; the user simulation program memory (5) is a power-down volatile memory.

2. The integrated simulation system of claim 1, wherein,

when an actual chip is simulated, a circuit program of the actual chip is downloaded to a chip program memory (4) from a computer (1), the internal logic connection of the simulated chip is realized through an FPGA digital circuit module (2), and a simulation result is output from a user test port (6);

the simulation chip comprises an FPGA digital circuit module (2), a plurality of simulation modules (3), a chip program memory (4) and a user simulation program memory (5) in the simulation system.