CN104426511A - Technical mapping method and integrated circuit for automatically generating global asynchronous reset signals - Google Patents
Technical mapping method and integrated circuit for automatically generating global asynchronous reset signals Download PDFInfo
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- CN104426511A CN104426511A CN201310368651.1A CN201310368651A CN104426511A CN 104426511 A CN104426511 A CN 104426511A CN 201310368651 A CN201310368651 A CN 201310368651A CN 104426511 A CN104426511 A CN 104426511A
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Abstract
The invention relates to a technical mapping method and integrated circuit for automatically generating global asynchronous reset signals. The method comprises the following steps: according to different RTL writing ways in a user design, correspondingly mapping registers; and performing logic operation on the mapped registers, mapping no-and/or asynchronous-and/or synchronous reset signals in the registers to form the global asynchronous reset signals, and performing global resetting through the global asynchronous reset signals, wherein the global asynchronous reset signals are effective in low level. According to the invention, it can be ensured that all the registers in an FPGA chip can obtain the global asynchronous reset signals, the design stability is guaranteed, and the cross-platform transportability of the design can also be ensured.
Description
Technical field
The present invention relates to the process mapping method of asynchronous reset signal, be specifically related in fpga chip, a kind of process mapping method of automatic generation Global Asynchronous reset signal and integrated circuit.
Background technology
At many FPGA(Field-Programmable Gate Array, i.e. field programmable gate array) design in, need to guarantee that register is started working from the state that is determined, therefore need to carry out unified reset operation to the register that fpga chip uses, can by electrification reset functional realiey time reset operation is most.But the electrification reset implementation of existing fpga chip is had nothing in common with each other, even some chip does not have electrification reset function at all, or electrification reset function is also unstable, thus an application design depending on electrification reset function is made to be difficult to realize cross-platform transplanting.
Design a kind of process mapping method that can carry out Global Asynchronous reset to fpga chip, can obtain Global Asynchronous reset signal, the stability of design and the cross-platform portability of design to reach whole register in design, be problem demanding prompt solution.
Summary of the invention
The object of this invention is to provide a kind of process mapping method and the integrated circuit that realize Global Asynchronous reset signal, unstable with the fpga chip design solved under prior art, can not the problem of cross-platform transplanting.
For achieving the above object, the invention provides a kind of reset signal source generated based on a known outside or inside, automatically add the method for the asynchronous reset signal of the upper overall situation for registers whole in design.When reset signal source is consistent with the signal waveform of electrification reset, the whole registers in design can be guaranteed to obtain electrification reset function, both ensure that the stability of design, also can ensure the cross-platform portability designed.
In first aspect, the invention provides a kind of process mapping method of automatic generation Global Asynchronous reset signal, comprising: go out register according to different RTL literary style correspondence mappings in user's design; Logical operation is carried out to the register mapped out, by in register without and/or asynchronous and/or synchronous reset signal be mapped to Global Asynchronous reset signal, Global reset is carried out, wherein said Global Asynchronous reset signal Low level effective by this Global Asynchronous reset signal.
In second aspect, the invention provides a kind of integrated circuit of automatic generation Global Asynchronous reset signal, comprise: nothing and/or register that is asynchronous and/or synchronous reset signal, as the logical circuit of logical operation, be coupled to the Global Asynchronous reset signal of register control end; Wherein, by register without and/or asynchronous and/or synchronous reset signal be mapped to Global Asynchronous reset signal by logical circuit, described Global Asynchronous reset signal carries out Global reset.
The invention solves traditional design unsteadiness and cross-platform not portable problem, employ less general-purpose device, the automatic generation achieving Global Asynchronous reset signal of low cost, maintains the stability of design.
Accompanying drawing explanation
Fig. 1 is the process mapping method flow chart of a kind of automatic generation Global Asynchronous reset signal in the present invention;
Fig. 2 be in one embodiment of the invention register without asynchronous the schematic diagram of synchronous reset signal;
Fig. 3 is without reset schemes schematic diagram during reset signal in a preferred embodiment of the invention;
Fig. 4 is containing high level effective asynchronous reset signal reset schemes schematic diagram in the present invention;
Fig. 5 is the asynchronous reset signal reset schemes schematic diagram containing Low level effective in the present invention;
Fig. 6 is containing high level effective synchronous reset signal reset schemes schematic diagram in the present invention;
Fig. 7 is the synchronous reset signal reset schemes schematic diagram containing Low level effective in the present invention.
Embodiment
Fig. 1 is the process mapping method flow chart of a kind of automatic generation Global Asynchronous reset signal in the present invention.The method comprises the following steps:
In step 100, go out register according to different RTL literary style correspondence mappings in user's design.RTL(Register-transfer Level), i.e. Method at Register Transfer Level, there are direct mapping relations between statement in RTL model literary style and the structural model of actual register, the behavior model analyzing this RTL can determine type and the quantity of required register.
In step 110, logical operation is carried out to the register mapped out, by register without and/or asynchronous and/or synchronous reset signal be mapped to Global Asynchronous reset signal, carry out Global reset by this Global Asynchronous reset signal.According to the register that step 100 maps out, as shown in Figure 2, its type can be divided into five kinds: do not comprise the register of reset signal, the register containing the effective asynchronous reset signal of high level, the register of the asynchronous reset signal containing Low level effective, the register containing the effective synchronous reset signal of high level and the register of synchronous reset signal containing Low level effective.
Below in conjunction with Fig. 3-Fig. 7, the specific implementation process automatically generating Global Asynchronous reset signal is described in detail.Fig. 3 is the register reset schemes schematic diagram without reset signal, and its RTL literary style is as follows:
According to RTL literary style, map out type and the quantity of this register, wherein this register does not comprise reset signal, directly global reset signal GC can be coupled to the asynchronous reset end ACLR of register, as the asynchronous reset signal of this register.Such as: when the reset terminal of this register is Low level effective, directly global reset signal GC is connected to the reset signal end ACLR of register, when the reset terminal of register be high level effective time, by global reset signal by after negate (can be connect not gate), be connected to the reset signal end ACLR of register.When Global Asynchronous reset signal GC is placed in low level, reset signal is effective, and this register is reset.
It should be noted that, this global reset signal may come from the reset signal source in external software or indoor design.
Fig. 4 is the register comprising the effective asynchronous reset signal of high level, and its RTL literary style is as follows:
In this register, logical circuit comprises or door and not gate, Global Asynchronous reset signal is input to non-being connected to behind the door or the first input end of door, high level effective asynchronous reset signal AC(and former asynchronous reset signal AC) be connected to or the second input of door, should or the output of door be connected to the asynchronous reset end ACLR of register, when Global Asynchronous reset signal GC is in low level, register is reset, the effective asynchronous reset signal AC of high level contained by this register lost efficacy, and register resets under the control of Global Asynchronous reset signal GC.Fig. 5 is the register of the asynchronous reset signal comprising Low level effective, and its RTL literary style is as follows:
In this register, logical operation is carried out to this register, logical operation is realized by logical circuit, this logical circuit comprises and door, wherein, Global Asynchronous reset signal GC is connected to the first input end with door, the asynchronous reset signal AC(of Low level effective and former asynchronous reset signal) as the second input with door, be somebody's turn to do the asynchronous reset end being coupled to register with the output of door, when Global Asynchronous reset signal GC is in low level, reset signal is effective, now, register is reset, the asynchronous reset signal AC of the Low level effective contained by this register lost efficacy, register resets under the control of Global Asynchronous reset signal GC.
It should be noted that, in Fig. 4, Fig. 5, when this register reset terminal is Low level effective, the output signal (i.e. Global Asynchronous reset signal) of logical circuit is connected to the reset signal end ACLR of register, when register reset terminal be high level effective time, after the output negate (can be connect not gate) of logical circuit, be connected to the reset signal end ACLR of register.Fig. 6 is the register comprising the effective synchronous reset signal of high level, and its RTL literary style is as follows:
In this register, logical circuit comprise not gate and with door, this high level effective synchronous reset signal SC(and former synchronous reset signal SC) be input to the non-first input end with door that is connected to behind the door, the original input signal D of register is connected to the second input with door, be somebody's turn to do the data input pin being connected to this register with the output of door, by global reset signal GC, namely Global Asynchronous reset signal is coupled to the asynchronous reset end ACLR of register.When Global Asynchronous reset signal GC is in low level, reset signal is effective, and this register is reset.
Fig. 7 is the register of the synchronous reset signal comprising Low level effective, and its RTL literary style is as follows:
In this register, logical circuit comprises and door, the synchronous reset signal (i.e. former synchronous reset signal SC) of Low level effective is connected to the first input end with door, register original input signal D is connected to the second input with door, be somebody's turn to do the data input pin being connected to register with the output signal of door, global reset signal GC is also now Global Asynchronous reset signal, is connected to the asynchronous reset end ACLR of register.When Global Asynchronous reset signal GC is in low level, Global Asynchronous reset signal is effective, and this register is reset.
It should be noted that, in Fig. 6, Fig. 7, when this register reset terminal is Low level effective, Global Asynchronous reset signal is connected to the reset signal end ACLR of register, when register reset terminal be high level effective time, after Global Asynchronous reset signal negate (can be connect not gate), be connected to the reset signal end ACLR of register.Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. automatically generate a process mapping method for Global Asynchronous reset signal, comprising:
Register is gone out according to different RTL literary style correspondence mappings in user's design;
Logical operation is carried out to the register mapped out, by in register without and/or asynchronous and/or synchronous reset signal be mapped to Global Asynchronous reset signal, Global reset is carried out, wherein said Global Asynchronous reset signal Low level effective by this Global Asynchronous reset signal.
2. the process mapping method of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 1, it is characterized in that, the step being mapped to Global Asynchronous reset signal without reset signal in register is comprised, when described register is the register not comprising reset signal, directly Global Asynchronous reset signal is coupled to the asynchronous reset end of this register, when Global Asynchronous reset signal is effective, register is reset.
3. the process mapping method of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 1, it is characterized in that, the step that asynchronous reset signal in register is mapped to Global Asynchronous reset signal is comprised, when described register asynchronous reset signal effective containing high level, Global Asynchronous reset signal is input to non-being connected to behind the door or the first input end of door, effective for described high level asynchronous reset signal is connected to or the second input of door, should or the output of door be coupled to the asynchronous reset end of register.
4. the process mapping method of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 1, it is characterized in that, the step that asynchronous reset signal in register is mapped to Global Asynchronous reset signal is comprised, when described register contains the asynchronous reset signal of Low level effective, Global Asynchronous reset signal is connected to the first input end with door, using the asynchronous reset signal of described Low level effective as the second input with door, be somebody's turn to do the asynchronous reset end being coupled to register with the output of door.
5. the process mapping method of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 1, it is characterized in that, the step that synchronous reset signal in register is mapped to Global Asynchronous reset signal is comprised, when described register synchronous reset signal effective containing high level, the effective synchronous reset signal of this high level is input to the non-first input end with door that is connected to behind the door, the original input signal of described register is connected to the second input with door, be somebody's turn to do the data input pin being connected to this register with the output of door, global reset signal is coupled to the asynchronous reset end of described register.
6. the process mapping method of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 1, it is characterized in that, the step that synchronous reset signal in register is mapped to Global Asynchronous reset signal is comprised, when described register contains the synchronous reset signal of Low level effective, the synchronous reset signal of this Low level effective is connected to the first input end with door, register original input signal is connected to the second input with door, be somebody's turn to do the data input pin being connected to register with the output signal of door, global reset signal is coupled to the asynchronous reset end of described register.
7. automatically generate an integrated circuit for Global Asynchronous reset signal, comprising: nothing and/or register that is asynchronous and/or synchronous reset signal, as the logical circuit of logical operation, be coupled to the Global Asynchronous reset signal of register control end; Wherein, by register without and/or asynchronous and/or synchronous reset signal be mapped to Global Asynchronous reset signal by logical circuit, described Global Asynchronous reset signal carries out Global reset.
8. the integrated circuit of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 7, it is characterized in that, in described integrated circuit, register is the register not comprising reset signal, Global Asynchronous reset signal is coupled to the asynchronous reset end of this register, when Global Asynchronous reset signal is effective, register is reset.
9. the integrated circuit of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 7, is characterized in that, in described integrated circuit, register is the register containing the effective asynchronous reset signal of high level, and described logical circuit comprises not gate or door; Global Asynchronous reset signal is input to non-being connected to behind the door or the first input end of door, is connected to by effective for described high level asynchronous reset signal or the second input of door, should or the output of door be coupled to the asynchronous reset end of described register.
10. the integrated circuit of a kind of automatic generation Global Asynchronous reset signal as claimed in claim 7, it is characterized in that, in described integrated circuit, register is the register of the asynchronous reset signal of Low level effective, and described logical circuit comprises and door; Wherein, Global Asynchronous reset signal is connected to the first input end with door, and the asynchronous reset signal of described Low level effective, as the second input with door, is somebody's turn to do the asynchronous reset end being coupled to register with the output of door.
The integrated circuit of 11. a kind of automatic generation Global Asynchronous reset signals as claimed in claim 7, is characterized in that, in described integrated circuit, register is the register containing the effective synchronous reset signal of high level, and described logical circuit comprises not gate and door; Wherein, the effective synchronous reset signal of this high level is input to the non-first input end with door that is connected to behind the door, the original input signal of described register is connected to the second input with door, be somebody's turn to do the data input pin being connected to this register with the output of door, global reset signal is coupled to the asynchronous reset end of described register.
The integrated circuit of 12. a kind of automatic generation Global Asynchronous reset signals as claimed in claim 7, is characterized in that, in described integrated circuit, register is the register of the synchronous reset signal containing Low level effective, and described logical circuit comprises and door; Wherein, the synchronous reset signal of this Low level effective is connected to the first input end with door, register original input signal is connected to the second input with door, and be somebody's turn to do the data input pin being connected to register with the output signal of door, global reset signal is coupled to the asynchronous reset end of described register.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108226752A (en) * | 2017-12-25 | 2018-06-29 | 北京物芯科技有限责任公司 | A kind of fault repairing method of chip, device and equipment |
| CN112187233A (en) * | 2020-10-14 | 2021-01-05 | Oppo广东移动通信有限公司 | Reset device, method, clock system and electronic equipment |
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| CN101082939A (en) * | 2006-05-31 | 2007-12-05 | 中国科学院微电子研究所 | Reset circuit design method in system design on piece |
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| CN101082939A (en) * | 2006-05-31 | 2007-12-05 | 中国科学院微电子研究所 | Reset circuit design method in system design on piece |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108226752A (en) * | 2017-12-25 | 2018-06-29 | 北京物芯科技有限责任公司 | A kind of fault repairing method of chip, device and equipment |
| CN108226752B (en) * | 2017-12-25 | 2020-07-03 | 北京物芯科技有限责任公司 | Chip fault repairing method, device and equipment |
| CN112187233A (en) * | 2020-10-14 | 2021-01-05 | Oppo广东移动通信有限公司 | Reset device, method, clock system and electronic equipment |
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