CN101082939A - Reset circuit design method in system design on piece - Google Patents
Reset circuit design method in system design on piece Download PDFInfo
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Abstract
The invention discloses a reset circuit designing method in the piece system for different SOC circuit patterns, which is characterized by the following: adopting reset circuit structure pattern of synchronous reset end and asynchronous reset end for single reset IP pattern;; using reset circuit of synchronous reset end and Schmitt shaping circuit for synchronous SOC in the single-clock zone; adopting asynchronous reset end of trigger, synchronizing asynchronous circuit and reset circuit of Schmitt shaping circuit and reset signal time-sequence to control the reset circuit for multi-clock zone SOC; fitting for designing kinds of SOC reset circuit.
Description
Technical field
The present invention relates to the SOC (system on a chip) technical field, the reset circuit design method in particularly a kind of practical system-on-chip designs that very strong versatility arranged.
Background technology
In SOC (SOC (system on a chip), VLSI (very large scale integrated circuit)) design process, the design of reset circuit is to be left in the basket easily, can bring difficulty to design again, and influences the problem of chip operation stability.Whether suitable logic synthesis, static timing analysis, the design for Measurability that can directly influence the SOC design of reset circuit Scheme Choice and optimization implementation method, physical Design, each stage such as functional simulation checking, module are integrated, and and then influence the interface debugging difficulty of SOC under system's service condition and the stability when moving.
At present, full synchronous reset circuit form or full asynchronous reset circuit form are normally simply used in the design of reset circuit, the metastable state situation that part developer is occurred, select of the influence of reset circuit form to the SOC design process from actual use, some concrete solutions have been proposed, but for SOC research staff and since the design of reset circuit be in the SOC design process the comprehensive design problem that must consider comprehensively, weigh the pros and cons.Different design objects need be selected different reset circuit forms for use with the SOC applied environment, this just causes the method for designing of research staff institute reference to lack system and specific aim, rational circuit form can not be applied in the specific circuit structure, even the self-contradictory situation of partial design method occurs.
Summary of the invention
The inventive method is the complete design cycle method of a cover that is applicable to SOC reset circuit design process, and the comprehensive solution of procedure can be provided for the design of the reset circuit in the SOC design process.
To the IP type of the single form that resets, adopt reset circuit version based on synchronous reset end and asynchronous reset end; To the synchronous SOC in single clock territory, adopt reset circuit based on synchronous reset end and schmidt shaping circuit; To multi-clock zone SOC, adopt reset circuit, reset signal sequential control reset circuit based on trigger asynchronous reset end, synchronization asynchronous circuit, schmidt shaping circuit.This method for designing can effectively solve the various reset circuit design problems in the SOC design process, for the design of the reset circuit of SOC provides layout strategy.And can improve system's operational reliability of SOC.Method for designing can be widely used in the reset circuit design of various SOC.
The object of the present invention is to provide a system and a practical reset circuit design method that can be applicable to SOC.Summary of the invention mainly comprises the sorting technique that has proposed the SOC that is applicable to the different reset circuits of employing.According to the classification to SOC, it is complete at the designed reset circuit version of different SOC and the design procedure and the method for concrete reset circuit to the present invention proposes a cover.The concrete grammar and the step of this invention are as follows:
1) at first SOC is pressed interface and circuit structure feature, the specific (special) requirements of SOC design in logic synthesis, gate leve emulation, physical Design process, the reset signal loading procedure is divided SOC the SOC working reliability influence during practical application.This method mainly is divided into SOC the IP submodule of 3 classes: SOC; Be applicable to the SOC of full synchronous reset; Be applicable to the SOC of full asynchronous reset.According to this sorting technique, provide corresponding reset circuit design solution.
2) to the IP submodule of SOC, the design of reset circuit, mainly be integrated from being convenient to modular system, avoid gate leve emulation " unknown (X) attitude " to occur, be convenient to carry out three aspects such as design for Measurability and consider, proposed reset circuit design form, and provided the Hdl code based on synchronous reset end or asynchronous reset end.
3) SOC to full synchronous reset designs, mainly be from avoiding gate leve emulation " unknown (X) attitude " to occur, be convenient to carry out front end logic design and back-end physical design, avoid in the synchronous reset signal loading procedure caused metastable state (metastable), external interference signal that 4 aspects such as influence of reset terminal are considered, adopt the synchronous reset signal end is carried out synchronization process and increases circuit PAD that the close special efficacy of band application answers to increase the synchronous reset circuit form of the anti-interference inhibition ability of input port at input end.
4) SOC to full asynchronous reset designs, mainly be from avoiding the caused metastable state of asynchronous reset signal dispose procedure (metastable), the external interference signal is to the influence of reset terminal, asynchronous reset signal arrives the circuit sequence disorder that the reseting terminal of disparate modules causes at different time, be convenient to carry out 4 aspects such as front end logic design and back-end physical design and consider, provided the asynchronous reset signal end is carried out synchronization process and increases the anti-interference inhibition ability of input port and the asynchronous reset circuit design form and the method for the sequential of control reset signal arrival trigger reset end.
Reset circuit design method in a kind of system-on-chip designs, it is characterized in that, according to the SOC structure and the mode of operation that resets one cover reset circuit design category method is proposed, according to different sorting techniques, reset circuit circuit structure and method for designing that different SOC circuit forms are adopted have been proposed.
Reset circuit design method in the described system-on-chip designs, this method is the circuit structure feature according to SOC, the specific (special) requirements of SOC design in logic synthesis, gate leve emulation, physical Design process, real system when operation reset signal loads considers the very strong comprehensive sorting technique of a kind of operability that proposed to many-sided factors such as SOC working reliability influence comprehensively, method adopts the reset circuit version based on synchronous reset end and asynchronous reset end with the IP type that SOC is divided into the single form that resets; The synchronous SOC in single clock territory; To multi-clock zone SOC three major types type.
Reset circuit design method in the described system-on-chip designs, described sorting technique, IP type to the single form that resets, the form that resets that adopts is the circuit reset structure of full synchronous reset or full asynchronous reset, be characterized in that resetting of IP must be to reset by the Global reset end, adopt full synchronous reset or full asynchronous reset mode to be determined by the mode of operation of SOC.
Reset circuit design method in the described system-on-chip designs, described sorting technique, to the synchronous SOC of general purpose single clock zone, if during the same clock source that other IC that reset signal resetted of this SOC also is to use with this SOC, the designed reset circuit that goes out of the reset circuit design method of selecting is characterized in that: the circuit solution of selecting synchronous reset, disturbed the maloperation that produces to increase the PAD of band schmidt trigger function at the chip reset end for suppressing the reset signal port, avoid emulation " don't-know state (X attitude) " to occur to guarantee that reset signal is based on that the reseting terminal of trigger resets in the SOC design process for solving, at the big characteristics of Global reset fan-out number, adopt the method processing logic of the tree that bufcreates comprehensive, the physical Design sequential can not the convergent problem.
Reset circuit design method in the described system-on-chip designs, described sorting technique, to general multi-clock zone SOC, single clock territory SOC is (during system applies, this SOC does not use same clock source in other SOC) circuit, the designed reset circuit of selecting of method is characterized in that: the circuit solution of selecting asynchronous reset, disturbed the maloperation that produces for suppressing the reset signal port, select the circuit solution of synchronous reset, for solving the design for Measurability problem in the SOC design process, be the influence avoid the metastable state phenomenon that reset signal is discharged, and it starts the synchronized circuit design method of asynchronous reset that sequential has the band sequential control function that the different actual conditions that require provide according to SOC clock zone circuit logic module.
Description of drawings
Fig. 1 is method step figure of the present invention.
Fig. 2 is based on the circuit diagram of the trigger of the synchronous reset end of trigger and asynchronous reset.
Fig. 3 is based on the flip-flop circuit figure that resets of the data input pin of trigger.
Fig. 4 is the circuit description synoptic diagram of ' X ' transport phenomenon in the emulation.
Fig. 5 is the reset circuit figure that is applicable to full synchronous reset.
Fig. 6 is the reset circuit figure that is applicable to the incoherent full asynchronous reset of each clock zone circuit working sequential.
Fig. 7 reduces the standard circuit for synchronizing figure that the metastable state phenomenon takes place.
Fig. 8 is applicable to that each clock zone circuit working sequential has the reset circuit figure of the full asynchronous reset of strict demand.
Embodiment
The method of the invention of Fig. 1, its step is as follows:
The first step of embodiment is that the applied SOC design object of reset circuit is analyzed, and analyzing content mainly is that 3 aspects such as SOC circuit structure, SOC specific design factor, SOC reset circuit mode of operation are considered.Wherein clock zone situation, the reset circuit that need analyze SOC to the analysis content of SOC circuit structure analyzed in the distribution situation of SOC; SOC specific design factor need be analyzed the type of spendable library unit, and " X " attitude phenomenon is to the consideration of simulating, verifying in the simulating, verifying, and reset signal is analyzed three aspects that influence of physical Design; SOC reset circuit mode of operation need be to be operated in synchronously or asynchronous system the reset circuit of SOC, and the interface annoyance level of the reset signal of SOC is analyzed.
Second step of embodiment is that basis is classified to the analysis content of SOC, and the type of the reset circuit that is applicable to SOC that the present invention proposes mainly comprises the IP submodule of following 3 classes: SOC, is applicable to the SOC of full synchronous reset, the SOC of full asynchronous reset.Concrete sorting technique and step are as follows:
1) the IP submodule of SOC, be meant that can offer SOC does the integrated design submodule of System on Chip/SoC, consider from the SOC circuit structure, it is characterized in that clock zone is a single clock territory mode (if multi-clock zone, handle by the 3rd kind of mode), consider from the SOC mode of operation aspect that resets, it is characterized in that to adopt synchronous reset or asynchronous reset mode in the IP design of SOC integral reset working method decision SOC.
2) be applicable to the SOC of full synchronous reset, be meant according to the system applies specification requirements, the reseting terminal of chip works under the synchronous reset operator scheme fully, and the SOC that satisfies this classification mainly contains following 2 features: considering from the SOC circuit structure, is the single clock territory during SOC operate as normal; From the consideration to the SOC design process, if the reset terminal not by trigger resets, in carrying out simulation process, the emulation of " X " attitude might appear; Consider from the SOC mode of operation aspect that resets, when system-level application is used, the same clock source of other IC that reset signal resetted of this SOC and this SOC use.Design to this type of reset circuit needs reset circuit to solve: reseting terminal is subjected to the influence of factors such as external interference (synchro source switching noise, train of signal around); Reset signal does not satisfy the demand of setup/hold and the metastable state duty that causes; Reset circuit designs unreasonable " X attitude " problem that causes occurring in the design of Simulation.
3) SOC of full asynchronous reset is meant that the reset terminal of SOC works under the mode of operation of asynchronous reset.This type of SOC mainly contains following 2 characteristics: 1) from the SOC structure, SOC itself is the circuit of a multi-clock zone structure; SOC is the single clock circuit structure, but other IC that reset signal resetted of this SOC and this SOC use is not same clock source.2) from the mode of operation of SOC, the inside multi-clock zone module of SOC works in different resetting constantly, and SOC works in different resetting constantly when system works.The criteria for classification that inventive method proposed also shows, for most SOC designs, should use the working method of full asynchronous reset as far as possible.
The 3rd step of embodiment is that the sorting technique that is proposed according to summary of the invention part in the literary composition the 2nd step is described, if corresponding to the IP submodule of SOC, the reset circuit design method that should adopt summary of the invention part the 3rd joint to be adopted.Reset circuit adopts the reset circuit form (as Fig. 2) based on synchronous reset end or asynchronous reset end, consider the digital circuit part in present SOC design, normally on providing the basis of basic library unit, storehouse provider finishes the design of digital circuit, use based on the synchronous reset end of trigger or the reset mode of asynchronous reset end and can provide high-quality assurance as SOC design for Measurability and simulating, verifying, only the area to SOC has specific (special) requirements, on each trigger of SOC, all should have reseting terminal, if area is had specific (special) requirements, also should guarantee to realize resetting control at the synchronous reset end or the asynchronous reset end of the first order trigger of module.Fig. 3 is based on the trigger that the data input pin realization resets, if the schematic diagram of the phenomenon that don't-know state (' X ') transmits appears in Fig. 4 explanation when the reset mode that resets of the data input pin by SYN register might not cause gate leve emulation, this is because on the one hand, the reset signal of register and the data input signal of register can only work by the data input pin of register, make the reset signal of register could under the effect of clock signal, play reset response by certain combinational logic to register.On the other hand, the EDA synthesis tool is different with the logical value that emulation tool is considered, what synthesis tool used is two-valued function, and (i.e. only consideration ' 0 ' and ' 1 ' state, what emulation tool was then considered is multi valued logic.With Fig. 3 is example, in the starting stage, DC thinks that the output Q of register cell DFF1 is ' 0 ' or ' 1 ', therefore, and when RST=' 0 ', DFF2 must reset, yet emulation tool VCS thinks but that in the starting stage output Q of DFF1 is ' X ', therefore, when Reset=' 0 ', the output of DFF2 also is ' X '.Thereby cause at functional simulation during the stage, chip can't enter init state.Consider when using IP to carry out system combination, whole SOC might be the synchronous reset operator scheme, it also might be asynchronous reset operation element pattern, therefore, this IP need be designed to work in the synchronous reset operator scheme, also can work in the asynchronous reset operator scheme, its Verilog code is as follows respectively:
Always@ (posedge clk or negedge rst) // based on the reset circuit of asynchronous reset end
if(！rst)q＜＝1′b0；
else?q＜＝d；
endmodule
Always@ (posedge clk) // based on the reset circuit of synchronous reset end
if(！rst)q＜＝1′b0；
else?q＜＝d；
endmodule
The 4th step of embodiment is that the sorting technique that is proposed according to summary of the invention part in the literary composition the 2nd joint is described, if corresponding to the SOC that is applicable to full synchronous reset, and the reset circuit design method that should adopt summary of the invention part the 4th part to be adopted.Fig. 5 is the reset circuit form at this type of SOC design, to this type of SOC design, for fear of external interference, reseting terminal by a schmidt trigger circuit, delay cell and or door (low level resets, if high level resets, then will or door change into and door) enter reseting network, thereby utilize the hysteresis effect of schmidt trigger circuit can realize that shaping pulse effectively suppresses to disturb, utilize delay cell with or the acting in conjunction of door can the filtering unusual waveforms to the influence of reset circuit.The difficulty that " X attitude " (don't-know state) brings to simulating, verifying appears for fear of trigger resets the simulation process that causes by synchronous input end in, the principle that resets and all should reset of whole SOC in accordance with the synchronous reset terminal of use library unit, in the process of carrying out logic synthesis and physical Design, especially when handling the design of 1,000,000 gate leve ASIC, because the fan-out number that its global reset signal drove is just quite high, need carry out particular design, the better physical synthesis tool is as (PC) at present, the method of handling the high fan-out network of this class is provided, the deviser is when carrying out logical level comprehensive, set_ideal_net can be set to ideal signal with global reset signal with order, when the completion logic rank is comprehensive, by physical synthesis instrument create_buffer_tree, finish the physical synthesis of reset signal network.
The 5th step of embodiment is that the sorting technique that is proposed according to summary of the invention part in the literary composition the 2nd joint is described, if corresponding to the SOC that is applicable to full asynchronous reset, and the reset circuit design method that should adopt summary of the invention part the 2nd joint to be adopted.Consideration mainly contains: reseting terminal is subjected to the influence of factors such as external interference (synchro source switching noise, train of signal around); Reset signal fails to satisfy the requirement of recovery time of asynchronous reset end when resetting release, thus the metastable state duty that causes; The disorder of the logical circuit work schedule of the inconsistent different clock-domains that causes of the moment of the release signal arrival different clock-domains trigger of reset signal; Influence in SOC design processes such as SOC measurability, logic synthesis, physical Design.
To this type of SOC circuit, can further be subdivided into following two classes: there is arbitrated logic in each clock zone circuit, and reset signal discharges the whether orderly operate as normal that can not influence whole SOC constantly; The initialization of each clock zone circuit must have the branch of priority constantly.To the 1st kind of SOC, adopt the reset circuit form of Fig. 6, the reseting terminal of this circuit by a schmidt trigger circuit, delay cell and or door (low level resets, if high level resets, then will or the door change into the door) function mainly be for suppressing the influence of various undesired signals, after this processing of circuit, reset signal is re-used as the clear terminal of two other synchronizer trigger, the output of these two triggers enters reseting network after being connected to multi-way switch (MUX), is to avoid the metastable state phenomenon that occurred when reset signal discharges through the benefit of synchronizer trigger.The function that multi-way switch possessed that increases can realize the design for Measurability of VLSI is convenient in the direct bypass of the output terminal of reset signal slave flipflop.Fig. 7 is a kind of synchronization device of canonical form, can weaken the influence of metastable state phenomenon significantly.To second kind of SOC, circuit start has the strict sequential order requirement in each clock zone, at this situation, provided the reset circuit form of Fig. 8, compare with Fig. 6, its difference with the strict sequential order control that can realize that each clock zone circuit reset starts, SOC research staff can select corresponding reset circuit layout strategy and circuit form according to the circuit structure and the real work situation in the circuit clock territory of designed SOC.
Specific embodiment
Reset circuit design method at SOC is applied in 4,500,000 hypervelocity dsp chip Speed-I of Chinese Academy of Sciences Microelectronics Institute's development.This dsp chip design effort frequency 80Mhz, scale reaches 4,500,000, and flow on the 0.18um of SMIC production line is tested on the Agilent93000 tester of Beijing big Tai Site semiconductor detection technique company limited of China and is passed through.Utilize this reset circuit design method, we have formulated the reset circuit layout strategy of this SOC rapidly, circuit form and the method for designing of utilizing invention to be provided have well solved the technical matters that reset circuit brings several respects such as logic synthesis in the SOC design, functional simulation, physical Design.Simultaneously, the test of real system and reliability service have also fully proved practicality and the science of considering employed special circuit form behind metastable state and the external interference signal.(method of the present invention is still unexposed).
Claims (7)
1, reset circuit design method in a kind of system-on-chip designs, it is characterized in that, according to the SOC structure and the mode of operation that resets one cover reset circuit design category method is proposed, according to different sorting techniques, reset circuit circuit structure and method for designing that different SOC circuit forms are adopted have been proposed.
2, reset circuit design method in the system-on-chip designs according to claim 1, it is characterized in that: this method is the circuit structure feature according to SOC, the specific (special) requirements of SOC design in logic synthesis, gate leve emulation, physical Design process, real system when operation reset signal loads considers the very strong comprehensive sorting technique of a kind of operability that proposed to many-sided factors such as SOC working reliability influence comprehensively, method adopts the reset circuit version based on synchronous reset end and asynchronous reset end with the IP type that SOC is divided into the single form that resets; The synchronous SOC in single clock territory; To multi-clock zone SOC three major types type.
3, reset circuit design method in the system-on-chip designs according to claim 2, it is characterized in that: described sorting technique, IP type to the single form that resets, the form that resets that adopts is the circuit reset structure of full synchronous reset or full asynchronous reset, be characterized in that resetting of IP must be to reset by the Global reset end, adopt full synchronous reset or full asynchronous reset mode to be determined by the mode of operation of SOC.
4, reset circuit design method in the system-on-chip designs according to claim 2, it is characterized in that: described sorting technique, to the synchronous SOC of general purpose single clock zone, if during the same clock source that other IC that reset signal resetted of this SOC also is to use with this SOC, the designed reset circuit that goes out of the reset circuit design method of selecting is characterized in that: the circuit solution of selecting synchronous reset, disturbed the maloperation that produces to increase the PAD of band schmidt trigger function at the chip reset end for suppressing the reset signal port, avoid emulation " don't-know state (X attitude) " to occur to guarantee that reset signal is based on that the reseting terminal of trigger resets in the SOC design process for solving, at the big characteristics of Global reset fan-out number, adopt the method processing logic of the tree that bufcreates comprehensive, the physical Design sequential can not the convergent problem.
5, reset circuit design method in the system-on-chip designs according to claim 2, it is characterized in that: described sorting technique, to general multi-clock zone SOC, single clock territory SOC is (during system applies, this SOC does not use same clock source in other SOC) circuit, the designed reset circuit of selecting of method is characterized in that: the circuit solution of selecting asynchronous reset, disturbed the maloperation that produces for suppressing the reset signal port, select the circuit solution of synchronous reset, for solving the design for Measurability problem in the SOC design process, be the influence avoid the metastable state phenomenon that reset signal is discharged, and it starts the synchronized circuit design method of asynchronous reset that sequential has the band sequential control function that the different actual conditions that require provide according to SOC clock zone circuit logic module.
6, reset circuit design method in the system-on-chip designs according to claim 1, step is as follows: 1) at first SOC is pressed interface and circuit structure feature, the specific (special) requirements of SOC design in logic synthesis, gate leve emulation, physical Design process, the reset signal loading procedure is divided SOC the SOC working reliability influence during practical application, mainly SOC is divided into the IP submodule of 3 classes: SOC; Be applicable to the SOC of full synchronous reset; Be applicable to the SOC of full asynchronous reset;
2) to the IP submodule of SOC, the design of reset circuit, avoid gate leve emulation " unknown (X) attitude " to occur, be convenient to carry out the consideration of design for Measurability three aspects, propose reset circuit design form, and provide the Hdl code based on synchronous reset end or asynchronous reset end;
3) SOC to full synchronous reset designs, mainly be from avoiding gate leve emulation " unknown (X) attitude " to occur, avoid caused metastable state in the synchronous reset signal loading procedure, external interference signal that 4 aspects that influence of reset terminal are considered, adopt the synchronous reset signal end is carried out synchronization process and increases circuit PAD that the close special efficacy of band application answers to increase the synchronous reset circuit form of the anti-interference inhibition ability of input port at input end;
4) SOC to full asynchronous reset designs, mainly be from avoiding the caused metastable state of asynchronous reset signal dispose procedure, external interference signal that the influence of reset terminal, asynchronous reset signal are arrived circuit sequence disorder that the reseting terminal of disparate modules causes at different time, are convenient to carry out consider aspect 4 of front end logic design and the back-end physical designs, provide the asynchronous reset signal end is carried out synchronization process and increases the anti-interference inhibition ability of input port and the control reset signal arrives the asynchronous reset circuit design form and the method for the sequential of trigger reset end.
7, the reset circuit design method in the system-on-chip designs according to claim 1, its step is as follows:
The first step is that the applied SOC design object of reset circuit is analyzed, SOC circuit structure, SOC specific design factor, SOC reset circuit mode of operation 3 aspects are considered wherein clock zone situation, the reset circuit that need analyze SOC to the analysis content of SOC circuit structure analyzed in the distribution situation of SOC; SOC specific design factor need be analyzed the type of spendable library unit, and " X " attitude phenomenon is to the consideration of simulating, verifying in the simulating, verifying, and reset signal is analyzed three aspects that influence of physical Design;
Second step was according to the analysis content of SOC is classified, and the type that is applicable to the reset circuit of SOC mainly comprises the IP submodule of following 3 classes: SOC, was applicable to the SOC of full synchronous reset, the SOC of full asynchronous reset, and concrete sorting technique and step are as follows:
1) the IP submodule of SOC is meant that can offer SOC does the integrated design submodule of System on Chip/SoC, considers from the SOC circuit structure; 2) be applicable to the SOC of full synchronous reset, be meant according to the system applies specification requirements, the reseting terminal of chip works under the synchronous reset operator scheme fully, and the SOC that satisfies this classification mainly contains following 2 features: considering from the SOC circuit structure, is the single clock territory during SOC operate as normal; From the consideration to the SOC design process, if the reset terminal not by trigger resets, in carrying out simulation process, the emulation of " X " attitude might appear; Consider from the SOC mode of operation aspect that resets, when system-level application is used, the same clock source of other IC that reset signal resetted of this SOC and this SOC use; 3) SOC of full asynchronous reset is meant that the reset terminal of SOC works under the mode of operation of asynchronous reset, and this type of SOC mainly contains following 2 characteristics: 1) from the SOC structure, SOC itself is the circuit of a multi-clock zone structure; SOC is the single clock circuit structure, but what other IC that reset signal resetted of this SOC and this SOC used is not same clock source, 2) from the mode of operation of SOC, the inside multi-clock zone module of SOC works in different resetting constantly, SOC works in different resetting constantly when system works, the criteria for classification that is proposed also shows, for most SOC designs, should use the working method of full asynchronous reset as far as possible;
The 3rd step was a basis, the sorting technique that is proposed, if IP submodule corresponding to SOC, should adopt the reset circuit design method that is adopted, reset circuit adopts the reset circuit form based on synchronous reset end or asynchronous reset end, consider the digital circuit part in present SOC design, normally on providing the basis of basic library unit, storehouse provider finishes the design of digital circuit, use based on the synchronous reset end of trigger or the reset mode of asynchronous reset end and can provide high-quality assurance as SOC design for Measurability and simulating, verifying, only the area to SOC has specific (special) requirements, on each trigger of SOC, all should have reseting terminal, if area is had specific (special) requirements, also should guarantee to realize resetting control at the synchronous reset end or the asynchronous reset end of the first order trigger of module, the reset signal of register and the data input signal of register can only work by the data input pin of register, make that the reset signal of register must could be under the effect of clock signal by certain combinational logic, register is played reset response, on the other hand, the EDA synthesis tool is different with the logical value that emulation tool is considered, what synthesis tool used is two-valued function, i.e. only consideration ' 0 ' and ' 1 ' state, what emulation tool was then considered is multi valued logic;
The 4th step was according to the sorting technique that is proposed, if corresponding to the SOC that is applicable to full synchronous reset, should adopt the reset circuit design method that is adopted, reset circuit form at this type of SOC design, to this type of SOC design, for fear of external interference, reseting terminal is by a schmidt trigger circuit, delay cell and or door enter reseting network, the hysteresis effect of utilizing schmidt trigger circuit can realize that thereby shaping pulse effectively suppresses to disturb, utilize delay cell with or the acting in conjunction of door can the filtering unusual waveforms to the influence of reset circuit, " X attitude " appears for fear of trigger resets the simulation process that causes by synchronous input end in;
The 5th step was according to the sorting technique that is proposed, if corresponding to the SOC that is applicable to full asynchronous reset, should adopt the reset circuit design method that is adopted, and Consideration mainly contains: reseting terminal is subjected to the influence of external interference factor; Reset signal fails to satisfy the requirement of asynchronous reset end time when resetting release, thus the metastable state duty that causes; The disorder of the logical circuit work schedule of the inconsistent different clock-domains that causes of the moment of the release signal arrival different clock-domains trigger of reset signal; Influence in SOC measurability, logic synthesis, physical Design SOC design process.
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| CN104426511A (en) * | 2013-08-22 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Technical mapping method and integrated circuit for automatically generating global asynchronous reset signals |
| CN106164853A (en) * | 2014-04-07 | 2016-11-23 | 高通股份有限公司 | The system and method that the instruction using the chip residing on external memory devices to limit is revised for initiating sequence |
| CN108226743A (en) * | 2016-12-22 | 2018-06-29 | 深圳市中兴微电子技术有限公司 | The generation method and device of a kind of test vector |
| CN111857306A (en) * | 2020-07-30 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
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| CN116094518A (en) * | 2022-12-30 | 2023-05-09 | 成都电科星拓科技有限公司 | Reset method of high-precision all-digital phase-locked loop |
| CN117422032A (en) * | 2023-12-19 | 2024-01-19 | 苏州旗芯微半导体有限公司 | Local reset circuit of complex system comprising multiple subsystems |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104426511A (en) * | 2013-08-22 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Technical mapping method and integrated circuit for automatically generating global asynchronous reset signals |
| CN106164853A (en) * | 2014-04-07 | 2016-11-23 | 高通股份有限公司 | The system and method that the instruction using the chip residing on external memory devices to limit is revised for initiating sequence |
| CN108226743A (en) * | 2016-12-22 | 2018-06-29 | 深圳市中兴微电子技术有限公司 | The generation method and device of a kind of test vector |
| CN111857306A (en) * | 2020-07-30 | 2020-10-30 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
| CN111857306B (en) * | 2020-07-30 | 2021-12-03 | 山东云海国创云计算装备产业创新中心有限公司 | SoC system universal reset method and system, universal reset unit and SoC reset circuit |
| CN112187233A (en) * | 2020-10-14 | 2021-01-05 | Oppo广东移动通信有限公司 | Reset device, method, clock system and electronic equipment |
| CN112130651A (en) * | 2020-10-28 | 2020-12-25 | 北京百瑞互联技术有限公司 | Reset method and device of SOC (System on chip) system and storage medium thereof |
| CN116094518A (en) * | 2022-12-30 | 2023-05-09 | 成都电科星拓科技有限公司 | Reset method of high-precision all-digital phase-locked loop |
| CN116094518B (en) * | 2022-12-30 | 2024-04-05 | 成都电科星拓科技有限公司 | Reset method of high-precision all-digital phase-locked loop |
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