CN106531222B

CN106531222B - FPGA driving voltage generating circuit based on FLASH and driving method

Info

Publication number: CN106531222B
Application number: CN201610988481.0A
Authority: CN
Inventors: 赵宏建; 赵以诚; 周刚
Original assignee: CETC 4 Research Institute
Current assignee: CETC 4 Research Institute
Priority date: 2016-11-10
Filing date: 2016-11-10
Publication date: 2020-01-24
Anticipated expiration: 2036-11-10
Also published as: CN106531222A

Abstract

The invention relates to an FPGA driving voltage generating circuit based on FLASH, comprising: the device comprises a rheostat circuit, a voltage conversion circuit, a push-pull output stage circuit and a power-on control circuit, wherein the rheostat circuit, the voltage conversion circuit, the push-pull output stage circuit and the power-on control circuit are sequentially connected, and the power-on control circuit is connected with the voltage conversion circuit. The method is to select different voltages according to different operation time sequence states. The invention can achieve the design goals of rapidness, high efficiency and low power consumption, and ensures the low power consumption and flexible voltage control of the system. The voltage selection requirements of programming, reading, erasing and the like in various FPGA systems based on FLASH are met to the maximum extent, and the FPGA system has the advantages of simple structure, convenience in use and the like.

Description

FPGA driving voltage generating circuit based on FLASH and driving method

Technical Field

The invention relates to an FPGA and an analog circuit, in particular to a voltage driving circuit in the FPGA, and specifically relates to a FLASH-based FPGA programming, reading and erasing driving voltage generating circuit and a driving method.

Background

FPGAs (field programmable gate arrays) are important tools widely used in modern communication technology, electronic technology, computer technology, and automation technology. FLASH memory is a new type of non-volatile semiconductor memory, which combines the advantages of other memories and has the features of high density, low cost and high reliability. And the FPGA chip based on the FLASH organically combines the two chips, thereby realizing the high-density storage and transmission functions. The chip has the characteristics of low cost and high storage density, and is widely applied to various fields including PC and peripheral equipment, telecommunication switches, network interconnection equipment, instruments and meters, automotive electronics and emerging products such as voice, image and data storage.

The FPGA chip based on the FLASH memory unit is mainly based on the FLASH memory unit array, so that the performance of the FPGA chip is mainly dependent on the performance of the FLASH memory unit and the FLASH memory unit array. The performance of the FLASH memory array in the prior art is mainly reflected in the programming, erasing and reading operation functions and the speed of the FLASH memory array, and each operation needs to rapidly and accurately provide a voltage state for the word line of the FLASH memory cell, so that the whole system has higher reliability.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a FLASH unit-based FPGA programming, reading and erasing driving voltage generation circuit, which can quickly and accurately provide three voltages required by a word line.

The technical scheme adopted by the invention for realizing the purpose is as follows: FPGA driving voltage generation circuit based on FLASH includes: the device comprises a rheostat circuit, a voltage conversion circuit, a push-pull output stage circuit and an electrifying control circuit, wherein the rheostat circuit, the voltage conversion circuit, the push-pull output stage circuit and the electrifying control circuit are connected in sequence;

the rheostat circuit is used for adjusting the resistance value of the rheostat circuit by weighting the inputted different decoded resistances and outputting voltage to the voltage conversion circuit;

the power-on control circuit is used for controlling the power-on starting of the FPGA driving voltage generation circuit;

the voltage conversion circuit is used for converting a voltage value into a linear region of the push-pull output stage circuit through the voltage conversion circuit according to the voltage output by the rheostat circuit, and outputting a voltage V3 to the push-pull output stage circuit;

and the push-pull output stage circuit amplifies the output result of the voltage conversion circuit to a required voltage value and is used for providing a programming voltage to a storage unit of the FPGA.

The varistor circuit comprises a plurality of resistor units; the resistor unit comprises an even number of NMOS tube pairs;

the NMOS tube pair comprises two NMOS tubes connected in series, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube; the grid electrode of the first NMOS tube is used as the switch control end of the NMOS tube pair, the drain electrode is used as the output end of the NMOS tube pair, the grid electrode of the second NMOS tube is used as the input end of the NMOS tube pair, and the source electrode is grounded; the input ends of all NMOS tube pairs in the resistor unit are connected to be used as the input end OUT _1 of the resistor unit, and the output ends of all NMOS tube pairs in the resistor unit are connected to be used as the output end OUT _2 of the resistor unit; each control end is used for inputting decoding;

the input end OUT _1 and the output end OUT _2 of the resistor unit are connected with the input end of the voltage conversion circuit.

The power-on control circuit comprises an inverter, a PMOS tube P1 and an NMOS tube N1; the input end of the phase inverter is used for receiving an enable signal, and the output end of the phase inverter is connected with the G pole of a PMOS tube P1 and the G pole of an NMOS tube N1; the S pole of the PMOS tube P1 is connected with a power supply, and the S pole of the NMOS tube N1 is grounded; the D pole of the PMOS transistor P1 and the D pole of the NMOS transistor N1 are connected, and are used as the output end VDDP _1 of the power-on control circuit and are connected to the voltage conversion circuit.

The voltage conversion circuit comprises a plurality of operational amplifiers; the positive input end of the operational amplifier A1 and the positive input end of the operational amplifier A2 are respectively connected with the output end VDDP _1 through resistors, and the reverse input end of the operational amplifier A1 and the positive input end of the operational amplifier A3 are connected with the positive input end of the operational amplifier A2 and the positive input end of the operational amplifier A3; the positive input end of the operational amplifier A1 is connected with the output end OUT of the rheostat RX2, the A end of the rheostat RX2 is connected with the output end VDDP _1, and the B end is connected with the output end of the operational amplifier A1; the power supply end of the operational amplifier A1 is connected with the output end VDDP _1, and the output end of the operational amplifier A1 is connected with the input end OUT _1 of the rheostat circuit;

the positive input end of the operational amplifier A2 is grounded, and the negative input end is respectively connected with the output end of the operational amplifier A2 and the output end VDDP _1 through resistors;

the inverting input end of the operational amplifier A3 is connected with the output end of the operational amplifier A3 through a resistor and is also connected with the output end OUT _2 of the rheostat circuit;

the output end of the operational amplifier A2 and the output end of the operational amplifier A3 are respectively connected with the reverse input end and the forward input end of the operational amplifier A4 through resistors, the forward input end is grounded, the reverse input end is connected with the output end through a resistor, and the power supply end is connected with the output end VDDP _ 1; the output end of the operational amplifier A4 is connected with the input end of the push-pull output stage circuit.

The rheostat RX2 comprises an even number of NMOS tube pairs, the source electrode of a first NMOS tube is connected with the drain electrode of a second NMOS tube, and the source electrode of the second NMOS tube is grounded; the grid electrode of the first NMOS transistor of all the NMOS transistor pairs is connected to serve as the A end of the rheostat RX2, the drain electrode of the first NMOS transistor of all the NMOS transistor pairs serves as the output end OUT of the rheostat RX2, and the grid electrode of the second NMOS transistor of all the NMOS transistor pairs serves as the B end of the rheostat RX 2.

The push-pull output stage circuit comprises an operational amplifier A5 and an inverter which are connected in sequence; the inverting input end of the operational amplifier A5 is connected with the output end of the operational amplifier A4, the forward input end is grounded through a resistor and is also connected with the output end of an inverter through a resistor, and the output end of the inverter is used for being connected with the programming voltage input end of the memory cell.

A FPGA driving voltage generation method based on FLASH comprises the following steps:

the rheostat circuit outputs voltage to the voltage conversion circuit by carrying out different resistance weighted values on input codes;

the power-on control circuit performs power supply starting control on the whole circuit according to an external enabling signal to enable the power supply of the whole circuit to be effective;

the voltage conversion circuit converts the voltage into a linear amplification region range of the push-pull output stage circuit according to the voltage output value of the rheostat circuit, and outputs the voltage V3 to the push-pull output stage circuit;

the push-pull output stage circuit further amplifies the voltage V3 and provides the output voltage VPPH to the input of the memory cell programming voltage for memory programming.

The varistor circuit performing different resistance weighting values by decoding the input comprises the steps of:

the OUT _1 end of each resistor unit receives the OUT _1 end voltage of the voltage conversion circuit, and the control end receives 8-bit control codes;

the input end of OUT _1 controls the on-resistance of the MOS tube, and different voltage values correspond to different resistance values; the switch of the MOS switch is controlled by the control end, so that the parallel number of the resistor array is obtained, and further, the resistance value and the output voltage of the whole rheostat are obtained.

The power-on control circuit performs power supply starting control on the whole circuit according to an external enabling signal and comprises the following steps:

the inverter inverts an externally input enable signal, and then conducts the voltage VDDP through the PMOS tube to provide the voltage conversion circuit with VDDP _1 as a power supply.

The voltage conversion circuit converts the voltage into the range of a linear amplification region of a push-pull output stage circuit according to the voltage output value of the rheostat circuit and comprises the following steps:

the voltage VDDP _1 outputs OUT _1 through the operational amplifier A to control the conduction resistance value of the MOS tube of the rheostat circuit;

the operational amplifier A2 passes the VDDP _1 voltage value through the voltage proportional operational output voltage V1 to the operational amplifier A4, the operational amplifier A3 passes the varistor output voltage value through the voltage proportional operational output voltage V2 to the operational amplifier A4; the operational amplifier a4 outputs a voltage V3 to the push-pull output stage circuit by voltage scaling operation of V1 and V2.

The invention has the following beneficial effects and advantages:

1. the invention provides a novel programming, reading and erasing drive voltage generating circuit of a FPGA based on FLASH, which can utilize an MOS transistor resistor weighting array to control the voltage conversion, thereby controlling the programming, reading and erasing drive voltage through a processor at different moments and requirements, ensuring that a FLASH storage unit has higher reliability in programming, reading and erasing operations, enabling the FLASH storage to work quickly, efficiently and stably and improving the performance of the whole circuit system.

2. The invention provides required voltage when programming, reading, erasing and other operations are carried out on the word line and the bit line of the FLASH storage unit, different voltage selections can be carried out according to different operation time sequence states, the design targets of high speed, high efficiency and low power consumption can be achieved, and the low power consumption and flexible voltage control of a system are ensured. The voltage selection requirements of programming, reading, erasing and the like in various FPGA systems based on FLASH are met to the maximum extent, and the FPGA system has the advantages of simple structure, convenience in use and the like.

Drawings

FIG. 1 is a schematic block diagram of a FLASH cell based FPGA programming, readout, and erase drive voltage generation circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a specific circuit implementation in the circuit block diagram of FIG. 1;

fig. 3 is a circuit diagram of an implementation manner of the varistor module RX2 based on MOS transistor resistance in fig. 2;

fig. 4a is a first circuit diagram of an implementation manner of the varistor module RX1 based on MOS transistor resistance in fig. 2;

fig. 4b is a circuit diagram of a second implementation manner of the varistor module RX1 based on MOS transistor resistance in fig. 2.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The invention provides a design of a FLASH-based FPGA (field programmable gate array) programming, reading and erasing driving voltage generating circuit, which comprises a rheostat module based on an MOS (metal oxide semiconductor) tube resistor; the conversion circuit is used for converting the resistance value configured by the rheostat module into required voltage through an operational amplifier; a push-pull output stage circuit outputting the voltage of the voltage conversion circuit; a control circuit and a bias circuit for controlling the whole circuit to start power-up.

A programming, reading and erasing drive voltage generating circuit of FPGA based on FLASH comprises:

the rheostat module based on the MOS transistor resistor adjusts the resistance value of the whole rheostat module by adjusting the resistance weighting of different decoding;

a voltage conversion circuit converting a power supply voltage to a linear region of the push-pull output stage;

the push-pull output stage circuit amplifies the final output result to a required voltage value and improves the driving capability;

and the power-on control circuit controls the power-on start of the whole circuit and provides bias voltage of the amplifier.

The rheostat module of the MOS resistor is composed of an MOS tube resistor weighting network.

The voltage conversion circuit comprises a resistance proportion operation network circuit consisting of operational amplifiers.

The push-pull output stage circuit amplifies an output voltage of the voltage conversion circuit as an output voltage through a push-pull amplifier.

The power-on control circuit is a reference bias circuit consisting of an MOS tube and a resistor.

The FPGA programming, reading and erasing drive voltage generating circuit based on the FLASH unit provided by the invention comprises: a rheostat module based on MOS tube resistance; the conversion circuit is used for converting the resistance value configured by the rheostat module into required voltage through an operational amplifier; a push-pull output stage circuit outputting the voltage of the voltage conversion circuit; a control circuit and a bias circuit for controlling the whole circuit to start power-up.

The rheostat module based on the MOS tube resistor is characterized in that an MOS tube switch and the MOS tube resistor are connected in series, and the resistance value of the whole rheostat module is determined by logic control through different decoding gating different weighted resistance networks.

The obtained resistance value is used for converting the power voltage into the linear amplification area range of the push-pull output stage through proportional operation by the operational amplifier, and the voltage is further amplified to a required voltage value through the amplification effect of the push-pull output stage, so that the driving capability is improved.

In some embodiments, the varistor module based on the MOS transistor resistance is a weighted array of a resistor network formed by MOS resistors and MOS switches connected in series.

In some embodiments, the voltage conversion circuit includes a first stage voltage conversion circuit and a second stage voltage conversion circuit; the voltage conversion circuit input by the starting power supply voltage and the voltage conversion circuit input by the rheostat module are used as two first-stage voltage conversion circuits; the outputs of the two first-stage voltage conversion circuits are used as the input of the second-stage voltage conversion circuit, and are amplified in proportion by an operational amplifier to obtain a proper conversion voltage.

In some embodiments, the push-pull output stage is formed by a push-pull amplifier and an input amplifier to form a closed-loop negative feedback loop, so that the stability and the driving capability of voltage are ensured.

In some embodiments, the power-on control circuit is composed of a reference circuit composed of an inverter, a MOS tube and a resistor.

Fig. 1 is a schematic block diagram of a FLASH cell-based FPGA programming, reading, and erasing driving voltage generating circuit according to an embodiment of the present invention.

As shown in fig. 1, the driving circuit includes a varistor module 1 based on MOS resistance, a voltage conversion circuit 2, a push-pull output stage circuit 3, and a power-on control circuit 4.

The varistor module 1 based on MOS resistors adjusts the resistance value of the entire varistor module by setting resistance weights of different decoding, and the obtained resistance value is one of the proportional resistances.

Fig. 2 shows a circuit principle of the voltage conversion circuit in the circuit block diagram of fig. 1 in detail.

As shown in fig. 2, according to one embodiment, a power-up start circuit is composed of INV and P1, N1 tube, VDDP _1 is high when EN is high, and power supply voltage is provided for all other operational amplifiers a1, a2, A3, a4, a5 and push-pull output stage a 6. The OUT _1 bias voltage is obtained by the rheostat RX2 and the operational amplifier A1 and is used as the resistance value of the MOS resistor for controlling the rheostat RX 1.

The decoding control ends of the varistors A7, A6, A5, A4, A3, A2, A1 and A0 are controlled by different decoding to gate different resistance weights, so that the RX1 can obtain different resistance values. The voltage VDDP _1 is processed by an operational amplifier A2 to obtain V1, RX1 and R6 form a proportional resistor, the voltage VDDP _1 is processed by an operational amplifier A3 to obtain V2, and V1 and V2 are output results of the first-stage voltage converter. V1 and V2 are used as input ends of the second-stage voltage converter, and the voltage V3 which is converted and output by the operational amplifier A4 is used as input of the push-pull output stage. And finally, the power supply voltage of the push-pull output stage is VPP, and the final output voltage VPPH is obtained through the amplification of the output stage.

Fig. 3 shows a circuit block diagram specifically illustrating the circuit block diagram of fig. 2 based on the MOS transistor resistor RX 2.

As shown in fig. 3, the NMOS switch tube corresponding to the input end a, and the NMOS tube resistor corresponding to the input end B, where the end B is externally connected to OUT _1, and the resistance value is determined according to the value of OUT _ 1.

Fig. 4a to 4b are circuit block diagrams specifically showing the MOS transistor resistor RX1 based circuit block diagram shown in fig. 2.

As shown in fig. 4a to 4b, in all the serially connected NMOS transistor pairs, the gate of the lower NMOS transistor is connected to OUT _1 to be used as a MOS transistor resistor, and the upper NMOS transistor is used as a switch transistor, where a7 corresponds to 128 MOS transistor resistor arrays, a6 corresponds to 64 MOS transistor resistor arrays, a5 corresponds to 32 MOS transistor resistor arrays, a4 corresponds to 16 MOS transistor resistor arrays, A3 corresponds to 8 MOS transistor resistor arrays, a2 corresponds to 4 MOS transistor resistor arrays, a1 corresponds to 2 MOS transistor resistor arrays, and a0 corresponds to 2 MOS transistor resistor arrays, and different decoding control terminals are used to gate different resistor array weights, so that RX1 can obtain different resistance values.

According to the above embodiment, the supply voltage VDDP is converted to VDDP _1 through power-up, then converted to the input voltage of the push-pull output stage through the secondary voltage, and then converted to the required output voltage VPPH using the push-pull output stage.

The above description is only an embodiment of the present invention, and does not limit the scope of the present invention, and the present invention may be additionally modified or replaced by technical equivalents, such as: adding further optimized modules, and the like. Therefore, structural equivalents made by using the description and drawings of the present invention or by directly or indirectly applying to other related arts are also encompassed within the scope of the present invention.

Claims

1. FPGA driving voltage generation circuit based on FLASH is characterized by comprising: the device comprises a rheostat circuit, a voltage conversion circuit, a push-pull output stage circuit and an electrifying control circuit, wherein the rheostat circuit, the voltage conversion circuit, the push-pull output stage circuit and the electrifying control circuit are connected in sequence;

the push-pull output stage circuit amplifies an output result of the voltage conversion circuit to a required voltage value and is used for providing programming voltage to a storage unit of the FPGA;

2. The FLASH-based FPGA drive voltage generating circuit of claim 1, wherein said power-on control circuit comprises an inverter, a PMOS transistor P1 and an NMOS transistor N1; the input end of the phase inverter is used for receiving an enable signal, and the output end of the phase inverter is connected with the G pole of a PMOS tube P1 and the G pole of an NMOS tube N1; the S pole of the PMOS tube P1 is connected with a power supply, and the S pole of the NMOS tube N1 is grounded; the D pole of the PMOS transistor P1 and the D pole of the NMOS transistor N1 are connected, and are used as the output end VDDP _1 of the power-on control circuit and are connected to the voltage conversion circuit.

3. The FLASH-based FPGA drive voltage generation circuit of claim 1, wherein said voltage conversion circuit comprises a plurality of operational amplifiers; the positive input end of the operational amplifier A1 and the positive input end of the operational amplifier A2 are respectively connected with the output end VDDP _1 through resistors, and the reverse input end of the operational amplifier A1 and the positive input end of the operational amplifier A3 are connected with the positive input end of the operational amplifier A2 and the positive input end of the operational amplifier A3; the positive input end of the operational amplifier A1 is connected with the output end OUT of the rheostat RX2, the A end of the rheostat RX2 is connected with the output end VDDP _1, and the B end is connected with the output end of the operational amplifier A1; the power supply end of the operational amplifier A1 is connected with the output end VDDP _1, and the output end of the operational amplifier A1 is connected with the input end OUT _1 of the rheostat circuit;

4. The FPGA driving voltage generating circuit based on FLASH of claim 3, characterized in that said rheostat RX2 comprises an even number of NMOS transistor pairs, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded; the grid electrode of the first NMOS transistor of all the NMOS transistor pairs is connected to serve as the A end of the rheostat RX2, the drain electrode of the first NMOS transistor of all the NMOS transistor pairs serves as the output end OUT of the rheostat RX2, and the grid electrode of the second NMOS transistor of all the NMOS transistor pairs serves as the B end of the rheostat RX 2.

5. The FLASH-based FPGA drive voltage generating circuit of claim 1, wherein said push-pull output stage circuit comprises an operational amplifier a5 and an inverter connected in series; the inverting input end of the operational amplifier A5 is connected with the output end of the operational amplifier A4, the forward input end is grounded through a resistor and is also connected with the output end of an inverter through a resistor, and the output end of the inverter is used for being connected with the programming voltage input end of the memory cell.

6. A FPGA driving voltage generation method based on FLASH is characterized by comprising the following steps:

the push-pull output stage circuit further amplifies the voltage V3, and the output voltage VPPH is sent to the input end of the programming voltage of the memory cell for programming the memory;

7. The method for generating FPGA driving voltage based on FLASH according to claim 6, wherein the power-on control circuit for performing power supply start-up control of the whole circuit according to the external enable signal comprises the following steps:

8. The method of claim 6 wherein said voltage conversion circuit converts the voltage to a range of a linear amplification region of a push-pull output stage circuit based on the voltage output value of the varistor circuit, comprising the steps of: