CN112133342B - Memory device - Google Patents
Memory device Download PDFInfo
- Publication number
- CN112133342B CN112133342B CN201910556335.4A CN201910556335A CN112133342B CN 112133342 B CN112133342 B CN 112133342B CN 201910556335 A CN201910556335 A CN 201910556335A CN 112133342 B CN112133342 B CN 112133342B
- Authority
- CN
- China
- Prior art keywords
- convolution
- memory
- electrically connected
- terminal
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/045—Combinations of networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Neurology (AREA)
- Semiconductor Memories (AREA)
Abstract
The present application provides a memory comprising: a memory cell including a memory array formed of a plurality of memory elements; and the convolution unit is electrically connected with the storage unit and is provided with a convolution input end, and the convolution unit is used for convolving the storage data of the storage unit and the input data of the convolution input end. In the memory, a storage unit includes a storage array formed of a plurality of storage elements, and a convolution unit convolves storage data of the storage unit with input data of a convolution input terminal. The convolution of the memory is realized in the memory, so that the time for reading data from the memory is saved, and the convolution speed is improved, thereby solving the problem that the convolution speed of the memory with the convolution function in the prior art is lower.
Description
Technical Field
The present application relates to the field of memories, and more particularly, to a memory.
Background
The prior art memory with convolution operation function, such as von neumann memory, needs to access memory and then perform convolution, and the convolution speed is slow and the power consumption is large.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide a memory, so as to solve the problem in the prior art that the convolution speed of a memory with convolution function is slow.
In order to achieve the above object, according to one aspect of the present application, there is provided a memory including: a memory cell including a memory array formed of a plurality of memory elements; and a convolution unit electrically connected to the storage unit, the convolution unit having a convolution input terminal, the convolution unit being configured to convolve the storage data of the storage unit with the input data of the convolution input terminal.
Further, the convolution unit includes: a first selector including a first terminal, a second terminal, and a third terminal, the first terminal of the first selector being electrically connected to the memory element, the second terminal of the first selector being the convolution input terminal; a convolution current generating circuit including a first terminal, a second terminal, and a third terminal, wherein the third terminal of the first selector is electrically connected to the first terminal of the convolution current generating circuit, a convolution voltage is input to the second terminal of the convolution current generating circuit, and a convolution current is output from the third terminal of the convolution current generating circuit; and the analog-to-digital converter comprises an input end and an output end, the input end of the analog-to-digital converter is electrically connected with the third end of the convolution current generation circuit, and the analog-to-digital converter is used for converting the convolution current into a digital signal and outputting the digital signal from the output end of the analog-to-digital converter.
Further, there are a plurality of first selectors, and third terminals of the plurality of first selectors are electrically connected.
Further, the convolution current generation circuit includes: and an operational amplifier including a first terminal, a second terminal, and a third terminal, wherein the first terminal of the operational amplifier is the first terminal of the convolution current generation circuit, and the second terminal of the operational amplifier is the second terminal of the convolution current generation circuit.
Further, the convolution current generation circuit further includes: a third end of the operational amplifier is electrically connected with a grid electrode of the NMOS tube, and a first end of the operational amplifier is electrically connected with a drain electrode of the NMOS tube; and the current mirror comprises an input end and an output end, the input end of the current mirror is electrically connected with the source electrode of the NMOS tube, and the output end of the current mirror is the third end of the convolution current generation circuit.
Further, the current mirror includes: a first PMOS transistor, wherein the drain electrode of the first PMOS transistor is electrically connected with the source electrode of the NMOS transistor, and the source electrode of the first PMOS transistor is electrically connected with a power supply; and a gate of the second PMOS transistor is electrically connected to a source of the NMOS transistor and a gate of the first PMOS transistor, respectively, a source of the second PMOS transistor is electrically connected to a power supply, and a drain of the second PMOS transistor is a third terminal of the convolution current generation circuit.
Further, the convolution unit further includes: and the first control circuit is electrically connected with the convolution current generation circuit and is used for controlling the working state of the convolution current generation circuit.
Further, the first control circuit includes a first enable terminal and an output terminal, the first control circuit output terminal is electrically connected to the second terminal of the convolution current generation circuit, and the first control circuit outputs the convolution voltage when a first enable signal is input to the first enable terminal.
Further, the memory cell includes: a plurality of spaced word lines, each of the word lines being electrically connected to the memory elements in one row of the memory array; a plurality of spaced bit lines each electrically connected to the memory elements in one row of the memory array, and each having one end electrically connected to a first end of the first selector; and a word line driver electrically connected to each of the word lines, the word line driver applying a voltage to the word lines.
Further, the storage unit further includes: a read-write circuit electrically connected to the memory array; a decoder electrically connected to the word line driver, the decoder controlling the operation of the word line driver; and a second control circuit electrically connected to the decoder, the second control circuit controlling an operation of the decoder, the second control circuit including a second enable terminal, the decoder operating when a second enable signal is input to the second enable terminal.
By applying the technical scheme of the application, in the memory, the storage unit comprises a storage array formed by a plurality of storage elements, and the convolution unit convolutes the storage data of the storage unit and the input data of the convolution input end. The memory performs convolution by using the storage data of the memory and the input data of the convolution input end, and the memory can be convolved without accessing the memory, so that the time for reading data from the memory during convolution is saved, the convolution speed is improved, and the problem that the convolution speed of the memory with the convolution function in the prior art is low is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic diagram of a memory according to the present application;
FIG. 2 illustrates a schematic diagram of one embodiment of a memory according to the present application;
FIG. 3 shows a schematic block diagram of another embodiment of a memory according to the present application; and
fig. 4 shows a schematic diagram of convolution currents corresponding to the result of convolution according to an embodiment of the present application.
Wherein the figures include the following reference numerals:
10. a storage unit; 20. a convolution unit; 11. a read-write circuit; 12. a storage element; 13. a word line; 14. a bit line; 15. a word line driver; 16. a decoder; 17. a second control circuit; 170. a second enable terminal; 21. a first selector; 210. a convolution input; 22. a convolution current generating circuit; 23. an analog-to-digital converter; 230. a third enable terminal; 231. a convolution output; 24. a first control circuit; 240. a first enable terminal; 221. an operational amplifier; 222. an NMOS tube; 223. a current mirror; 224. a first PMOS tube; 225. and a second PMOS tube.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background, the convolution speed of the memory with convolution function in the prior art is slow, and in order to solve this problem, according to the embodiment of the present application, a memory is provided.
Fig. 1 is a schematic structural diagram of a memory according to an embodiment of the present application. As shown in fig. 1, the memory includes:
a memory cell 10 including a memory array formed of a plurality of memory elements 12;
In the above memory, the storage unit includes a storage array formed of a plurality of storage elements, and the convolution unit convolves the storage data of the storage unit with the input data of the convolution input terminal. The memory performs convolution by using the storage data of the memory and the input data of the convolution input end, and the memory can be convolved without accessing the memory, so that the time for reading data from the memory during convolution is saved, the convolution speed is improved, and the problem that the convolution speed of the memory with the convolution function in the prior art is low is solved.
It should be noted that the memory array in the memory of the present application includes a plurality of memory elements, each memory element includes a switch and a memory bit, and those skilled in the art can select an appropriate memory bit and switch to form a memory element according to actual situations, for example, the memory bit is an MTJ, and the switch is an NMOS transistor.
The convolution unit in this application may be any circuit structure capable of implementing convolution of data stored in the storage unit and data input by a convolution input terminal, in a specific embodiment of this application, as shown in fig. 1, the convolution unit 20 includes a first selector 21, a convolution current generation circuit 22, and an analog-to-digital converter 23, where the first selector 21 includes a first terminal, a second terminal, and a third terminal, the first terminal of the first selector 21 is electrically connected to the storage element 12, and the second terminal of the first selector 21 is the convolution input terminal 210; the convolution current generation circuit 22 includes a first terminal, a second terminal, and a third terminal, the third terminal of the first selector 21 is electrically connected to the first terminal of the convolution current generation circuit 22, the second terminal of the convolution current generation circuit 22 is inputted with a convolution voltage, and the third terminal of the convolution current generation circuit 22 outputs a convolution current; the analog-to-digital converter 23 includes an input terminal and an output terminal, the input terminal of the analog-to-digital converter 23 is electrically connected to the third terminal of the convolution current generating circuit 22, and the analog-to-digital converter 23 is configured to convert the convolution current into a digital signal and output the digital signal from the output terminal of the analog-to-digital converter 23. The skilled person can select a suitable first selector according to practical situations, for example, the first selector is an NMOS transistor. The first end of the first selector 21 is a source, the second end is a gate, the third end is a drain, and the output end of the analog-to-digital converter 23 is a convolution output end 231 of the convolution unit.
Specifically, a convolution voltage Vc input to the second terminal of the convolution current generation circuit generates a voltage corresponding to the voltage at the first terminal of the convolution current generation circuit, the voltage signal is input to the first selector, a voltage corresponding to the voltage is generated at the first terminal of the first selector, the voltage signal is input to the storage unit, corresponding weight W data is read from the storage unit and input to the first terminal of the first selector, the first selector inputs the selected weight W and the selected convolution input X to the convolution current generation circuit through the third terminal for convolution operation, the convolution current generation circuit generates a convolution current and inputs the convolution current to the input terminal of the analog-to-digital converter, and the analog-to-digital converter converts the convolution current into a digital signal and outputs the digital signal from the output terminal.
The number of the first selectors of the present application may be determined according to actual situations, and for a scheme in which the memory cell includes a memory array having a plurality of rows and a plurality of columns, in order to convolve data of each column, in an embodiment of the present application, as shown in fig. 1, there are a plurality of the first selectors 21, and third terminals of the plurality of the first selectors 21 are electrically connected. The first selectors 21 are in one-to-one correspondence with the storage elements 12, and the third terminals of the first selectors 21 are electrically connected to ensure that the third terminals of the first selectors 21 are electrically connected to the first terminal of the convolution current generation circuit 22, so as to ensure that the output signal of each first selector 21 can be input to the first terminal of the convolution current generation circuit 22. There are three first selectors 21 in fig. 1.
In order to generate an accurate convolution current to ensure that the convolution current is converted into a digital signal to obtain a correct convolution operation result, as shown in fig. 1, in an embodiment of the present application, the convolution current generation circuit 22 includes an operational amplifier 221, the operational amplifier 221 includes a first end, a second end and a third end, the first end of the operational amplifier 221 is the first end of the convolution current generation circuit 22, and the second end of the operational amplifier 221 is the second end of the convolution current generation circuit 22.
In order to generate an accurate convolution current for the analog-to-digital converter to convert the convolution current into a digital signal, in an embodiment of the present application, as shown in fig. 1, the convolution current generation circuit 22 further includes an NMOS transistor 222 and a current mirror 223, wherein a gate of the NMOS transistor 222 is electrically connected to the third terminal of the operational amplifier 221, and a first terminal of the operational amplifier 221 is electrically connected to a drain of the NMOS transistor 222; the current mirror 223 includes an input terminal and an output terminal, the input terminal of the current mirror 223 is electrically connected to the source of the NMOS transistor 222, and the output terminal of the current mirror 223 is the third terminal of the convolution current generating circuit 22. The NMOS tube inputs the convolution current into the current mirror, and the convolution current is mirrored to the input end of the analog-to-digital converter through the current mirror so as to be converted into a digital signal. The convolution current generation circuit can accurately control convolution voltage VCTherefore, the convolution current is accurately controlled, and the precision of convolution operation is further improved.
The NMOS tube in the convolution current generation circuit of the application only plays a role of switching, and the NMOS tube can be replaced by any other devices capable of playing a role of switching, such as a PMOS tube and a triode.
In an embodiment of the present application, as shown in fig. 1, the current mirror 223 includes a first PMOS transistor 224 and a second PMOS transistor 225, wherein a drain of the first PMOS transistor 224 is electrically connected to a source of the NMOS transistor 222, and a source of the first PMOS transistor 224 is electrically connected to a power supply; a gate of the second PMOS transistor 225 is electrically connected to a source of the NMOS transistor 222 and a gate of the first PMOS transistor 224, respectively, a source of the second PMOS transistor 225 is electrically connected to a power supply, and a drain of the second PMOS transistor 225 is a third terminal of the convolution current generating circuit 22.
Of course, the current mirror of the present application is not limited to the above structure, and may be any other current mirror structure, and those skilled in the art may select a suitable structure to form the current mirror of the present application according to practical situations.
The memory of the application can have two working states, wherein the first working state is a convolution working state; the second is a non-convolutional operating state. In order to flexibly control whether the memory is in the convolution operation state, in an embodiment of the present application, as shown in fig. 1, the convolution unit 20 further includes a first control circuit 24, the first control circuit 24 is electrically connected to the convolution current generation circuit 22, and the first control circuit 24 is configured to control the operation state of the convolution current generation circuit 22. That is, the first control circuit can control the operating state of the convolution current generation circuit to turn on or off the convolution function of the memory.
Specifically, as shown in fig. 1, the first control circuit 24 includes a first enable terminal 240 and an output terminal, the output terminal of the first control circuit 24 is electrically connected to the second terminal of the convolution current generation circuit 22, and the first control circuit 24 outputs the convolution voltage when a first enable signal is input to the first enable terminal 240. That is, when the memory is in the convolution operation state, the first enable terminal 240 inputs the first enable signal, the first control circuit 24 outputs the convolution voltage, the convolved voltages are input to an operational amplifier 221, a voltage corresponding to the convolved voltages is generated at a first terminal of the operational amplifier 221, the voltage signal is input to the memory cell 10, the corresponding weight W data is read from the memory cell 10, the first selector 21 inputs the selected weight W and the selected convolution input X to the first end of the first selector 21, the first selector 21 inputs the selected weight W and the selected convolution input X to the convolution current generating circuit 22 through the third end to perform convolution operation, the convolution current generating circuit 22 generates convolution current to be input to the input end of the analog-to-digital converter 23, the third enabling end 230 inputs a third enabling signal, the analog-to-digital converter 23 converts the convolution current into a digital signal and outputs the digital signal from the convolution output end 231, and therefore convolution operation of the convolution input X and the weight W is achieved; when the memory is in a non-convolution working state, the first control circuit controls the convolution function of the memory to be closed, the first enable signal is not input to the first enable end, the output end of the first control circuit stops outputting convolution voltage, the convolution current generation circuit stops working, and therefore convolution operation is stopped.
In order to flexibly control the operation state of the analog-to-digital converter, in an embodiment of the present application, as shown in fig. 1, the analog-to-digital converter further includes a third enable terminal, and in a case that a third enable signal is input to the third enable terminal, the analog-to-digital converter converts the convolution current into a digital signal. The analog-digital converter has two working states, namely, the analog-digital converter works under the condition that the third enabling end inputs a third enabling signal, and does not work otherwise.
In the present application, the weight in the convolution operation is the storage data of the storage bit in the storage array, and therefore, the storage array may also be referred to as a weight storage array. Specifically, the memory cells may be MRAM, RRAM, PRAM, DRAM, SRAM, NOR FLASH, and NAND FLASH arrays.
In one embodiment of the present invention, in order to facilitate reading and writing of stored data, as shown in fig. 1, the memory cell 10 includes a plurality of spaced word lines 13, a plurality of spaced bit lines 14 and a word line driver 15, wherein each of the word lines 13 is electrically connected to the memory elements 12 in one row of the memory array; each of the bit lines 14 is electrically connected to the memory elements 12 in one row of the memory array, and one end of the bit line 14 is electrically connected to a first end of the first selector 21; the word line driver 15 is electrically connected to each of the word lines 13, and the word line driver 15 applies a voltage to the word lines.
In the practical application process of the memory, in order to facilitate the control of the operation of the memory unit and the reading and writing of the memory, in an embodiment of the present application, as shown in fig. 1, the memory unit 10 further includes a reading and writing circuit 11, a decoder 16, and a second control circuit 17, where the reading and writing circuit 11 is electrically connected to the memory array; a decoder 16 electrically connected to the word line driver 15, the decoder 16 controlling the operation of the word line driver 15; the second control circuit 17 is electrically connected to the decoder 16, the second control circuit 17 controls the operation of the decoder 16, and the second control circuit 17 includes a second enable terminal 170, and the decoder 16 operates when a second enable signal is input to the second enable terminal 170. When the read-write function of the memory is started, a second enabling end inputs a second enabling signal, the decoder works, the word line driver applies voltage to the word line, and the read-write circuit realizes the read-write operation of the weight W; when the read-write function of the memory is closed, the second enabling end stops inputting the second enabling signal, the decoder stops working, the word line driver stops applying the voltage to the word line, and the read-write circuit stops the read-write operation.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.
Example 1
As shown in fig. 2, the memory includes a memory cell 10 and a convolution unit 20, wherein the memory cell 10 includes a read/write circuit 11, a memory element 12, a word line 13, a bit line 14, a word line driver 15, a decoder 16 and a second control circuit 17, the memory element 12 is composed of a memory bit and a switch, the convolution unit 20 includes a first selector 21, a convolution current generation circuit 22 and an analog-to-digital converter 23, the convolution current generation circuit 22 includes a first control circuit 24, an operational amplifier 221, an NMOS transistor 222 and a current mirror 223, the word line 13 corresponds to a BL in fig. 2, the bit line 14 corresponds to a WL in fig. 2, and specific connection relationships are shown in fig. 2. The memory cell 10 is an MRAM memory array, the corresponding memory bit is MTJ, the first selector 21 is an NMOS selector, and the current mirror 223 is composed of two PMOS transistors.
The working state of the memory is two, the first working state is that only the memory cell works, in the state, the first enabling end does not input the first enabling signal, the second enabling end inputs the second enabling signal, the third enabling end does not input the third enabling signal, under the condition that the second enabling end inputs the second enabling signal, the memory cell works; the second operating state is that the storage unit and the convolution unit are both operated, in this state, the first enable terminal inputs a first enable signal, the second enable terminal inputs a second enable signal, the third enable terminal inputs a third enable signal, the storage unit is operated when the second enable terminal inputs the second enable signal, and the convolution unit is operated when the first enable terminal inputs the first enable signal and the third enable terminal inputs the third enable signal.
Example 2
As shown in fig. 3, the present embodiment is different from embodiment 1 in that: the memory cell is an SRAM memory array.
When the memory of embodiment 1 or embodiment 2 is used for convolution operation, the convolution input X is a 3 × 3 matrix, the number in the matrix is 0 or 1, the weight W is a three-dimensional vector, the number in the vector is-1 or 1, the convolution input X and the weight W are convolved, the convolution result is shown in the following table, and the convolution current corresponding to the convolution result is shown in fig. 4.
TABLE 1
| Number of 1 in X | Convolution (W X) |
| 0 | 0 |
| 1 | -1、+1 |
| 2 | -2、0、+2 |
| 3 | -3、-1、+1、+3 |
| 4 | -4、-2、0、+2、+4 |
| 5 | -5、-3、-1、+1、+3、+5 |
| 6 | -6、-4、-2、0、+2、+4、+6 |
| 7 | -7、-5、-3、-1、+1、+3、+5、+7 |
| 8 | -8、-6、-4、-2、0、+2、+4、+6、+8 |
| 9 | -9、-7、-5、-3、-1、+1、+3、+5、+7、+9 |
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
in the memory of the present application, the memory cell includes a memory array formed of a plurality of memory elements, and the convolution unit convolves the memory data of the memory cell with the input data of the convolution input terminal. The memory performs convolution by using the storage data of the memory and the input data of the convolution input end, and the memory can be convolved without accessing the memory, so that the time for reading data from the memory during convolution is saved, the convolution speed is improved, and the problem that the convolution speed of the memory with the convolution function in the prior art is low is solved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A memory, comprising:
a memory cell including a memory array formed of a plurality of memory elements;
the convolution unit is electrically connected with the storage unit and is provided with a convolution input end, and the convolution unit is used for convolving the storage data of the storage unit and the input data of the convolution input end;
the convolution unit includes:
a first selector including a first terminal, a second terminal and a third terminal, the first terminal of the first selector being electrically connected to the memory element, the second terminal of the first selector being the convolution input terminal;
the convolution current generation circuit comprises a first end, a second end and a third end, the third end of the first selector is electrically connected with the first end of the convolution current generation circuit, the second end of the convolution current generation circuit inputs convolution voltage, and the third end of the convolution current generation circuit outputs convolution current;
and the input end of the analog-to-digital converter is electrically connected with the third end of the convolution current generation circuit, and the analog-to-digital converter is used for converting the convolution current into a digital signal and outputting the digital signal from the output end of the analog-to-digital converter.
2. The memory according to claim 1, wherein the first selector has a plurality of first selectors, and third terminals of the plurality of first selectors are electrically connected.
3. The memory of claim 1, wherein the convolution current generation circuit comprises:
and the operational amplifier comprises a first end, a second end and a third end, wherein the first end of the operational amplifier is the first end of the convolution current generation circuit, and the second end of the operational amplifier is the second end of the convolution current generation circuit.
4. The memory of claim 3, wherein the convolution current generation circuit further comprises:
the third end of the operational amplifier is electrically connected with the grid electrode of the NMOS tube, and the first end of the operational amplifier is electrically connected with the drain electrode of the NMOS tube;
the current mirror comprises an input end and an output end, the input end of the current mirror is electrically connected with a source electrode of the NMOS tube, and the output end of the current mirror is the third end of the convolution current generating circuit.
5. The memory of claim 4, wherein the current mirror comprises:
the drain electrode of the first PMOS tube is electrically connected with the source electrode of the NMOS tube, and the source electrode of the first PMOS tube is electrically connected with a power supply;
and the grid electrode of the second PMOS tube is respectively and electrically connected with the source electrode of the NMOS tube and the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is electrically connected with a power supply, and the drain electrode of the second PMOS tube is the third end of the convolution current generation circuit.
6. The memory of claim 1, wherein the convolution unit further comprises:
and the first control circuit is electrically connected with the convolution current generation circuit and is used for controlling the working state of the convolution current generation circuit.
7. The memory according to claim 6, wherein the first control circuit comprises a first enable terminal and an output terminal, the first control circuit output terminal is electrically connected to the second terminal of the convolution current generation circuit, and the first control circuit outputs the convolution voltage in a case where a first enable signal is input to the first enable terminal.
8. The memory according to any one of claims 1 to 7, wherein the storage unit comprises:
a plurality of spaced word lines, each of the word lines being electrically connected to a respective one of the memory elements of a row of the memory array;
a plurality of spaced bit lines, each of the bit lines being electrically connected to the memory elements of a column of the memory array, and one end of each of the bit lines being electrically connected to the first end of the first selector;
a word line driver electrically connected to each of the word lines, the word line driver for applying a voltage to the word lines.
9. The memory of claim 8, wherein the storage unit further comprises:
the read-write circuit is electrically connected with the storage array;
the decoder is electrically connected with the word line driver and is used for controlling the work of the word line driver;
and the second control circuit is electrically connected with the decoder and is used for controlling the operation of the decoder, the second control circuit comprises a second enabling end, and the decoder operates under the condition that a second enabling signal is input to the second enabling end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910556335.4A CN112133342B (en) | 2019-06-25 | 2019-06-25 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910556335.4A CN112133342B (en) | 2019-06-25 | 2019-06-25 | Memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112133342A CN112133342A (en) | 2020-12-25 |
| CN112133342B true CN112133342B (en) | 2022-05-06 |
Family
ID=73849463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910556335.4A Active CN112133342B (en) | 2019-06-25 | 2019-06-25 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112133342B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170023708A (en) * | 2015-08-24 | 2017-03-06 | (주)뉴로컴즈 | Convolutional neural network computing apparatus |
| CN108073548A (en) * | 2016-11-14 | 2018-05-25 | 耐能股份有限公司 | Convolution algorithm device and convolution algorithm method |
| JP2018124867A (en) * | 2017-02-02 | 2018-08-09 | 富士通株式会社 | Arithmetic processing device and control method therefor |
| CN108717571A (en) * | 2018-06-01 | 2018-10-30 | 阿依瓦（北京）技术有限公司 | A kind of acceleration method and device for artificial intelligence |
| KR20180128267A (en) * | 2017-05-23 | 2018-12-03 | 고려대학교 산학협력단 | Bidirectional fifo memoy and processing device for convoultion using the same |
| CN108985450A (en) * | 2018-06-28 | 2018-12-11 | 中国人民解放军国防科技大学 | Vector processor-oriented convolution neural network operation vectorization method |
| EP3489863A1 (en) * | 2017-11-28 | 2019-05-29 | Nanjing Horizon Robotics Technology Co., Ltd. | Method and apparatus for performing operation of convolutional layer in convolutional neural network |
-
2019
- 2019-06-25 CN CN201910556335.4A patent/CN112133342B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170023708A (en) * | 2015-08-24 | 2017-03-06 | (주)뉴로컴즈 | Convolutional neural network computing apparatus |
| CN108073548A (en) * | 2016-11-14 | 2018-05-25 | 耐能股份有限公司 | Convolution algorithm device and convolution algorithm method |
| JP2018124867A (en) * | 2017-02-02 | 2018-08-09 | 富士通株式会社 | Arithmetic processing device and control method therefor |
| KR20180128267A (en) * | 2017-05-23 | 2018-12-03 | 고려대학교 산학협력단 | Bidirectional fifo memoy and processing device for convoultion using the same |
| EP3489863A1 (en) * | 2017-11-28 | 2019-05-29 | Nanjing Horizon Robotics Technology Co., Ltd. | Method and apparatus for performing operation of convolutional layer in convolutional neural network |
| CN108717571A (en) * | 2018-06-01 | 2018-10-30 | 阿依瓦（北京）技术有限公司 | A kind of acceleration method and device for artificial intelligence |
| CN108985450A (en) * | 2018-06-28 | 2018-12-11 | 中国人民解放军国防科技大学 | Vector processor-oriented convolution neural network operation vectorization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112133342A (en) | 2020-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110825345B (en) | Multiplication using non-volatile memory cells | |
| CN113467751B (en) | Analog domain memory internal computing array structure based on magnetic random access memory | |
| CN101174467B (en) | Self-reference sense amplifier circuit and sensing method | |
| CN110797063B (en) | Memristor memory chip and operation method thereof | |
| CN103050148A (en) | Resistive memory apparatus, layout structure, and sensing circuit thereof | |
| CN106898371B (en) | Three-dimensional memory reading circuit and word line and bit line voltage configuration method thereof | |
| JP2011198407A (en) | Nonvolatile semiconductor memory and method for manufacturing the same | |
| CN114902334A (en) | Tri-state programming of memory cells | |
| WO2021051548A1 (en) | Read-write circuit and read-write method for memristor | |
| US9401207B2 (en) | Pseudo SRAM using resistive elements for non-volatile storage | |
| CN111755045A (en) | Semiconductor memory device with a plurality of memory cells | |
| US20210117499A1 (en) | Methods to tolerate programming and retention errors of crossbar memory arrays | |
| US7701747B2 (en) | Non-volatile memory including sub cell array and method of writing data thereto | |
| TWI778674B (en) | Signal preserve in mram during reading | |
| CN112133342B (en) | Memory device | |
| TWI773393B (en) | Signal amplification in mram during reading | |
| CN204667887U (en) | Memory device | |
| CN110136760B (en) | MRAM chip | |
| Bazzi et al. | Design of a Novel Hybrid CMOS Non-Volatile SRAM Memory in 130nm RRAM Technology | |
| KR102157360B1 (en) | Memroy Device and Memroy Cell Array | |
| CN219658388U (en) | Memory device and write circuit thereof | |
| US20230162785A1 (en) | Non-volatile memory based compute-in-memory cell | |
| TWI631562B (en) | Resistive non-volatile memory group and memory architecture and associated operation method | |
| TW202247184A (en) | Memory device | |
| TW202341150A (en) | Memory system and operating method of memory array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |