CN110136760B

CN110136760B - MRAM chip

Info

Publication number: CN110136760B
Application number: CN201810130958.0A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2021-03-23
Anticipated expiration: 2038-02-09
Also published as: CN110136760A

Abstract

The invention discloses an MRAM chip, wherein an MRAM array comprises a plurality of sub-arrays, each sub-array comprises a common source line connected to all units and a plurality of bit lines connected to each column; each bit line is connected with the first transmission gate and the second transmission gate; the first transmission gate is connected with the common source line, and the second transmission gate is connected with a common bit line; the pre-decoder includes: a plurality of address line inputs, selection signals matched with the number of the bit lines and outputs of inverted signals of the selection signals; and the selection signal and the inverted signal output end thereof are connected to the first transmission gate and the second transmission gate corresponding to the corresponding bit line of each sub array, and the first transmission gate and the second transmission gate are controlled to be opened or closed. By the control of the pre-decoder, only one bit is written in one array at a time, high voltage and negative voltage are not needed any more, the design is simple, and the energy consumption is reduced.

Description

MRAM chip

Technical Field

The present invention relates to semiconductor chips, and more particularly, to MRAM chips.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory.

The chip has good economy, and the silicon chip area occupied by unit capacity has great advantages compared with SRAM, NOR Flash frequently used in the chips and embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to the best SRAM, and the power consumption is the best in various memory and storage technologies. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash. The MRAM may be integrated with the logic circuit in one chip.

The principle of MRAM is based on a structure called MTJ (magnetic tunnel junction). It is composed of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. The lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance. The process of reading the MRAM is to measure the resistance of the MTJ. Using the newer STT-MRAM technology, writing to MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

Each memory cell of MRAM consists of an MTJ and a MOS transistor. The gate of the MOS tube is connected to Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on Bit Line of the chip. The read and write operations are performed on Bit Line.

An MRAM chip is made up of one or more arrays of MRAM memory cells, each array having a number of external circuits, such as: a row address decoder: changing the received address into a Word Line selection; a column address decoder: changing the received address into a selection of Bit Line; a read-write controller: controlling a read (measure) write (add current) operation on the Bit Line; input and output control: and exchange data externally.

Currently, the BL and SL vertical layout is adopted, which is beneficial to reducing the chip area occupied by each memory cell and reducing the cost. The operation is slightly more complex when writing: pulling a word line high opens the row and places the source line of the row at an intermediate potential. Then high or low potentials are applied to the bit lines, respectively, as required for each cell to write a 0 or 1. The low potential may be a negative voltage.

The BL and SL vertical layout scheme can reduce the cost, but has the following two problems:

1. since a fixed voltage drop is required across the memory cell during writing, the difference between the high and low voltages required for this approach is twice that of the BL and SL parallel scheme. The chip requires the use of either a high voltage, which cannot be supplied externally, or a negative voltage. Both cases require different voltages to be generated in the internal design circuit, and voltage conversion brings about reduction of power utilization efficiency and additional cost.

2. During writing, the current required by the whole Line flows in from the same Bit Line. Difficulties often arise in design due to insufficient SL source line width.

Disclosure of Invention

In view of the foregoing drawbacks of the prior art, an object of the present invention is to provide an MRAM chip, including: an MRAM array and a pre-decoder with source lines and bit lines arranged vertically, wherein the MRAM array comprises a plurality of sub-arrays, the sub-arrays comprise a common source line connected to all the units and a plurality of bit lines connected to each column; each bit line is connected with the first transmission gate and the second transmission gate; the first transmission gate is connected with the common source line, and the second transmission gate is connected with a common bit line; the pre-decoder includes: a plurality of address line inputs, selection signals matched with the number of the bit lines and outputs of inverted signals of the selection signals; and the selection signal and the inverted signal output end thereof are connected to the first transmission gate and the second transmission gate corresponding to the corresponding bit line of each sub array, and the first transmission gate and the second transmission gate are controlled to be opened or closed.

Preferably, the sub-array further includes: and the reference bit line of the reference unit column is respectively connected with the common source line and the reference input end through two third transmission gates.

Preferably, the common bit line and the common source line are connected with a read-write unit.

Preferably, when one bit line is selected by the pre-decoder, the selection signal matched with the bit line is opposite to the signals output by other selection signals.

Compared with the prior art, the invention effectively solves the problems of high cost and difficult manufacture, only one bit is written in one array at a time through the control of the pre-decoder, and the problem of insufficient power supply of a source line is solved, so that high voltage and negative voltage are not needed any more, the design is simple, and the energy consumption is reduced. And the sense amplifier is shared, so that the cost is effectively reduced.

The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.

Drawings

FIG. 1 is a circuit diagram of a precoder in accordance with the present invention;

FIG. 2 is a circuit diagram of a predecoder of the present invention;

fig. 3 is a circuit diagram of the first transfer gate and the second transfer gate of the present invention.

Detailed Description

As shown, fig. 1 is a circuit diagram of a precoder of the present invention, fig. 2 is a circuit diagram of a predecoder of the present invention, and an MRAM chip includes: the MRAM array and the pre-decoder 3 are vertically arranged by a source line 2 and a bit line 1, the source line 2(SL) of the MRAM array is vertically arranged by the bit line 1(BL), a common bit line 7 is connected with a plurality of bit lines 1, wherein the MRAM array comprises a plurality of sub-arrays, the sub-arrays comprise a common source line 8 connected to all units, the common source line 8 is connected with a plurality of bit lines 1 in each column, specifically, every n columns can be adopted to form a group, the sub-arrays comprise a common source line 8 connected with a plurality of source lines 2, and the SLs in all rows in each group are connected together through a common SL; each bit line 1 is connected with a first transmission gate and a second transmission gate; the first transmission gate is connected with a common source line 8, and the second transmission gate is connected with a common bit line 7; each sub-array is connected to a pre-decoder 3, the pre-decoder 3(Y Predecoder) comprising: a plurality of address line inputs 31 (inputting k address lines), selection signals and inverted signal outputs in a number matching the number of bit lines 1; and the output end of the selection signal and the inverted signal thereof are connected to the first transmission gate and the second transmission gate corresponding to the bit line 1 corresponding to each sub array, and the first transmission gate and the second transmission gate are controlled to be opened or closed.

FIG. 3 is a circuit diagram of a first transfer gate, a second transfer gate of the present invention, further, selecting signal 4(YDEP), inverting signal output 5(YDEN), the two signals being opposite, and inverting for selected column x, YDEPx and the other YDEP < n-1,0 >; the first transfer gate includes: the first PMOS12 is connected in parallel with the first NMOS11, the selection signal 4 controls the switch of the first PMOS12, and the second output end controls the switch of the first NMOS 11; the second transfer gate includes: a second PMOS22, a second NMOS21, an inverted signal output terminal 5 controlling the switch of the second PMOS22, and a selection signal 4 controlling the switch of the second NMOS 21.

Specifically, in the specific implementation process of the invention: for each column of BL < n-1,0>, two transfer gates are configured. One transfer gate connects it to the common SL and the other to the common BL. The YDEP and YDEN signals control the on-off of the transmission gates, and the connection sequence of the two transmission gates YDEP and YDEN is opposite, so that one transmission gate is opened and the other transmission gate is closed. For the selected row x, the Y-Predecoder opens the connection of BLx and the common BL. For the other rows, the connection of BLx and common SL is opened.

Further, the sub-array further includes: the pre-decoder 3 has a reference input terminal, and the reference bit line 1 of the reference cell column is connected to the common source line 8 and the reference input terminal through two third transmission gates.

Specifically, in this case, the Y-Predecoder adds a read/write control signal input. The two transfer gates of the reference column connect their BL to a common SL one and to the reference input of the read circuit. In a read mode, the column represented by the address signal is selected, while the reference column is selected and connected to the read circuit.

In one embodiment of the present invention: k-3, n-8 + 1-9 is a common choice. With 8 columns selected by 3 address lines and a column of reference cells.

Furthermore, the common bit line 7 and the common source line 8 are connected with the read-write unit.

Further, if the pre-decoder 3 selects a bit line 1, the selection signal 4 matching the bit line 1 is opposite to the signals output by the other selection signals 4.

The common BL and the common SL of the present invention are connected to the read/write unit. Thus, only the selected column is read and written at a time. The other columns, because their BL and SL are shorted, do not read or write operations, although the select transistor is open.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. An MRAM chip, comprising: an MRAM array and a pre-decoder with source lines and bit lines arranged vertically, wherein the MRAM array comprises a plurality of sub-arrays, the sub-arrays comprise a common source line connected to all the cells and a plurality of bit lines connected to each column; each column of the bit lines is connected with a first transmission gate and a second transmission gate, the first transmission gate is connected between the bit line and the common source line, and the second transmission gate is connected between the bit line and the common bit line; the pre-decoder includes: a plurality of address line inputs, selection signals matched with the number of the bit lines and outputs of inverted signals of the selection signals; the selection signal and the inverted signal output end are connected to a first transmission gate and a second transmission gate corresponding to a bit line corresponding to each sub array, and the first transmission gate and the second transmission gate are controlled to be opened or closed.

2. The MRAM chip of claim 1, wherein the sub-array further comprises: and the reference bit line of the reference unit column is respectively connected with the common source line and the reference input end through two third transmission gates.

3. The MRAM chip of claim 1, wherein the common bit line, the common source line are connected to a read-write unit.

4. The MRAM chip of claim 2, wherein the pre-decoder selects a bit line, and wherein a select signal matching the bit line is opposite to the signal output by the other select signals.