CN108288481B

CN108288481B - Voltage-adjustable MRAM (magnetic random Access memory) reading circuit

Info

Publication number: CN108288481B
Application number: CN201810053311.2A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Information Technologies Co ltd
Current assignee: Shanghai Information Technologies Co ltd
Priority date: 2018-01-19
Filing date: 2018-01-19
Publication date: 2021-10-01
Anticipated expiration: 2038-01-19
Also published as: CN108288481A

Abstract

The invention discloses a voltage-adjustable MRAM read-out circuit, which comprises a current mirror, a reference unit group, a control current-limiting unit and an operational amplifier OP Amp; and controlling the clamping voltage V _ clamp of the current limiting control unit through the feedback action of the operational amplifier OP Amp, so that the voltage applied to the reference unit of the reference unit group is stabilized to be about V _ read. Furthermore, the input reference voltage V _ read of the operational amplifier OP Amp may also be adjusted by a configurable reference voltage generator. The reading circuit disclosed by the invention uses the feedback circuit to dynamically adjust the clamping voltage, so that the same MRAM module can adapt to different embedded environments and achieve the optimal power consumption in different environments.

Description

Voltage-adjustable MRAM (magnetic random Access memory) reading circuit

Technical Field

The invention belongs to the field of semiconductor chip memories, and particularly relates to a voltage-adjustable MRAM (magnetic random Access memory) reading circuit.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration and can be written repeatedly for unlimited times. MRAM can be read and written randomly as fast as SRAM/DRAM, and can also permanently retain data after power-off as Flash memory.

MRAM has very good economy and performance, and its unit capacity occupies silicon area which is much more advantageous than SRAM, and also more advantageous than NOR Flash which is often used in such chips, and much more advantageous than embedded NOR Flash. The MRAM read-write time delay is close to the best SRAM, and the power consumption is the best in various memories and storage technologies; MRAM is compatible with standard CMOS semiconductor technology, DRAM and Flash are incompatible with standard CMOS semiconductor technology; the MRAM can also be integrated with the logic circuit in one chip.

MRAM is based on MTJ (magnetic tunnel junction) architecture. Consisting of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance.

The process of reading the MRAM is to measure the resistance of the MTJ. Writing MRAM uses a relatively new STT-MRAM technology to write through MTJs using a stronger current than reading. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

As shown in FIG. 2, each MRAM memory cell is composed of an MTJ and an NMOS transistor. The gate electrode (gate) of the NMOS tube is connected to the Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on the Bit Line of the chip. The read and write operations are performed on Bit Line.

As shown in fig. 3, an MRAM chip is composed of one or more arrays of MRAM memory cells, each array having a number of external circuits, such as:

● Row Address decoder: selection of changing received address to Word Line

● column address decoder: selection of changing received address to Bit Line

● read/write controller: controlling read (measure) write (add current) operations on Bit Line

● input-output control: exchange data with the outside

The read-out circuit of an MRAM needs to detect the resistance of the MRAM memory cell. Since the resistance of the MTJ may drift with temperature or the like, a common method is to use some memory cells on the chip that have been written to a high resistance state or a low resistance state as reference cells. The resistance of the memory cell and the reference cell are compared using a Sense Amplifier (Sense Amplifier).

The read process of an MRAM is the detection and comparison of the resistance of the memory cell. Whether the memory cell is in the high resistance state or the low resistance state is generally determined by combining the reference cell into a standard resistance to compare with the memory cell.

Fig. 4 is a schematic diagram of an MRAM readout circuit in the prior art, where P1, P2, and P3 shown in fig. 4 are the same PMOS transistors, forming a current mirror, and the current of each path above is equal (I _ read). The difference in resistance causes a difference between V _ out and V _ out _ n, which is input to the comparator of the next stage to generate an output. The example in fig. 4 is a path of memory cells, comparing a path of reference cells in P state with a path of reference cells in AP state. In actual use, multiple memory cells can be compared with m AP and n P reference cells.

V _ clamp in fig. 4 is a clamp voltage, controls the resistance of NMOS transistors such as N1, N2, and N3, and protects the memory cell reference cell from being affected by the high voltage, and generally adopts a fixed voltage. However, the selection of this voltage affects the signal-to-noise ratio and power consumption during the read operation, and when the voltage is too low, the signal-to-noise ratio is insufficient, and when the voltage is too high, the power consumption is large. For embedded MRAM, noise is affected not only by its embedded environment, but also by temperature.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a voltage-adjustable MRAM readout circuit, which uses a feedback circuit to dynamically adjust a clamping voltage, so that the same MRAM module can adapt to different embedded environments, and achieve optimal power consumption in different environments.

In order to achieve the above object, the present invention provides a voltage-adjustable MRAM readout circuit, which includes a current mirror, a reference cell group, a control current-limiting unit, and an operational amplifier OP Amp.

The current mirror is composed of identical PMOS tubes, wherein the current of each PMOS tube is I _ read.

The reference unit group comprises a group of reference units connected in parallel, wherein part of the reference units are placed in a P state, and the other reference units are placed in an AP state; one end of the reference unit group is grounded, the other end of the reference unit group is connected with the control current limiting unit, and the connection point is A.

The control current limiting unit consists of a group of equivalent NMOS tubes controlled by the same clamping voltage V _ clamp, and the clamping voltage V _ clamp is used for controlling the resistance of the NMOS tubes.

One input of the operational amplifier OP Amp is a reference voltage V _ read, the other input is the potential V _ A of the point A, the output of the operational amplifier OP Amp is connected to the clamping voltage V _ clamp, and the voltage applied to the reference unit is controlled to be stabilized around the V _ read through a feedback effect.

Further, the sensing circuit also includes a configurable reference voltage generator that outputs the reference voltage V _ read.

Further, the configurable reference voltage generator adjusts the V _ read by register configuration of the MRAM.

Further, the configurable reference voltage generator inputs a temperature of a temperature sensor within the MRAM chip, and adjusts the reference voltage V _ read according to the temperature.

The reading circuit disclosed by the invention uses the feedback circuit to dynamically adjust the clamping voltage, so that the influence of the clamping voltage on the signal-to-noise ratio and the power consumption during reading operation is reduced, and the same MRAM module can adapt to different embedded environments and achieve the optimal power consumption in different environments.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ.

FIG. 2 is a schematic diagram of a prior art MRAM memory cell architecture.

Fig. 3 is a prior art MRAM chip architecture diagram.

Fig. 4 is a schematic diagram of a prior art MRAM read circuit.

FIG. 5 is a schematic diagram of a voltage-tunable MRAM read circuit according to a preferred embodiment of the invention.

Detailed Description

The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to more readily understand the advantages and features of the present invention, and to clearly and unequivocally define the scope of the present invention.

Fig. 5 shows a voltage-tunable MRAM readout circuit comprising a current mirror 1, a reference cell group 2, a control current limiting unit 3 and an operational amplifier OP Amp 4.

The current mirror 1 is composed of equivalent PMOS tubes, wherein the current of each PMOS tube is I _ read, the difference of the resistances causes the difference of V _ out and V _ out _ n, and the difference is input to a comparator of the next stage to generate an output.

The reference unit group 2 comprises a group of reference units which are connected in parallel, part of the reference units are arranged in a P state, the other reference units are arranged in an AP state, one end of the reference unit group is grounded, the other end of the reference unit group is connected with the control current limiting unit 3, and the connection point is A. In fig. 5, a path of memory cell R is used to compare a path of reference cell in P state with a path of reference cell in AP state, and in actual use, there may be multiple paths of memory cells 2 to compare m paths of AP state reference cells and n paths of P state reference cells connected in parallel.

The control current limiting unit 3 is composed of a group of equivalent NMOS tubes controlled by the same clamping voltage V _ clamp, and the clamping voltage V _ clamp is used for controlling the resistance of the NMOS tubes and protecting the storage unit and the reference unit 2 from being influenced by high voltage.

One input of the operational amplifier OP Amp4 is a reference voltage V _ read, the other input is a potential V _ A at the point A, the output of the amplifier OP Amp4 is connected to a clamp voltage V _ clamp, and the voltage applied to the reference cells of the reference cell group 2 is controlled to be stabilized around V _ read by a feedback effect.

In the preferred embodiment of the present invention, the sensing circuit further includes a configurable reference voltage generator 5, and the configurable reference voltage generator 5 outputs a reference voltage V _ read, which can be adjusted by register configuration of the MRAM.

In addition, the output temperature of the temperature sensor in the MRAM chip can be connected to the configurable reference voltage generator 5, and the reference voltage V _ read can be adjusted according to the temperature.

The read-out results are obtained by connecting the outputs V _ out and V _ out _ n shown in fig. 5 to a comparator.

The reading circuit disclosed by the embodiment uses the feedback circuit to dynamically adjust the clamping voltage, so that the influence of the clamping voltage on the signal-to-noise ratio and the power consumption during reading operation is reduced, and the same MRAM module can adapt to different embedded environments and achieve the optimal power consumption in different environments.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. A voltage-adjustable MRAM read-out circuit comprises a current mirror, a reference unit group, a control current-limiting unit and an operational amplifier OP Amp,

the current mirror is composed of equivalent PMOS tubes, wherein the current of each PMOS tube is I _ read, the difference of V _ out and V _ out _ n is caused by the difference of resistors, and the difference is input to a comparator at the next stage to generate output;

the reference unit group comprises a group of reference units connected in parallel, wherein part of the reference units are placed in a P state, and the other reference units are placed in an AP state; one end of the reference unit group is grounded, and the other end of the reference unit group is connected with the control current limiting unit, wherein the connection point is A;

the control current-limiting unit consists of a group of equivalent NMOS tubes controlled by the same clamping voltage V _ clamp, and the clamping voltage V _ clamp is used for controlling the resistance of the NMOS tubes and protecting the storage unit and the reference unit from being influenced by high voltage;

2. The voltage adjustable MRAM sensing circuit of claim 1, wherein the sensing circuit further comprises a configurable reference voltage generator that outputs the reference voltage V read.

3. The voltage adjustable MRAM readout circuit of claim 2, wherein the configurable reference voltage generator adjusts the V read by a register configuration of the MRAM.

4. The voltage adjustable MRAM readout circuit of claim 2, wherein the configurable reference voltage generator inputs a temperature of a temperature sensor within the MRAM chip, the reference voltage V read being adjusted according to the temperature.