CN108257635B - Magnetic random access memory and reading method thereof - Google Patents
Magnetic random access memory and reading method thereof Download PDFInfo
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- CN108257635B CN108257635B CN201611238874.6A CN201611238874A CN108257635B CN 108257635 B CN108257635 B CN 108257635B CN 201611238874 A CN201611238874 A CN 201611238874A CN 108257635 B CN108257635 B CN 108257635B
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Abstract
The invention provides a magnetic random access memory, which comprises a plurality of arrays consisting of magnetoresistive memory cells, wherein a source line of each array is parallel to word lines, each array also comprises two rows of reference cells connected with two reference bit lines, each i word line corresponds to one reference word line, wherein i is a positive integer, and the reference word lines are connected with all the reference cells on the corresponding row. The invention also provides a reading method of the magnetic random access memory. According to the magnetic random access memory and the reading method thereof provided by the invention, by adopting the layout of the new reference units, when the i-row storage units in the array are read, the same average value of the i-row reference units is used, so that the number of the reference units in each array is reduced, and the problem of overhigh ratio of the number of the reference units to the number of the storage units in the small-capacity magnetic random access memory is solved.
Description
Technical Field
The invention relates to the field of memories of semiconductor chips, in particular to a magnetic random access memory and a reading method thereof.
Background
Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration and can be written repeatedly for unlimited times.
A magnetic random access memory is composed of an array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a structure called a Magnetic Tunnel Junction (MTJ). A magnetic tunnel junction is comprised of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. One of the ferromagnetic layers is a reference layer with a fixed magnetization direction, and the other ferromagnetic layer is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. The resistance value of the magnetic tunnel junction depends on the magnetization directions of the two layers of ferromagnetic material: the magnetic tunnel junction resistance is low if they are in the same direction, whereas the magnetic tunnel junction resistance is high. Typically, the high resistance state is a logic "1" and the low resistance state is a logic "0". Changing the magnetization direction of the memory layer changes the resistance state of the magnetic tunnel junction, and sensing the resistance state of the magnetic tunnel junction allows the stored contents of the magnetoresistive memory cell to be known.
Different magnetic random access memories use different methods to change the magnetization direction of the memory layer. The first generation of field switching magnetic random access memory uses a large current to generate a magnetic field at the magnetic tunnel junction to change the direction of the magnetic field in the memory layer. The new spin torque transfer magnetic random access memory (STT MRAM) uses a current pulse directly across a magnetic tunnel junction, the direction of which can change the magnetization direction of the memory layer, thereby determining the resistance state of the magnetic tunnel junction and the logic state of the magnetoresistive memory cell. The novel magnetic random access memory not only has very low energy consumption, but also can meet the requirement of further shrinking the node size of a semiconductor chip in the future because the required switching current can be reduced along with the reduction of the size of a magnetic tunnel junction. However, as the number of magnetic tunnel junctions in the magnetic random access memory is increased and the size is reduced, the requirements on the manufacturing process are higher and higher, and the uniformity of the magnetoresistance in the existing process is poorer and poorer.
Reading the data of a magnetoresistive memory cell is to detect whether its magnetic tunnel junction is in a high resistance state "1" or a low resistance state "0". In order to accurately distinguish the resistance states, the magnetic tunnel junction is required to achieve a high magneto-resistivity (ratio of the resistance difference to the low resistance). A large capacity magnetic random access memory contains hundreds of millions of magnetic tunnel junctions, and the distribution of high and low resistance states of the junctions is a double-bell curve, as shown in figure 1. Since the junction magnetoresistance of the magnetic tunnel junction is also non-uniform, and the high resistance state of the magnetic tunnel junction has a larger standard deviation than the low resistance state, the two-clock curve is not bilaterally symmetrical with the midpoint resistance value.
The reference is optionally scaled as shown in fig. 1, corresponding to a certain fault tolerance.
The existing reading technology generally adopts a method of determining the resistance state of the magnetic tunnel junction to be measured by taking average midpoint resistance as a reference: a number of high resistance state and a number of low resistance state magnetic tunnel junctions on the same word line are averaged as a reference resistance to be compared to the sensed magnetic tunnel junction resistance.
In a typical magnetic tunnel junction array arrangement method, the physical locations of the memory cells on a word are arranged adjacently on a word line row, and the array is formed in units of words. The reference resistance is the average resistance of all magnetic tunnel junctions over a word. If a word of the magnetic random access memory is 32 bits, each reference resistance is the average resistance of 32 magnetic tunnel junctions without considering ECC. Therefore, in order to reduce the ratio of the number of reference magnetic tunnel junctions to the number of data storage cells, each reference resistance often needs to be shared by a large number of data storage cells of a word on the same word line row. If the reference tunnel junction is too far away from the cell to be tested, the resistance of the reference tunnel junction and the cell to be tested will be greatly different, which affects the accurate reading. On the other hand, in some embedded magnetic random access memory applications, because the capacity is small, there are only a few words on the same word line row, and the reference resistance layout makes the ratio of the number of reference magnetic tunnel junctions to the number of data storage units very high, which is not economical.
Disclosure of Invention
The invention provides a magnetic random access memory, aiming at the problems in the prior art, and aiming at providing a magnetic random access memory, by adopting a new layout of reference units, the same average value of i-row reference units is used when i-row memory units in an array are read, so that the number of the reference units in each array is reduced, and the problem of overhigh ratio of the number of the reference units to the number of the memory units in the small-capacity magnetic random access memory is solved.
The invention provides a magnetic random access memory, which comprises a plurality of arrays consisting of magnetoresistive memory cells, wherein a source line of each array is parallel to word lines, each array also comprises two rows of reference cells connected with two reference bit lines, each i word line corresponds to one reference word line, wherein i is a positive integer, and the reference word lines are connected with all the reference cells on the corresponding row.
Further, each magnetoresistive memory cell is connected with a MOS transistor for switching on or off the memory cell.
Furthermore, in two rows of reference cells, one row is a high-resistance state reference cell connected to the first reference bit line, and the other row is a low-resistance state reference cell connected to the second reference bit line.
Further, the average value of the high-resistance state reference units connected to the first reference bit line is used as a high-resistance state reference resistance, and the average value of the low-resistance state reference units connected to the second reference bit line is used as a low-resistance state reference resistance.
Further, the gate electrode of the MOS tube is connected to the word line of the magnetic random access memory, and the magnetic tunnel junction and the source electrode and the drain electrode of the MOS tube are connected in series between the source line and the bit line of the magnetic random access memory.
Further, memory cells of different bits of the same word are arranged in the same relative position in different arrays.
Further, the reference word line is adjacent to the corresponding i word lines.
The invention also provides a reading method of the magnetic random access memory, which comprises the following steps:
(1) the memory cells in each array corresponding to the read word are turned on by a row and column decoder;
(2) for each memory cell, the corresponding reference word line and two reference bit lines in the array are also switched on, and the i high-resistance state reference cells and the i low-resistance state reference cells connected with the corresponding reference word line are switched on;
(3) the i high-resistance state reference units and the i low-resistance state reference units input signals to a first end of the amplification comparator through a reference averaging circuit;
(4) the signal from the storage unit is input to a second end of the amplification comparator;
(5) the signals input to the first terminal and the second terminal are compared, and the state of the memory cell is determined based on the output of the amplification comparator.
Compared with the prior art, the magnetic random access memory and the reading method thereof provided by the invention have the following beneficial effects: by adopting the layout of the new reference unit, the average value of the same i-row reference units is used when the i-row memory units in the array are read, so that the number of the reference units in each array is reduced, and the problem of overhigh ratio of the number of the reference units to the number of the memory units in the small-capacity magnetic random access memory is solved.
Drawings
FIG. 1 is a schematic diagram of a selection of magnetic memory tunnel junction resistance distributions and reference resistance ranges;
FIG. 2 is a schematic layout diagram of a reference cell and a memory cell of a magnetic random access memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a magnetic tunnel junction memory cell;
fig. 4 is a schematic diagram of a comparison circuit.
Detailed Description
As shown in fig. 2, the magnetic random access memory according to one embodiment of the present invention includes a plurality of arrays of memory cells (magnetic tunnel junctions) arranged in n rows (word lines) and m columns (bit lines).
Each memory cell can store a high resistance state 1 or a low resistance state 0, and the magnetic random access memory further comprises a certain number of reference cells (magnetic tunnel junctions), wherein the resistance state is preset and is used for comparing the resistance value with the memory cell, so that the state of the memory cell is detected.
In the invention, the memory cells of different bits of the same word are arranged in the same relative position in different arrays, i.e. the memory cells of the same bit belonging to different words are arranged together to form an array. Therefore, adjacent memory cells sharing a source line on a word line cannot be read and written at the same time because the memory cells do not belong to the same word, and the problem that when different memory cells sharing the source line need to be written at the same time, some write 1 of 0, some bit line voltage are higher than the source line voltage, some bit line voltage are lower than the source line voltage, and the source line voltage is shared, so that the high bit line voltage and the low bit line voltage in the circuit need to be twice the write voltage is solved.
Each array further comprises two columns of reference units connected to two reference bit lines, wherein each i word line corresponds to one reference word line, i is a positive integer, the reference word lines are adjacent to the corresponding i word lines, and the reference word lines are located behind the i word lines and connected with all the reference units on the corresponding rows.
In the two rows of reference units, one row is a high-resistance state reference unit connected to a first reference bit line, the other row is a low-resistance state reference unit connected to a second reference bit line, and the two rows of reference units are divided into the high-resistance state reference unit and the low-resistance state reference unit for facilitating writing of the resistance state of the reference unit.
The i high-resistance state reference units and the i low-resistance state reference units are averaged and then compared with the memory unit, the resistance value is closer to the middle resistance value, i high-resistance state reference units are needed instead of one high (low) resistance state reference unit, and the problem that the state reading error of the memory unit is caused by the resistance value deviation of a single reference unit is avoided.
Specifically, in this embodiment, the mean reference value obtained by averaging the high and low reference units is directly input to one end of the amplifier and compared with the memory unit to be tested; the high and low reference cells can also be respectively averaged, for example, the average value of the high resistance state reference cells connected to the first reference bit line is used as the high resistance state reference resistance, and the average value of the low resistance state reference cells connected to the second reference bit line is used as the low resistance state reference resistance, and the average values are respectively compared with the memory cell to be tested.
Such a reference cell arrangement not only averages the resistance values of the plurality of reference cells so that the resistance value of the reference resistor is better, but also because the averaged reference cells are arranged along the bit lines, two reference bit lines are shared by the memory cells on a large number of bit lines, so that the ratio of the number of reference cells to the number of data memory cells can be very low, which is particularly advantageous for a small-capacity memory.
In order to reduce the unit area required by each memory cell, a source line 4 is parallel to a word line 3, the source line 4 and the word line 3 are perpendicular to a bit line 2 in each array, and as shown in fig. 3, each memory cell (magnetic tunnel junction MTJ)1 is connected to a MOS transistor for switching on or off the memory cell.
The gate 51 of the MOS tube is connected to the word line 3 of the magnetic random access memory, and the magnetic tunnel junction 1 and the source 53 and the drain 52 of the MOS tube are connected in series between the source line 4 and the bit line 2 of the magnetic random access memory.
The read and write operations are performed on bit lines whose potential difference from the source line determines the direction of current through the magnetic tunnel junction MTJ, with the direction of current being opposite for the write 0 and the write 1.
A plurality of arrays in the magnetic random access memory are mirror-symmetrical to each other, and the arrays are connected with a main data line and an address line to form a complete magnetic random access memory chip.
The method for reading the magnetic random access memory in the embodiment comprises the following steps:
(1) the memory cells in each array corresponding to the read word are turned on by a row and column decoder;
(2) for each memory cell, the corresponding reference word line and two reference bit lines in the array are also switched on, and the i high-resistance state reference cells and the i low-resistance state reference cells connected with the corresponding reference word line are switched on;
(3) the i high-resistance state reference units and the i low-resistance state reference units input signals to a first end of the amplification comparator through a reference averaging circuit;
(4) the signal from the storage unit is input to a second end of the amplification comparator;
(5) the signals input to the first terminal and the second terminal are compared, and as shown in fig. 4, the state of the memory cell is determined based on the output of the amplification comparator.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (6)
1. A magnetic random access memory comprises a plurality of arrays consisting of memory cells, and is characterized in that a source line of each array is parallel to word lines, each array further comprises two rows of reference cells connected to two reference bit lines, each i word line corresponds to one reference word line, wherein i is a positive integer, the reference word lines are connected with all the reference cells on the corresponding row, each memory cell is connected with an MOS (metal oxide semiconductor) tube, the MOS tubes are used for switching on or switching off the memory cells, gate electrodes of the MOS tubes are connected to the word lines of the magnetic random access memory, and a magnetic tunnel junction and source and drain electrodes of the MOS tubes are connected in series between the source line and the bit lines of the magnetic random access memory.
2. The magnetic random access memory of claim 1 wherein two columns of reference cells, one column being high resistance state reference cells connected to a first reference bit line and the other column being low resistance state reference cells connected to a second reference bit line.
3. The magnetic random access memory of claim 2 wherein the average of the high resistance state reference cells connected to the first reference bit line is used as the high resistance state reference resistance and the average of the low resistance state reference cells connected to the second reference bit line is used as the low resistance state reference resistance.
4. The magnetic random access memory of claim 1 wherein memory cells of different bits of the same word are arranged in the same relative position in different arrays.
5. The magnetic random access memory of claim 1 wherein the reference word line is adjacent to the corresponding i word lines.
6. Method for reading a magnetic random access memory according to any of claims 1 to 5, characterized in that it comprises the following steps:
(1) the memory cells in each array corresponding to the read word are turned on by a row and column decoder;
(2) for each memory cell, the corresponding reference word line and two reference bit lines in the array are also switched on, and i high-resistance state reference cells and i low-resistance state reference cells connected with the corresponding reference word line are switched on;
(3) the i high-resistance state reference units and the i low-resistance state reference units input signals to a first end of the amplification comparator through a reference averaging circuit;
(4) the signal from the storage unit is input to a second end of the amplification comparator;
(5) and comparing the signals input to the first end and the second end, and judging the state of the storage unit according to the output of the amplification comparator.
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| KR100496858B1 (en) * | 2002-08-02 | 2005-06-22 | 삼성전자주식회사 | Magnetic random access memory for flowing constant(I(H)+I(L))/2) current to reference cell without regard of bitline clamp voltage |
| KR100515053B1 (en) * | 2002-10-02 | 2005-09-14 | 삼성전자주식회사 | Magnetic memory device implementing read operation tolerant of bitline clamp voltage(VREF) |
| US8488357B2 (en) * | 2010-10-22 | 2013-07-16 | Magic Technologies, Inc. | Reference cell architectures for small memory array block activation |
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| US6191972B1 (en) * | 1999-04-30 | 2001-02-20 | Nec Corporation | Magnetic random access memory circuit |
| CN1396598A (en) * | 2001-06-06 | 2003-02-12 | 三洋电机株式会社 | Magnetic memory device |
| JP2005251273A (en) * | 2004-03-03 | 2005-09-15 | Renesas Technology Corp | Semiconductor memory |
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