CN108133725B - MRAM readout circuit using low voltage pulse - Google Patents

Abstract

The invention discloses an MRAM readout circuit using low-voltage pulses, which comprises a plurality of equivalent MOS (metal oxide semiconductor) tubes, a reference unit combination and a comparator, wherein the plurality of equivalent MOS tubes are arranged in a row and connected in parallel; the device comprises a plurality of MOS tubes, a reference unit, a comparator and a storage unit, wherein k MOS tubes in the plurality of MOS tubes are connected in parallel and then connected in series with k reference units combined with the reference unit, each other MOS tube Pax in the plurality of MOS tubes is connected in series with a read storage unit, the comparator is positioned between the two points Ax and B, and whether the storage unit is in a P state or an AP state is determined according to the voltage difference between the two points. The invention adopts low-voltage pulse to read, thus effectively reducing the reading power consumption of the MRAM reading circuit.

Description

MRAM readout circuit using low voltage pulse

Technical Field

The invention belongs to the field of semiconductor chip memories, and particularly relates to an MRAM (magnetic random Access memory) reading circuit using low-voltage pulses.

Background

Magnetic Random Access Memory (MRAM) is an emerging non-volatile memory technology. It has high read-write speed and high integration and can be written repeatedly for unlimited times. MRAM can be read and written randomly as fast as SRAM/DRAM, and can also permanently retain data after power-off as Flash memory.

MRAM has very good economy and performance, and its unit capacity occupies silicon area which is much more advantageous than SRAM, and also more advantageous than NOR Flash which is often used in such chips, and much more advantageous than embedded NOR Flash. The MRAM read-write time delay is close to the best SRAM, and the power consumption is the best in various memories and storage technologies; MRAM is compatible with standard CMOS semiconductor technology, DRAM and Flash are incompatible with standard CMOS semiconductor technology; the MRAM can also be integrated with the logic circuit in one chip.

MRAM is based on MTJ (magnetic tunnel junction) architecture. Consisting of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1: the lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a memory layer with a variable magnetization direction, which may be parallel or anti-parallel to the fixed magnetization layer. Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance.

The process of reading the MRAM is to measure the resistance of the MTJ. Writing MRAM uses a relatively new STT-MRAM technology to write through MTJs using a stronger current than reading. A bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer, and a top-down circuit places it in an anti-parallel direction.

As shown in FIG. 2, each MRAM memory cell is composed of an MTJ and an NMOS transistor. The gate electrode (gate) of the NMOS tube is connected to the Word Line of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on the Bit Line of the chip. The read and write operations are performed on Bit Line.

As shown in fig. 3, an MRAM chip is composed of one or more arrays of MRAM memory cells, each array having a number of external circuits, such as:

row address decoder: selection of changing received address to Word Line

Column address decoder: selection of changing received address to Bit Line

Read/write controller: controlling read (measure) write (add current) operations on Bit Line

Input-output control: exchange data with the outside

The read-out circuit of an MRAM needs to detect the resistance of the MRAM memory cell. Since the resistance of the MTJ may drift with temperature or the like, a common method is to use some memory cells on the chip that have been written to a high resistance state or a low resistance state as reference cells. The resistance of the memory cell and the reference cell are compared using a Sense Amplifier (Sense Amplifier).

The read process of an MRAM is the detection and comparison of the resistance of the memory cell. Whether the memory cell is in the high resistance state or the low resistance state is generally determined by combining the reference cell into a standard resistance to compare with the memory cell.

Fig. 4 is a schematic diagram of an MRAM readout circuit in the prior art, where P1, P2, and P3 shown in fig. 4 are the same PMOS transistors, forming a current mirror, and the current of each path above is equal (I _ read). The difference in resistance causes a difference between V _ out and V _ out _ n, which is input to the comparator of the next stage to generate an output. The example in fig. 4 is a path of memory cells, comparing a path of reference cells in P state with a path of reference cells in AP state. In actual use, multiple memory cells can be compared with m AP and n P reference cells.

One problem with the prior art MRAM read-out circuit shown in fig. 4 is that it consumes a lot of power. When the resistance of the memory cell is measured, direct current is inevitably supplied, and the power consumption of the read-out circuit accounts for most of the read power consumption of the MRAM. A certain I _ read is required to generate a certain signal strength in the circuit, and the read power consumption of the circuit is proportional to V _ DD I _ read. In practice, the voltage across the memory cell is only 150-200mV, and V _ DD is typically 1.2V, so that in MRAM using this sensing circuit, most of the power is not dissipated across the memory cell, but rather across the sensing circuit.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an MRAM readout circuit using a low voltage pulse, which can effectively reduce the read power consumption of the MRAM readout circuit.

In order to achieve the above object, the present invention provides an MRAM readout circuit using low voltage pulses, comprising a plurality of identical MOS transistors arranged in parallel in a row, a reference cell combination, a comparator, and a switch control circuit.

The reference unit combination is formed by connecting k reference units in parallel, wherein a part of the k reference units are configured to be in a P state, and the rest reference units are configured to be in an AP state;

k MOS tubes Pb1 and Pb2 … Pbk in the plurality of identical MOS tubes are connected in parallel and then connected in series with the k reference units, and the series connection point is B;

each of the other MOS transistors Pax (x ═ 1, 2, …) of the plurality of identical MOS transistors is connected in series with a read memory cell x (x ═ 1, 2, …), and the series connection point is Ax (x ═ 1, 2, …);

the comparators are arranged between two points of the series connection point Ax and the series connection point B, whether the read storage unit x is in a P state or an AP state is determined by the voltage difference between the two points, and the number of the comparators is determined by the number of the read storage units;

the read storage unit is connected with a reference voltage V _ B at one end of the source line side of all the read storage units, the bit line sides of the read storage units 1, 2 and … x are respectively connected with series connection points A1, A2 and … Ax, the reference unit combination is divided into a first end and a second end, the first end of the reference unit combination is connected with the series connection point B, and the second end of the reference unit combination is connected with the reference voltage V _ B;

the switch control circuit is used for controlling the on-off of the plurality of identical MOS tubes;

the switch control circuit switches on a plurality of equivalent MOS tube grid voltages to a specified voltage standard, and adds a voltage V _ read to form a voltage V _ read + V _ b on the basis of the reference voltage V _ b, the plurality of equivalent MOS tubes are divided into a first end and a second end, the first ends of the plurality of equivalent MOS tubes are connected with the voltage V _ read + V _ b, the second ends of the plurality of equivalent MOS tubes are connected with series connection points B, A1, A2 and … Ax, and the plurality of equivalent MOS tubes are switched on and are equivalent to a resistor.

Furthermore, the value of the voltage V _ read is-400 mV.

In the conventional circuit, the MOS transistor which is used as the current mirror must work in a saturation state. This means that they have a higher V _ DS and consume much power. The MOS tube works in an online state, an MRAM (magnetic random access memory) reading circuit with low voltage pulse (<400mV) can be used for reading operation by adopting the low voltage pulse, the reading power consumption of each path is V _ read I _ read, the reading power consumption of the traditional technology is V _ DD I _ read, and the I _ read in the two circuits is close, so that the power consumption of the circuit provided by the invention is only about 30 percent or even lower than that of the traditional circuit.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ.

FIG. 2 is a schematic diagram of a prior art MRAM memory cell architecture.

Fig. 3 is a prior art MRAM chip architecture diagram.

Fig. 4 is a schematic diagram of a prior art MRAM read circuit.

FIG. 5 is a schematic diagram of an MRAM read circuit using low voltage pulses in accordance with a preferred embodiment of the invention.

Detailed Description

The following detailed description of the preferred embodiments of the present invention is provided to enable those skilled in the art to more readily understand the advantages and features of the present invention, and to clearly and unequivocally define the scope of the present invention.

As shown in fig. 5, an MRAM readout circuit using low voltage pulses includes a plurality of identical MOS transistors arranged in a row, a reference cell combination, and a comparator.

A plurality of MOS transistors, which are identical and arranged in a row, are connected in parallel and divided into two groups, the first group being Pb1 and Pb2 … Pbk, and the second group being Pax (x ═ 1, 2, …).

The reference cell combination is formed by connecting k reference cells in parallel, wherein a part of the k reference cells are configured to be in a P state, the rest of the k reference cells are configured to be in an AP state, and the reference cells are divided into a plurality of columns and are arranged in an MRAM memory cell array.

The first group of MOS transistors Pb1 and Pb2 … Pbk are connected in parallel and then are connected in series with k parallel reference units, and the series connection point is B.

Each of the second group of MOS transistors Pax (x ═ 1, 2, …) is connected in series with one read memory cell x (x ═ 1, 2, …), and the series connection point is Ax (x ═ 1, 2, …).

The number of comparators is determined by the number of read memory cells, and one comparator is connected between each Ax and B.

And the switch control circuit is used for controlling the on-off of a plurality of identical MOS tubes. When reading, the gate voltage of the MOS tube is switched on to a specified voltage standard. When the reading operation is not carried out, the MOS tubes can be switched off.

One end of the reference cell combination and the read storage unit, which is positioned at the Source Line (Source Line) side of all the read storage units, is connected with a reference voltage V _ B, V _ B is added to the Source Line (Source Line) of all the read storage units shown in FIG. 2, and Ax (x is 1, 2, …) and B points are connected to Bit lines corresponding to all the read storage units. When reading, one end of the MOS tubes is added with a voltage V _ read, and the MOS tubes are switched on at the moment and play the role of a resistor. The value of V _ read is-250 mV.

When the MRAM chip reads, the read row is selected through Word Line, and the column address decoder opens the read column, as shown in FIG. 3. Multiple read memory cells may operate in parallel.

The MOS transistors disclosed in the above embodiments operate in a linear state, and an MRAM readout circuit using low voltage pulses can perform a read operation using low voltage pulses, where the read power consumption of each path is V _ read × I _ read, whereas the read power consumption of the conventional technology is V _ DD × I _ read, and I _ read in the two circuits are close to each other, so that the power consumption of the circuit provided by the present invention is only about 30% or even lower than that of the conventional circuit.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims (1)

1. An MRAM read circuit using low voltage pulses, comprising a plurality of identical MOS transistors arranged in parallel in a row, a reference cell combination, a comparator and a switch control circuit,

the reference unit combination is formed by connecting k reference units in parallel, wherein a part of the k reference units are configured to be in a P state, and the rest reference units are configured to be in an AP state;

k MOS tubes Pb1, Pb2 and … Pbk in the multiple equivalent MOS tubes are connected in parallel and then connected in series with the k reference units, and the series connection point is B;

the other MOS tubes Pa1, Pa2 and.. Pax in the plurality of identical MOS tubes are respectively connected with the read storage units 1, 2 and … x in series, and the series connection points are respectively A1, A2 and … Ax;

the comparators are arranged between two points of the series connection point Ax and the series connection point B, whether the read storage unit x is in a P state or an AP state is determined by the voltage difference between the two points, and the number of the comparators is determined by the number of the read storage units;

the read storage unit is connected with a reference voltage V _ B at one end of the source line side of all the read storage units, the bit line sides of the read storage units 1, 2 and … x are respectively connected with series connection points A1, A2 and … Ax, the reference unit combination is divided into a first end and a second end, the first end of the reference unit combination is connected with the series connection point B, and the second end of the reference unit combination is connected with the reference voltage V _ B;

the switch control circuit is used for controlling the on-off of the plurality of identical MOS tubes;

during reading operation, the switch control circuit switches on a plurality of equivalent MOS tube gate voltages to a specified voltage standard, and adds a voltage V _ read to form a voltage V _ read + V _ b on the basis of the reference voltage V _ b, the plurality of equivalent MOS tubes are divided into a first end and a second end, the first ends of the plurality of equivalent MOS tubes are connected with the voltage V _ read + V _ b, the second ends of the plurality of equivalent MOS tubes are respectively connected with series connection points B, A1, A2 and … Ax, and the plurality of equivalent MOS tubes are switched on;

the voltage V _ read takes a value of-400 mV to 400mV, so that the plurality of equivalent MOS tubes work in a linear state.

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