CN111383691A

CN111383691A - MRAM memory device with writing state detection unit

Info

Publication number: CN111383691A
Application number: CN201811624645.7A
Authority: CN
Inventors: 戴瑾; 郭一民
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-12-28
Filing date: 2018-12-28
Publication date: 2020-07-07

Abstract

An MRAM memory device having a write state detection unit includes an MRAM memory cell including at least first and second magnetic tunnel junctions, one of which has a normal order of a reference and a memory layer with respect to a read and write current path, and the other of which has a reverse order of the reference and memory layers with respect to the read and write current path; one ends of the first magnetic tunnel junction and the second magnetic tunnel junction are respectively connected with the first bit line and the second bit line, and the other ends of the first magnetic tunnel junction and the second magnetic tunnel junction are connected with the MOS tube; the writing state detection unit comprises a detection point and a comparator, and is suitable for detecting the state transition of the MRAM storage unit and terminating the writing operation in advance according to the detection result.

Description

MRAM memory device with writing state detection unit

Technical Field

The invention relates to the field of semiconductor chips, which is most importantly applied to the fields of Internet of things, wearable electronic equipment and the like with strict requirements on standby power consumption, in particular to an MRAM storage device with a writing state detection unit.

Background

The background of the present invention is that the MRAM manufacturing technology has matured, and in recent years, people use the magnetoresistance effect of Magnetic Tunnel Junction (MTJ) to make a Magnetic random Access memory, namely MRAM (Magnetic random Access memory), which is a nonvolatile Magnetic random Access memory, and compared with the existing memories, the MRAM has the advantages that (1) it has the high-speed reading and writing capability of Static Random Access Memory (SRAM), and the high integration degree of Dynamic Random Access Memory (DRAM), and can permanently retain data after power failure like Flash memory. (2) Its performance is quite good, the read-write time delay is close to SRAM, and the power consumption is much lower than that of flash memory. (3) The method has good economy, occupies small silicon chip area per unit volume, and has great advantages compared with SRAM; the number of additional photomasks required in the manufacturing process is small, and the cost advantage is larger than that of the embedded NOR Flash. (4) MRAM is not compatible with standard CMOS semiconductor processes, as is DRAM and Flash, and can be integrated with logic circuitry in one chip.

At present, the MRAM technology of each factory close to mass production has the disadvantages that although the read-write power consumption is much lower than that of a flash memory, the write-in power consumption is still larger, the write current is higher, and the MRAM technology is not ideal if replacing a DRAM or an SRAM. In particular, with current writing techniques, the waste of energy is very large:

1. if a bit of 1 is required, the probability that the bit is half of a 1 is already present, and no more energy is required. However, the write circuit cannot know the previous state of the bit, so whether the previous state is a 1 or a 0, it is common practice to do a write operation once. In a statistical sense, half of the energy is thus wasted.

2. The write operation is to apply an electrical pulse to a bit, which pulse must be maintained at a specific length to control the error rate within an acceptable range. For example, for a 1 megabit array in practice, the length of the write pulse may take 30 nanoseconds to control the error rate to within one millionth, but in practice, over 90% of the bits have completed the write operation in 10 nanoseconds. But randomly, there may be one millionth of bits that take 30 nanoseconds to complete a write operation, and the write circuit does not know the write time required for each bit, but only extends the pulse time to the most conservative case. Thus, 2/3 is wasteful of even more energy for most bits that need to be written.

In order to reduce the waste of writing energy, the industry has started studying a writing state detection circuit capable of detecting the state of a bit being written while a writing operation is being performed, and terminating the writing operation immediately upon detecting that the state of the bit has reached a target value. Such a write state detection circuit can significantly reduce write power consumption. US patent US20180061466 proposes the following techniques:

1. a write state detection circuit is added to the MRAM to terminate the write operation early when it is detected that the written bit has reached the target state.

2. A reference cell is required having a reference resistance.

3. The write detection circuit compares the resistance of the cell being written to with the reference resistance to determine its current state.

4. The specific implementation method is to apply the same voltage of the written unit to the reference unit and compare the potential of the same point on the writing circuit. The different resistances of the written cells inevitably lead to different circuit voltage division, resulting in the change of the potential at the detected point.

The write state detection circuit of the U.S. patent is directed to the most basic MRAM memory cell, i.e., the MRAM cell composed of 1 MTJ and 1 MOS transistor (hereinafter referred to as the MRAM memory cell of 1T1M), and how to perform write state detection on the MRAM cell having 2 MTJs connected to 2 MOS transistors (hereinafter referred to as the MRAM memory cell of 2T2M) is still an unsolved problem.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention proposes to use one of the reverse connection structures of 2T2M, and perform the write status detection based on this structure, so as to solve the problem of write status detection, and thus, the present invention is a fast and power-saving design.

An MRAM memory device with a write state detection unit comprises a plurality of MRAM memory units, and is characterized by further comprising a write state detection unit;

the MRAM memory cell includes at least a first magnetic tunnel junction and a second magnetic tunnel junction, one of the first and second magnetic tunnel junctions having a normal order of the reference and memory layers with respect to a read and write current path, and the other magnetic tunnel junction having a reverse order of the reference and memory layers with respect to the read and write current path, and a MOS transistor coupled to the first and second magnetic tunnel junctions; one ends of the first magnetic tunnel junction and the second magnetic tunnel junction are respectively connected with the first bit line and the second bit line, and the other ends of the first magnetic tunnel junction and the second magnetic tunnel junction are connected with the MOS tube; the other two ends of the MOS tube are respectively connected with a word line and a source line;

the writing state detection unit is adapted to detect a state transition of the MRAM memory cell and terminate the writing operation in advance according to a detection result.

Further, when writing the state, two bit lines connected with the first and second magnetic tunnel junctions in the MRAM memory cell and a source line connected with the MOS tube are electrified in the same direction.

Further, the number of the MOS tubes in the MRAM memory unit is two.

In one embodiment of the invention, the number of the MOS tubes in the MRAM memory cell is two.

Further, the number of the MOS tubes in the MRAM memory unit is one.

In another embodiment of the present invention, there is one MOS transistor in the MRAM memory cell.

Further, one of the two magnetic tunnel junctions is routed to the upper layer through a via hole by adding a via hole, and then the magnetic tunnel junction is laid down.

Further, the writing state detection unit includes a detection point and a comparator.

Furthermore, the detecting points are arranged at the same positions of the two bit lines of the peripheral region corresponding to the MRAM memory cell.

Furthermore, the detecting points are arranged at the same positions of the two source lines of the peripheral region corresponding to the MRAM memory cells.

In an embodiment of the invention, the detecting points may be disposed on two bit lines or two source lines of the peripheral region corresponding to the MRAM memory cell.

In another embodiment of the present invention, the detecting points can be disposed on only two bit lines of the peripheral region corresponding to the MRAM memory cell.

Further, the comparator sets a threshold value for comparing a difference between a detection point potential difference and the threshold value at the time of a write operation

The technical effects are as follows:

1. the invention adds a write state detection circuit on the basis of the reverse connection of 2T2M, and the write state power consumption of the MRAM memory device is greatly reduced.

2. On the basis of the reverse connection design of 2T2M, a 1T2M structure is provided, namely 2 MOS transistors in the MRAM memory unit are combined into 1 MOS transistor, so that the layout space can be greatly saved.

The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.

Drawings

FIG. 1 is a schematic diagram of a prior art MTJ low resistance state;

FIG. 2 is a schematic diagram of a prior art MTJ high resistance state;

FIG. 3 is a prior art MRAM chip architecture diagram;

FIG. 4 is a schematic diagram of a prior art MRAM memory cell (1T 1M);

FIG. 5 is a cross-sectional view of a prior art 3 MRAM memory cell structure;

FIG. 6 is a schematic diagram of a prior art MRAM memory cell (2T 2M);

FIG. 7 is a system block diagram of an MRAM memory device according to an embodiment of the invention;

FIG. 8 is a schematic diagram of an MRAM memory cell (1T2M inverted) according to another embodiment of the invention;

FIG. 9 is a diagram of a MOS transistor structure in an MRAM memory cell (1T2M flipped) of the present invention;

fig. 10 is a system block diagram of an MRAM memory device in accordance with another embodiment of the present invention.

The reference numbers illustrate:

1. a memory layer; 2. a tunnel barrier layer; 3. a reference layer.

Detailed Description

In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. The drawings are schematic diagrams or conceptual diagrams, and the relationship between the thickness and the width of each part, the proportional relationship between the parts and the like are not completely consistent with actual values.

MTJ (magnetic tunnel junction) is a sandwich structure consisting of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material. Fig. 1 shows a MTJ structure in which the lower layer of ferromagnetic material is a reference layer 3 having a fixed magnetization direction, and the upper layer of ferromagnetic material is a memory layer 1 having a variable magnetization direction, which may be parallel or antiparallel to the reference layer 3. Due to quantum physical effects, current can pass through the middle tunnel barrier 2, but the resistance of the MTJ is related to the magnetization direction of the changeable magnetization layer, with the MTJ in the low resistance state RL when the magnetization direction of the memory layer 1 is parallel to the magnetization direction of the reference layer 3 and in the high resistance state RH when the magnetization direction of the memory layer 1 is anti-parallel to the magnetization direction of the reference layer 3.

The procedure for reading MRAM is to measure the resistance of MTJ, and using the newer STT-MRAM (spin torque transfer memory) technology, writing MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. Based on the MTJ structure of FIG. 1, a bottom-up current places the variable magnetization layer in a direction parallel to the fixed layer and a top-down current places the variable magnetization layer in a direction anti-parallel to the fixed layer, as shown in FIG. 2.

As shown in fig. 3, an MRAM chip is composed of one or more arrays of MRAM memory cells, each array having a number of external circuits, such as:

row address decoder: changing the received address to a selection of a Word Line (Word Line);

column address decoder: changing the received address to a selection of Bit lines (Bit lines);

read/write controller: controlling a read (measure) write (add current) operation on the Bit Line;

● input-output control: and exchange data externally.

As shown in fig. 4, an MRAM memory cell generally consists of an MTJ and a MOS transistor, i.e., adopts a structure of 1T 1M. In this structure, the Gate of the MOS transistor is connected to the word line of the chip to turn on or off the unit, and the MTJ and MOS transistor are connected in series to the bit line of the chip. The read and write operations are performed on bit lines.

Fig. 5 shows a perspective cross-sectional view of 3 MRAM memory cells, the MOS transistor, typically an NMOS transistor, fabricated by a standard etching process, with the MTJ connected to the drain by a via.

The read circuit of the MRAM needs to detect the resistance of the MRAM memory cell. Since the resistance of the MTJ may drift with temperature or the like, a common method is to use some memory cells on the chip that have been written to a high resistance state or a low resistance state as reference cells. The resistance of the memory cell and the reference cell are compared using a Sense Amplifier (Sense Amplifier).

Fig. 6 shows another MRAM memory cell structure, in which each MRAM memory cell includes two MTJs and two MOS transistors, i.e., a 2T2M structure is adopted. In each memory cell the two MTJs are placed one in the P (reference layer parallel to the magnetization direction of the memory layer) state and the other in the AP (reference layer antiparallel to the magnetization direction of the memory layer) state, with two different arrangements storing the '0' state and '1' state, respectively. In such a memory cell, no reference cell is required. In a read operation, only the resistance values of the two MTJs need to be compared. The two MTJs are usually located adjacent to each other, the process non-uniformity causes very small variation, and the resistance difference is very large when one MTJ is in the P state and the other MTJ is in the AP state. Because the signal is strong, the reading speed is fast and the reliability is high. Therefore, although the area and cost are not dominant, the method is still an attractive option.

However, in this structure, there is a particular difficulty in detecting the write state, and since the two MTJs must be in opposite states, the two MTJs always pass opposite currents during the write operation, and in this situation, the equivalent resistances of the two MOS transistors are greatly different. However, the current around the memory device can only sense the resistance sum of the memory cells of the MOS transistor, and in this case, it is very difficult to determine the write state.

The present invention proposes to use a variant based on the 2T2M structure: one of the MTJs is reversely connected, so that although the states of the two MTJs are always opposite, the two MOS transistors pass current in the same direction during writing, fig. 7 is a system block diagram of a preferred embodiment of the present invention, actually, the MRAM memory device includes an MRAM array composed of a plurality of magnetic memory cells and a writing state detection unit in a peripheral region, and since the writing modes for each row of memory cells in the array are similar, the descriptions of a row encoder and row address selection are omitted in this embodiment (the same as the word line selection mode of the existing memory, and no further description is given). For convenience of description, the structure of an MRAM memory cell and a write state detection circuit is shown in the example in the figure, and in fig. 7, one MRAM memory cell, i.e., one bit, is composed of two MTJs and two MOS transistors and is connected by the same word line. One end of each MTJ is respectively connected with a first bit line and a second bit line, the read-write operation is carried out on the bit lines, and the first bit line and the second bit line apply the same-direction write voltage V _ write during the write operation; of course, V _ write may be applied to the first source line and the second source line according to different settings, and in this embodiment, V _ write is applied to the bit line only. The other ends of the two MTJs are respectively connected with two MOS tubes, the other ends of the two MOS tubes are respectively connected with a first source line and a second source line, and the switch of each MOS tube is controlled by a word line connection. It should be noted that the first bit line, the second bit line, the first source line, and the second source line are respectively connected to a first common bit line, a second common bit line, a first common source line, and a second common source line in the peripheral region of the MRAM memory device. The memory layer and the reference layer of the two MTJ elements are arranged in reverse order to each other. Meanwhile, a write state detection circuit is disposed in a peripheral region of the memory device, the detection circuit includes a detection point and a comparator, in this embodiment, the detection point is disposed on the first common bit line and the second common bit line, and of course, the detection point may also be disposed on the first common source line and the second common source line, which is not described herein again. The other end of the detection point is connected with a comparator, the comparator sets a threshold value, the potential difference detected by the two detection points during the writing operation is compared with the set threshold value, whether the writing operation is finished or not is judged according to the output result of the comparator, and when the writing operation is judged to be finished, the writing operation is terminated in advance.

In this embodiment, the specific write operation is as follows:

1. the write driver is a set of switches connected to a common source line and a common bit line, and receives a write voltage V _ write or ground as required for writing 0 and 1.

2. During writing operation, the row decoder selects to open one row, and the MOS tube of the MRAM memory unit on the corresponding word line of the row is opened.

3. The column decoder selects one column among several columns, two source lines such as a first source line and a second source line and two bit lines such as a first bit line and a second bit line are connected, and V _ write is applied to the first bit line and the second bit line.

4. Detection points are arranged at the same positions of the first common bit line and the second common bit line in the peripheral area of the MRAM magnetic memory device, of course, the detection points can also be arranged at the same positions of the first common source line and the second common source line, and different currents are caused by different resistances due to certain internal resistance of a writing driver, so that different voltage drops are generated.

5. A comparator connected to the other end of the detecting point sets a threshold value, compares the potential difference detected at the detecting point with the threshold value, and terminates the writing operation in advance when it is determined that the writing operation has been completed.

In the present embodiment, an MRAM memory device having a write state detection unit reversely connected to 2T2M is proposed, and the detection unit does not need to additionally provide a reference resistor, and by comparing the potential difference between the two bit lines with the threshold value set by the comparator, the write operation can be terminated early, so that the write state power consumption of the MRAM memory device can be greatly reduced.

Fig. 8 shows another MRAM memory cell structure proposed in the present invention, i.e., a 1T2M flip-flop structure, in which each MRAM memory cell, i.e., one bit, includes 2 MTJs and 1 MOS transistor, memory layers and reference layers of two MTJ elements are arranged in reverse order to each other, and voltages are applied to a first bit line, a second bit line, and a source line in the same direction.

Fig. 9 illustrates a method of achieving the structural connection illustrated in fig. 8, and fig. 9 shows a schematic cross-sectional view of 3 MRAM memory cells, where all source and bit lines are perpendicular to the page and the word lines are parallel to the page but not in cross-section. One implementation of the MTJ with the opposite connection is to add a via, and to pass one of the MTJ traces to the upper layer and then go down.

FIG. 10 is another embodiment of an MRAM memory device based on the MRAM memory cell structure shown in FIG. 8, in which one end of each of the two MTJs of each MRAM memory cell is connected to a first bit line and a second bit line, respectively, a read/write operation is performed on the bit lines, and a write operation is performed by applying a write voltage V _ write in the same direction to the first bit line and the second bit line; of course, V _ write can be applied to the first source line according to different settings, and in this embodiment, V _ write is applied to the bit line only. The other ends of the two MTJs are connected with the same MOS tube, the other end of the MOS tube is connected with a first source line, and the switch of the MOS tube is controlled by word line connection. It should be noted that the first bit line, the second bit line, and the first source line are connected to a first common bit line, a second common bit line, and a first common source line, respectively, in the peripheral region of the MRAM memory device. The memory layer and the reference layer of the two MTJ elements are arranged in reverse order to each other. And a write state detection circuit including a detection point and a comparator is provided in a peripheral region of the memory device, the detection point being provided only on the first common bit line and the second common bit line in this embodiment. The other end of the detection point is connected with a comparator, the comparator sets a threshold value, the potential difference detected by the two detection points during the writing operation is compared with the set threshold value, whether the writing operation is finished or not is judged according to the output result of the comparator, and when the writing operation is judged to be finished, the writing operation is interrupted in advance.

In this embodiment, the specific write operation is as follows:

1. the write driver is a set of switches that are switched in to the write voltage V _ write or ground as required for writing a 0 and writing a 1. 2. During writing operation, the row decoder selects to open one row, and the MOS tube of the MRAM memory unit on the corresponding word line of the row is opened.

3. A column decoder selects a column among columns, and a source line such as a first source line and two bit lines such as a first bit line and a second bit line are connected while V _ write is applied to the first bit line and the second bit line.

4. The detection points are arranged at the same positions on the first common bit line and the second common bit line in the peripheral area of the MRAM magnetic memory device, and different currents are caused by different resistances due to certain internal resistance of a writing driver, so that different voltage drops are generated.

5. And a comparator connected with the other end of the detection point sets a threshold value, compares the potential difference detected by the detection point with the threshold value, and selects to interrupt the writing operation in advance or continue the writing operation according to the comparison result.

In this embodiment, a write state detection circuit is added to the previous 2T2M design, and no additional reference resistor is needed, and by comparing the potential difference between the two bit lines with the threshold set by the comparator, the write operation can be terminated early, so that the write state power consumption of the MRAM memory device can be greatly reduced. In addition, on the basis of the reverse connection design of 2T2M, the present embodiment proposes a 1T2M structure, that is, 2 MOS transistors in the MRAM memory cell are combined into 1 MOS transistor, which can greatly save the layout space.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. An MRAM memory device having a write state detection unit, comprising a plurality of MRAM memory cells, characterized in that: the device also comprises a writing state detection unit;

the MRAM memory cell comprises at least a first magnetic tunnel junction and a second magnetic tunnel junction, one of which has a normal order of reference and memory layers with respect to current paths for reading and writing, and the other of which has a reverse order of reference and memory layers with respect to current paths for reading and writing, and a MOS transistor coupled to the first and second magnetic tunnel junctions; one ends of the first magnetic tunnel junction and the second magnetic tunnel junction are respectively connected with the first bit line and the second bit line, and the other ends of the first magnetic tunnel junction and the second magnetic tunnel junction are connected with the MOS tube; the other two ends of the MOS tube are respectively connected with a word line and a source line;

the write state detection unit is adapted to detect a state transition of the MRAM memory cell.

2. The MRAM memory device having a write state detection unit according to claim 1, wherein two bit lines connected to the first and second tunnel junctions in the MRAM memory cell and a source line connected to the MOS transistor are energized in the same direction when writing the state.

3. The MRAM memory device having a write state detection unit according to claim 1, wherein there are two MOS transistors in the MRAM memory cell.

4. The MRAM memory device having a write state detection unit according to claim 1, wherein the MRAM memory cell has one MOS transistor.

5. The MRAM memory device with a write state detection unit according to claim 1, wherein one of the two magnetic tunnel junctions is routed through a via to an upper layer and then down by adding a via.

6. The MRAM memory device having a write state detection unit according to claim 1, wherein the write state detection unit includes a detection point, a comparator.

7. The MRAM memory device having a write state detection unit according to claim 6, wherein the detection points are provided at the same positions on both bit lines of the peripheral region corresponding to the MRAM memory cell.

8. The MRAM memory device having a write state detection unit according to claim 6, wherein the detection points are provided at the same positions of the two source lines in the peripheral region corresponding to the MRAM memory cell.

9. The MRAM memory device having a write state detection unit according to claim 6, wherein the comparator sets a threshold value for comparing a difference between the detected point potential difference and the threshold value at the time of the write operation.