CN110136760A

CN110136760A - MRAM chip

Info

Publication number: CN110136760A
Application number: CN201810130958.0A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-02-09
Filing date: 2018-02-09
Publication date: 2019-08-16
Anticipated expiration: 2038-02-09
Also published as: CN110136760B

Abstract

The invention discloses a kind of MRAM chips, wherein MRAM array includes multiple subarrays, and the subarray includes that a common source line is connected to all units, and the multiple bit lines of each column of connection；Each bit line connects the first transmission gate, the second transmission gate；First transmission gate connects the common source line, and second transmission gate connects common bit lines；The pre decoder includes: more address wire inputs and the selection signal of the bit line quantity Matching and its output of inversion signal；The selection signal and its inversion signal output end are connected to the first transmission gate corresponding to the corresponding bit line of each subarray, the second transmission gate, control first transmission gate, any opening of the second transmission gate, another closing.By the control of pre decoder, so that an array only writes a bit every time, it is no longer necessary to which high voltage, negative voltage, designing simple energy consumption reduces.

Description

MRAM chip

Technical field

The present invention relates to a kind of semiconductor chip more particularly to a kind of MRAM chips.

Background technique

MRAM is a kind of new memory and memory technology, can as SRAM/DRAM quick random read-write, can also picture The same reservation data permanent after a loss of power of Flash flash memory.

It is local good that its economy is thought, the silicon area ratio SRAM that unit capacity occupies has very big advantage, than such The NOR Flash being commonly used in chip is also advantageous, bigger than the advantage of embedded NOR Flash.Its performance is also suitable It is good, time delay is read and write close to best SRAM, and power consumption is then best in various memories and memory technology.And MRAM unlike DRAM and Flash is incompatible with standard CMOS semiconductor technique like that.MRAM can be integrated into a chip with logic circuit.

The principle of MRAM is the structure for being called MTJ (magnetic tunnel junction) based on one.It is pressed from both sides by two layers of ferrimagnet One layer very thin non-ferric magnetic dielectric composition.One layer of following ferromagnetic material is the reference with fixed magnetisation direction Layer, ferromagnetic material above is the memory layer of changeable magnetization direction, its direction of magnetization can it is parallel with fixed magnetization layer or It is antiparallel.Due to the effect of quantum physics, electric current can pass through intermediate tunnel barrier layer, but the resistance of MTJ and variable magnetic The direction of magnetization for changing layer is related.The previous case resistance is low, and latter situation resistance is high.The process for reading MRAM is exactly to MTJ Resistance measure.Using newer STT-MRAM technology, it is also fairly simple to write MRAM: being worn using than reading stronger electric current It crosses MTJ and carries out write operation.One electric current from bottom to top variable magnetization stratification at the direction parallel with fixing layer, from top to bottom Circuit it is set to antiparallel direction.

The memory unit of each MRAM is made of MTJ and metal-oxide-semiconductor.The gate of metal-oxide-semiconductor is connected to chip Word Line is responsible for switching on or off this unit, and MTJ and metal-oxide-semiconductor are serially connected on the Bit Line of chip.Read-write operation exists It is carried out on Bit Line.

One MRAM chip is made of the array of one or more mram memory cells, and each array has several external electricals Road, such as: row-address decoder: the address received being become the selection of Word Line；Column address decoder: the address received Become the selection of Bit Line；Read-write controller: operation is write and (adds electric current) in the reading (measurement) on control Bit Line；Input and output Control: and external exchange data.

Currently, the layout vertical using BL and SL is conducive to reduce chip area shared by each storage unit, reduce at This.Operation is slightly complicated when write-in: the current potential of a wordline being drawn high and opens this line, and the source electrode line of this line is placed in one Intermediate potential.Then the demand that 0 or 1 is written according to each unit, increases on bit line or low potential respectively.Low potential has It may be negative voltage.

Although BL and SL vertical placement scheme can reduce cost, there is following two problem:

1, because requiring have a fixed voltage drop, high potential required for this method in storage unit when being written It is twice of BL and SL parallel scheme with the voltage difference of low potential.Chip requires the high voltage that cannot be provided using outside, or Negative voltage.Portion's design circuit generates different voltage including both of these case requires, and voltage transfer zone carrys out the drop of power consumption efficiency Low and additional cost.

2, when being written, electric current required for entire a line is all flowed into from same root Bit Line.In the design usually by Difficulty is not enough brought in SL source line widths.

Summary of the invention

In view of the above drawbacks of the prior art, technical problem to be solved by the invention is to provide a kind of MRAM chip, It include: the MRAM array and pre decoder of source line Yu bit line vertical arrangement, wherein the MRAM array includes multiple subarrays, The subarray includes that a common source line is connected to all units, and the multiple bit lines of each column of connection；Each bit line connects Connect the first transmission gate, the second transmission gate；First transmission gate connects the common source line, and the second transmission gate connection is public Bit line；The pre decoder includes: more address wire inputs, selection signals and its inversion signal with the bit line quantity Matching Output；The selection signal and its inversion signal output end are connected to first corresponding to the corresponding bit line of each subarray Transmission gate, the second transmission gate control first transmission gate, any opening of the second transmission gate, another closing.

Preferably, the subarray further include: reference unit column, the pre decoder have a reference input, ginseng The reference bit lines for examining cell columns are separately connected the common source line, the reference input by two third transmission gates.

Preferably, the common bit lines, the common source line connect read-write cell.

Preferably, the pre decoder chooses a bit line, then with the matched selection signal of the bit line and other described choosings The signal for selecting signal output is opposite.

The present invention efficiently solves the problems, such as that at high cost, manufacture is difficult, passes through the control of pre decoder compared to the prior art System, so that an array only writes a bit every time, solves the problems, such as source electrode line electricity shortage, to no longer need high electricity Pressure, negative voltage, designing simple energy consumption reduces.And shared sense amplifier, effectively reduce cost.

It is described further below with reference to technical effect of the attached drawing to design of the invention, specific structure and generation, with It is fully understood from the purpose of the present invention, feature and effect.

Detailed description of the invention

Fig. 1 is the circuit diagram of precoder of the invention；

Fig. 2 is predecoder circuits figure of the invention；

Fig. 3 is the circuit diagram of the first transmission gate of the invention, the second transmission gate.

Specific embodiment

As shown, Fig. 1 is the circuit diagram of precoder of the invention, Fig. 2 is predecoder circuits figure of the invention, one Kind MRAM chip, comprising: the MRAM array and pre decoder 3 of source line 2 and 1 vertical arrangement of bit line, the source line 2 (SL) of MRAM array With bit line 1 (BL) vertical arrangement, a common bit lines 7 connect multiple bit lines 1, wherein MRAM array includes multiple subarrays, submatrix Column include that a common source line 8 is connected to all units, and common source line 8 connects the multiple bit lines 1 of each column, can specifically use Every n column become one group, and subarray includes that a common source line 8 connects more root lines 2, and the SL of each group of all rows is passed through one Public SL links together；Each bit line 1 connects the first transmission gate, the second transmission gate；First transmission gate connects common source line 8, the second transmission gate connects common bit lines 7；Each subarray connects a pre decoder 3, pre decoder 3 (Y Predecoder) packet Include: more address wire inputs 31 (input k root address wire) export with the selection signal of 1 quantity Matching of bit line and inversion signal；Choosing It selects signal and its inversion signal output end is connected to the first transmission gate, second corresponding to the corresponding bit line 1 of each subarray Transmission gate controls the first transmission gate, any opening of the second transmission gate, another closing.

Fig. 3 is the circuit diagram of the first transmission gate of the invention, the second transmission gate, further, selection signal 4 (YDEP), Inversion signal output end 5 (YDEN), two signals are on the contrary, for selected column x, YDEPx and others YDEP<n-1,0>phase Instead；First transmission gate includes: the first PMOS12 in parallel with the first NMOS11, and selection signal 4 controls the first PMOS12 and switchs, and second Defeated output end controls the first NMOS11 switch；Second transmission gate includes: the 2nd PMOS22, the 2nd NMOS21, inversion signal output 5 control the 2nd PMOS22 switch of end, selection signal 4 control the 2nd NMOS21 switch.

Specifically, in specific implementation process of the invention: for BL<n-1 of each column, 0>, configure two transmission gates. One transmission gate connects it with public SL, another it connected with public BL.Theirs are controlled by YDEP and YDEN signal Switch, the sequence of two transmission gates YDEP, YDEN connection is on the contrary, so one is opened one and is bound to shut.For selected Row x, Y-Predecoder opens the connection of BLx and public BL.For other rows, the connection of BLx and public SL are opened.

Further, subarray further include: reference unit column, pre decoder 3 have a reference input, reference unit The reference bit lines 1 of column are separately connected common source line 8, reference input by two third transmission gates.

Specifically, in this case, Y-Predecoder increases a read-write control signal input.Two biographies of reference columns Its BL is connected to public SL by one, defeated door, another is connected to the reference input of reading circuit.In read mode, address is chosen The column that signal represents, while reference columns are chosen, it is connected to reading circuit.

In a specific implementation process of the invention: K=3, n=8+1=9 are a common selections.Containing by 3 ground 8 column of location line options and a column reference unit.

Further, common bit lines 7, common source line 8 connect read-write cell.

Further, pre decoder 3 chooses a bit line 1, then with the matched selection signal 4 of bit line 1 and other selection signals 4 The signal of output is opposite.

Public BL of the invention and public SL are connected to read/write cell.In this way, only reading and writing selected column each time.Its , although selecting pipe opens, read-write operation will not occur for its column because its BL and SL are shorted.

The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea Technical solution, all should be within the scope of protection determined by the claims.

Claims

1. a kind of MRAM chip, comprising: the MRAM array and pre decoder of source line and bit line vertical arrangement, which is characterized in that institute Stating MRAM array includes multiple subarrays, and the subarray includes that a common source line is connected to all units, and each column of connection Multiple bit lines；Each bit line connects the first transmission gate, the second transmission gate；First transmission gate connects the common source Line, second transmission gate connect common bit lines；The pre decoder includes: more address wire inputs and the bit line quantity The output of matched selection signal and its inversion signal；The selection signal and its inversion signal output end are connected to each height First transmission gate corresponding to the corresponding bit line of array, the second transmission gate control first transmission gate, second transmission gate Any opening, another closing.

2. MRAM chip according to claim 1, which is characterized in that the subarray further include: reference unit column, institute Pre decoder is stated with a reference input, the reference bit lines of reference unit column are separately connected the public affairs by two third transmission gates Common source line, the reference input.

3. MRAM chip according to claim 1, which is characterized in that the common bit lines, common source line connection are read R/w cell.

4. MRAM chip according to claim 2, which is characterized in that the pre decoder chooses a bit line, then with it is described The matched selection signal of bit line is opposite with the signal that selection signal described in other exports.