CN111079293B - Jitter simulation analysis method containing dynamic power supply noise - Google Patents
Jitter simulation analysis method containing dynamic power supply noise Download PDFInfo
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- CN111079293B CN111079293B CN201911317661.6A CN201911317661A CN111079293B CN 111079293 B CN111079293 B CN 111079293B CN 201911317661 A CN201911317661 A CN 201911317661A CN 111079293 B CN111079293 B CN 111079293B
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Abstract
A jitter simulation analysis method containing dynamic power supply noise comprises the following steps: 1) building a circuit netlist based on the time sequence path, and connecting VDD and VSS of each circuit unit to a direct-current voltage source; 2) at the starting point of the sequential circuit, a clock signal is created according to the frequency designated by a user; 3) acquiring the falling amount on VDD and the rising amount on VSS of each unit circuit; 4) creating a voltage source of sine or cosine waveform of a frequency given by a user instead of a direct voltage source connected to VDD and VSS; 5) the SPICE simulation is run, the worst case of the clock signal jitter of the adjacent period caused by the given falling amount of VDD and the rising amount of VSS is obtained, and the worst case is used as a reference for setting the allowance for the timing analysis. The jitter simulation analysis method containing the dynamic power supply noise accurately reflects the worst situation of the jitter caused by the power supply noise, and provides effective reference for setting allowance when an engineer performs time sequence analysis.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a jitter simulation analysis method.
Background
As the clock frequency in the field of digital design of integrated circuits is increasing, jitter is receiving more and more attention. In high-speed systems, the jitter of the clock signal directly reduces the margin of the setup hold time of the logic digital system, which seriously affects the logic operation and design performance. Jitter is defined as the short-term deviation of a particular instant of a signal from its ideal temporal position. The jitter is caused by many reasons, and one important factor is dynamic IR drop of the power supply network, and how to take the dynamic drop into account is a difficulty when an engineer performs timing analysis and sign-off by using SPICE (simulation circuit simulator) simulation.
The dynamic voltage drop refers to a phenomenon that the voltage on a power supply network and a ground network in an integrated circuit drops or rises, and the root cause is the voltage drop generated by the dynamic current passing through the parasitic resistance on the power supply network and the ground network when each unit in the circuit overturns. The dynamic voltage drop causes a transient reduction in the effective voltage of the unit modules in the circuit, thereby exacerbating the jitter phenomenon in the clock signal transmission process. Some EDA tools in the industry can analyze a power supply and ground network of a chip to obtain a dynamic voltage drop value of each unit in a circuit, but the data of the voltage drops only reflect the worst condition of an effective voltage of the unit circuit within a set working mode and time, and cannot be directly used for simulation analysis of the jitter effect.
The jitter description in the timing analysis is a signal of a clock tree, the object of the dynamic voltage drop analysis is noise on a power supply network, and the jitter description and the dynamic voltage drop analysis have a certain causal relationship, but cannot be directly corresponding to each other by a conventional method in specific analysis. Specifically, in the jitter simulation analysis, delay and transition time in the clock signal transmission process are affected by the effective voltage at the switching time and power supply noise, but such power supply noise is actually caused by the switching (or the switching of adjacent cells) of the clock signal when passing through the cell circuit. Therefore, the result of the dynamic droop analysis, whether the value of the IR drop or the waveform curve on the power supply network, cannot directly correspond to the clock signal edge when performing SPICE simulation on the timing path.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a jitter simulation analysis method containing dynamic power supply noise, which converts the existing dynamic voltage drop data into the power supply noise capable of being used for jitter simulation, accurately reflects the worst situation of the jitter caused by the power supply noise, and provides an effective reference for setting margin when an engineer performs time sequence analysis.
To achieve the above object, at least one embodiment of the present invention provides a jitter simulation analysis method including dynamic power supply noise, including the following steps:
the jitter simulation analysis method containing dynamic power supply noise comprises the following steps:
1) building a circuit netlist based on the time sequence path, and connecting VDD and VSS of each circuit unit to a direct-current voltage source;
2) at the starting point of the sequential circuit, a clock signal is created according to the frequency specified by a user;
3) acquiring drop on VDD and bound on VSS of each unit circuit;
4) creating a voltage source of sine or cosine waveform of a frequency given by a user instead of a direct voltage source connected to VDD and VSS;
5) the SPICE simulation is run, the worst case of clock signals jitter of adjacent cycles caused by the given drop of VDD and the round of VSS is obtained, and the worst case is used as a reference for setting a margin for timing analysis.
Further, in the step 1), the VDD and VSS of each circuit unit are connected to the dc voltage source, and the circuit units are connected to VDD and VSS respectively by using independent dc voltage sources.
Further, the step 3) further comprises,
using drop/2 as amplitude and VDD-drop/2 as direct current offset, creating a voltage source with sine or cosine waveform of frequency given by a user, and replacing the direct current voltage source connected to VDD;
Using the bound/2 as amplitude and the bound/2 as direct current offset, creating a voltage source with sine or cosine waveform of frequency given by a user to replace a direct current voltage source connected to VSS;
where drop is the drop on VDD and bound is the rise on VSS.
Further, the step 3) further comprises,
using (drop + bounce)/2 as amplitude, VDD- (drop + bounce)/2 as DC offset, using a voltage source with sine or cosine waveform with frequency given by a user to replace a DC voltage source connected to VDD, and grounding VSS;
where drop is the drop on VDD and bound is the rise on VSS.
Further, the user-specified frequency is a noise frequency in the power network other than the fundamental frequency and the harmonic frequency of the clock signal.
In order to achieve the above object, at least one embodiment of the present invention provides a jitter simulation analysis device including dynamic power noise, which includes a memory and a processor, wherein the memory stores a program running on the processor, and the processor implements the steps of the method for jitter simulation analysis including dynamic power noise when running the program.
To achieve the above object, the present invention provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the jitter simulation analysis method including dynamic power supply noise described above.
According to the jitter simulation analysis method containing the dynamic power supply noise, the value of the IR drop is converted into the dynamic noise on the power supply network, the voltage values of different power supplies and grounds within a given drop/bounce range are adopted in each jump when a clock signal reaches a unit module, and the worst situation of the clock signal jitter caused by the IR drop can occur when the number of clock cycles of simulation analysis is large enough. The jitter obtained by the method can truly reflect the maximum influence caused by the IR drop, and provides an accurate reference for setting effective and non-excessive margin in time sequence analysis.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a jitter simulation analysis method including dynamic power supply noise according to the present invention;
FIG. 2 is a schematic diagram of the jitter concept;
FIG. 3 is a schematic diagram of a cell circuit setting clock signals and DC VDD and VSS voltages according to the present invention;
FIG. 4 is a schematic diagram of a simulation including dynamic power supply noise according to the present invention;
FIG. 5 is a schematic diagram of setting dynamic power supply noise according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a jitter simulation analysis apparatus including dynamic power supply noise according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
FIG. 2 is a diagram illustrating the concept of jitter, and as shown in FIG. 2, for an ideal cycle, the arrival time of the clock edge in the next cycle is determined, and the offset of the arrival time of the clock edge is jitter.
Fig. 1 is a flowchart illustrating a jitter simulation analysis method including dynamic supply noise according to the present invention, and the following description will discuss the jitter simulation analysis method including dynamic supply noise in detail with reference to fig. 1.
First, in step 101, a circuit netlist is built based on a timing path, and VDD and VSS of each circuit unit are connected to a dc voltage source. FIG. 3 is a schematic diagram of setting clock signals and DC VDD and VSS voltages for a unit circuit according to the present invention, and FIG. 3 is a schematic diagram of setting clock signals and DC VDD and VSS voltages for a unit circuit during circuit simulation.
In the invention, VDD and VSS of each circuit unit are respectively connected to independent direct current voltage sources, or VDD can be connected to a direct current voltage source, and VSS is always grounded.
At step 102, at the start of the timing circuit, a clock signal is created according to a user-specified frequency ω 1.
In step 103, the drop amount (drop) on each cell circuit VDD and the rise amount (round) on VSS are obtained from the output results of other EDA tools (such as rednawk, Voltus, etc., which are popular in the industry).
In step 104, a voltage source of sine or cosine waveform of a user-given frequency is created instead of a dc voltage source connected to VDD and VSS.
In the present invention, drop/2 is used as the amplitude and VDD-drop/2 is used as the DC offset (offset) to create a voltage source with a sine (or cosine) waveform with frequency ω 2 instead of the DC voltage source connected to VDD described in step 101. The frequency ω 2 is set by the user and can be a typical noise frequency in the power supply network (e.g., 500 MHz), but the fundamental frequency (usually ω 1) and harmonic frequencies of the clock signal should be avoided.
In the present invention, a voltage source with sine (or cosine) waveform with frequency ω 3 is created with bound/2 as amplitude and bound/2 as DC offset, instead of the DC voltage source connected to VSS as described in step 101. The frequency ω 3 is set by the user and can be a typical noise frequency in the power supply network (e.g. 500 MHz), but the fundamental frequency (usually ω 1) and harmonic frequencies of the clock signal should be avoided.
In the present invention, (drop + bound)/2 is taken as the amplitude, and VDD- (drop + bound)/2 is taken as the dc offset, creating a voltage source of sine (or cosine) waveform with frequency ω 4, instead of the dc voltage source connected to VDD described in step 101, VSS is always grounded. The frequency ω 4 is set by the user and can be a typical noise frequency in the power supply network (e.g. 500 MHz), but the fundamental frequency (usually ω 1) and the harmonic frequencies of the clock signal should be avoided.
At step 105, SPICE simulation is run to obtain the worst case of clock signals jitter of adjacent cycles caused by the given drop of VDD and the round of VSS, and the worst case is used as a reference for setting margin (margin) for timing analysis.
In the invention, SPICE simulation is operated, when a circuit unit turns over when a clock edge arrives, the effective voltage obtained from the power supply and the ground network in each period is different because the noise frequency of the power supply and the ground network is different from the fundamental wave and harmonic frequency of a clock signal; when the number of clock cycles is large enough, the jitter phenomenon of adjacent cycles can cause the worst case that can be generated by the given launch of drop and VSS of VDD, and the worst case is used as a reference for setting the timing analysis margin.
FIG. 4 is a diagram illustrating a simulation of the dynamic power noise according to the present invention, as shown in FIG. 4, the dynamic noise of VDD is set according to the value of drop of VDD in the IR drop result; and setting the dynamic noise of the VSS according to the value of the bounce of the VSS.
FIG. 5 is a schematic diagram illustrating setting of dynamic power noise according to another embodiment of the present invention, as shown in FIG. 5, the dynamic noise of VDD is set according to the drop value of VDD and the bounce value of VSS in the IR drop result, and VSS is always grounded.
Example 1
In the embodiment of the present invention, when performing SPICE simulation on the timing path, taking a unit BUFF (exemplified as U1) as an example, the ideal power voltage is 1.1V, and the frequency of the clock signal is 400 MHz. The results of this unit in the IR drop analysis are: drop on VDD is 0.06V, and bound on VSS is 0.04V.
The description of this cell in the circuit is:
XU1 U1/Z U1/A U1/VDD U1/VSS BUFF
without considering IR drop, power and ground voltages are set for U1:
VU1/VDD U1/VDD 0 1.1
VU1/VSS U1/VSS 0 0
and (3) converting the drop in the IR drop result into dynamic noise on VDD and converting the bounce into dynamic noise on VSS, and assuming that the noise frequency of the power supply network is 333MHz, the power supply and ground voltage of U1 is as follows:
VU1/VDD U1/VDD 0 sin (1.07 0.03 3.33e8 0 0)
VU1/VSS U1/VSS 0 sin (0.02 0.02 3.33e8 0 0)
another way to set dynamic power supply noise, combining the drop of VDD and the bounce of VSS, the power and ground voltages of U1 are described as:
VU1/VDD U1/VDD 0 sin (1.05 0.05 3.33e8 0 0)
VU1/VSS U1/VSS 0 0
The user may simulate multiple (e.g., 5000) clock cycles, measuring the value of jitter; the power supply noise frequency can also be adjusted, SPICE simulation is carried out for a plurality of times, and the measured jitter result is analyzed and used as the basis for setting the allowance of time sequence analysis.
Example 2
Fig. 6 is a schematic structural diagram of a jitter simulation analysis apparatus containing dynamic power supply noise according to the present invention, and as shown in fig. 6, the jitter simulation analysis apparatus 60 containing dynamic power supply noise according to the present invention includes a processor 601 and a memory 602, where the memory 602 stores a program, and when the program is read and executed by the processor 601, the program performs the following operations:
building a circuit netlist based on a time sequence path, and connecting VDD and VSS of each circuit unit to a direct current voltage source;
at the starting point of the sequential circuit, a clock signal is created according to a frequency omega 1 specified by a user;
obtaining drop on each unit circuit VDD and bound on VSS;
creating a voltage source of sine or cosine waveform of a user given frequency instead of a direct voltage source connected to VDD and VSS;
the SPICE simulation is run, the worst case of clock signals jitter of adjacent cycles caused by the given drop of VDD and the round of VSS is obtained, and the worst case is used as a reference for setting a margin for timing analysis.
The computer readable storage medium provided by the present invention may be located on one or more computing devices, where the computing device includes a processor, and the processor executes a computer program in the computer readable storage medium on the computing device, so as to implement the steps of the jitter simulation analysis method including dynamic power supply noise according to the present invention.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A jitter simulation analysis method containing dynamic power supply noise comprises the following steps:
1) building a circuit netlist based on a time sequence path, and connecting VDD and VSS of each circuit unit to a direct current voltage source;
2) at the starting point of the sequential circuit, a clock signal is created according to the frequency designated by a user;
3) Acquiring the falling amount on VDD and the rising amount on VSS of each circuit unit;
4) creating a voltage source of sine or cosine waveform of a frequency given by a user instead of a direct voltage source connected to VDD and VSS;
5) the SPICE simulation is run, the worst case of the clock signal jitter of the adjacent period caused by the given falling amount of VDD and the rising amount of VSS is obtained, and the worst case is used as a reference for setting the allowance for the timing analysis.
2. The method for jitter simulation analysis including dynamic power supply noise of claim 1 wherein step 1) of connecting VDD and VSS of each circuit unit to dc voltage sources is to connect each circuit unit to VDD and VSS respectively using independent dc voltage sources.
3. The jitter simulation analysis method including dynamic power supply noise according to claim 1, wherein said step 4) further comprises,
using drop/2 as amplitude and VDD-drop/2 as direct current offset, creating a voltage source with sine or cosine waveform of frequency given by a user, and replacing the direct current voltage source connected to VDD;
using the bound/2 as amplitude and the bound/2 as direct current offset, creating a voltage source with sine or cosine waveform of frequency given by a user to replace a direct current voltage source connected to VSS;
Where drop is the drop on VDD and bound is the rise on VSS.
4. The jitter simulation analysis method including dynamic power supply noise of claim 1, wherein the step 4) further comprises,
using (drop + bounce)/2 as amplitude, VDD- (drop + bounce)/2 as DC offset, and using a voltage source with sine or cosine waveform of frequency given by a user to replace a DC voltage source connected to VDD, and grounding VSS;
where drop is the drop on VDD and bound is the rise on VSS.
5. The method for jitter simulation analysis including dynamic power supply noise of claim 3 or 4, wherein the user-specified frequency is a noise frequency in the power supply network other than the fundamental frequency and the harmonic frequency of the clock signal.
6. An apparatus for automatically group-repairing timing violations using load cells, comprising a memory and a processor, wherein the memory stores a program running on the processor, and the processor executes the program to perform the steps of the jitter simulation analysis method including dynamic power supply noise according to any one of claims 1-5.
7. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, carries out the steps of the jitter simulation analysis method including dynamic supply noise according to any one of claims 1 to 5.
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| CN112115676B (en) * | 2020-09-29 | 2021-10-26 | 飞腾信息技术有限公司 | Static voltage drop repairing method, device, equipment and storage medium |
| CN112464599B (en) * | 2020-11-26 | 2023-04-11 | 海光信息技术股份有限公司 | Method for determining power supply voltage data in static time sequence analysis of circuit |
| CN112613185B (en) * | 2020-12-30 | 2024-02-09 | 北京华大九天科技股份有限公司 | Modeling method for noise of composite current source |
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