CN112560377A

CN112560377A - Simulation verification method and system based on combination of virtual platform and FPGA

Info

Publication number: CN112560377A
Application number: CN202011441137.2A
Authority: CN
Inventors: 郭晨光; 何振; 罗文涛; 王秉文
Original assignee: Allwinner Technology Co Ltd
Current assignee: Allwinner Technology Co Ltd
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2021-03-26
Anticipated expiration: 2040-12-11
Also published as: CN112560377B

Abstract

The invention discloses a simulation verification method and a system based on combination of a virtual platform and an FPGA (field programmable gate array). the method comprises the steps of verifying, constructing a first conversion model, receiving a simulation request of a host model through the virtual platform based on TLM2.0, and converting the simulation request into a first data packet; constructing an FIFO transfer verification model according to a third-party PCIe DMA method, and simulating a data transceiving channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, and sending an analysis result to an RTL design DUT (device under test) according to an AHB/AXI (advanced high performance bus/extensible interface) protocol; and a simulation step, generating an executable file according to the host model and the second conversion model, storing the executable file into an upper computer for simulation, generating a burning file according to a third-party PCIe DMA method, the first conversion model and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation. The invention greatly reduces the economic cost and the verification cost of the simulation, and is convenient for users to flexibly optimize and modify according to the actual requirements.

Description

Simulation verification method and system based on combination of virtual platform and FPGA

Technical Field

The invention relates to the technical field of simulation verification, in particular to a simulation verification method and system based on the combination of a virtual platform and an FPGA.

Background

With the performance of SoC chips becoming higher and the design scale becoming larger and larger, the RTL simulation speed based on the conventional EDA tool has not been able to meet the project cycle requirements. At present, simulation through software and hardware cooperation is a common practice in the industry, one of the methods is to use an EDA tool to perform pure software hybrid simulation based on a functional model of a CPU/GPU/DSP and an RTL design, but if the RTL design is large in scale, the simulation speed is too slow and often unacceptable. Another method is to implement software and hardware co-simulation by using a virtual platform and a hardware accelerator together, but the usage cost of the hardware accelerator up to millions of dollars per year is not affordable for small and medium-sized chip companies.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a simulation verification method based on the combination of a virtual platform and an FPGA, which can reduce the economic cost of simulation verification and improve the simulation speed.

The invention also provides a simulation verification system based on the combination of the virtual platform and the FPGA, which is provided with the simulation verification method based on the combination of the virtual platform and the FPGA.

The simulation verification method based on the combination of the virtual platform and the FPGA comprises a verification step and a simulation step, wherein the verification step comprises the following steps: the method comprises the steps of constructing a first conversion model, receiving a simulation request of a host model through a virtual platform based on TLM2.0, converting the simulation request into a first data packet, receiving simulation reply data and returning the simulation reply data to the host model, wherein the simulation request comprises register configuration and excitation data; constructing an FIFO transfer verification model according to a third-party PCIe DMA method, and simulating a data transceiving channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; sequentially connecting the host model, the first conversion model, the FIFO transfer verification model, the second conversion model and the RTL design DUT, and building an EDA simulation platform for verification; and a simulation step, generating an executable file according to the host model and the second conversion model, storing the executable file into an upper computer for simulation, generating a burning file according to the third-party PCIe DMA method, the first conversion model and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation.

The simulation verification method based on the combination of the virtual platform and the FPGA has the following beneficial effects: TLM2.0 is converted into a corresponding RIFFA C + + interface, a first data packet is generated according to a simulation request, the first data packet is analyzed and sent to an RTL design DUT according to a hardware protocol, simulation is carried out, the economic cost and the verification cost of simulation are greatly reduced, and a user can flexibly optimize and modify the data packet according to actual requirements.

According to some embodiments of the invention the method of data interaction of the virtual platform with the host model comprises: the virtual platform is connected with a TLM _ initiator _ socket of the host model through a TLM _ target _ socket based on TLM2.0, receives the simulation request through a TLM _ genetic _ payload class, and converts the simulation request into the first data packet, wherein the TLM _ genetic _ payload class corresponds to an AHB/AXI request; and the virtual platform receives the simulation reply data through a RIFFA C + + API function, converts the simulation reply data into data load of a tlm _ generic _ payload class, and replies the data load to the host model through a tlm _ target _ socket class.

According to some embodiments of the invention, the first data packet comprises a header portion and a payload portion, wherein the header portion comprises a read-write type, a burst type, a host ID, and a trans number, and the payload portion comprises an address and a data length for each trans; the reply data is read-only data without a header.

According to some embodiments of the present invention, when the amount of the transmission DATA reaches the predetermined FIFO transmission depth and the DATA transmission is not finished, the FIFO transition verification model pulls down the CHNL _ RX _ DATA _ REN, marks that the channel is full, and pulls up the CHNL _ RX _ DATA _ REN to continue transmitting DATA after waiting for the first delay count.

According to some embodiments of the present invention, when the amount of received DATA reaches the predetermined FIFO receiving depth and the DATA transmission is not finished, the FIFO transition verification model pulls down the CHNL _ TX _ DATA _ REN, marks that the channel is full, and after waiting for the second delay count, pulls up the CHNL _ TX _ DATA _ REN to continue receiving DATA.

The simulation verification system based on the combination of the virtual platform and the FPGA according to the second aspect of the embodiment of the invention comprises: the system comprises a first conversion module, a second conversion module and a third conversion module, wherein the first conversion module is used for receiving a simulation request of a host model through a virtual platform based on TLM2.0, converting the simulation request into a first data packet, receiving simulation reply data and returning the simulation reply data to the host model, and the simulation request comprises register configuration and excitation data; the FIFO transfer verification module is used for simulating a data channel to receive and transmit data based on a third-party PCIe DMA method; the second conversion module is used for receiving the first data packet, analyzing the first data packet according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; the verification processing module is used for sequentially connecting the host model, the first conversion module, the FIFO transfer verification module, the second conversion module and the RTL design DUT and building an EDA simulation platform for verification; and the simulation management module is used for generating an executable file according to the host model and the first conversion module, storing the executable file into an upper computer for simulation, generating a burning file according to the third-party PCIe DMA method, the second conversion module and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation.

The simulation verification system based on the combination of the virtual platform and the FPGA has the following beneficial effects: the TML2.0 is converted into a corresponding RIFFA C + + interface, a first data packet is generated according to the simulation request, the first data packet is analyzed and sent to the RTL design DUT according to hardware, simulation is carried out, the economic cost and the verification cost of simulation are greatly reduced, and a user can flexibly optimize and modify the data packet according to actual requirements.

According to some embodiments of the invention, the first conversion module comprises: the first communication module is used for generating a C + + thread which is communicated with the FPGA hardware, interacting with the FPGA hardware and receiving the simulation reply data; and the first control module is used for judging whether the simulation reply data can be generated according to the simulation task of the host through a systemc thread and awakening the first communication module according to a judgment result.

According to some embodiments of the invention, the FIFO switchover validation module simulates the data channel based on RIFFA, comprising: the first state machine module is used for controlling the data transmission time sequence of the data channel and comprises: if the data channel is in an IDLE state, pulling up the CHNL _ RX signal and then entering an RX _ ACK state; if the DATA channel is in an RX _ ACK state, CHNL _ RX _ ACK is pulled high, the DATA channel enters an SIM _ DMI _ ACCESS state, and enters a SEND _ DATA state after random delay to transmit DATA; returning to an IDLE state after the data is sent; a second state machine module, configured to control a data receiving timing sequence of the data channel, including: if the data channel is in an IDLE state and the CHNL _ TX is high, pulling up a CHNL _ TX _ ACK signal and entering a TX _ ACK state; after entering a TX _ ACK state, pulling down CHNL _ TX _ ACK, clearing received DATA resources, and entering an RECV _ DATA state to receive DATA; and entering an IDLE state after the data is received.

According to some embodiments of the invention, the first state machine module further comprises: and the transmission busy simulation module is used for simulating a transmission DATA busy state, if the DATA channel is in a SEND _ DATA state, and the DATA channel detects that the transmission DATA amount reaches the preset FIFO transmission depth and DATA transmission is not finished, pulling down CHNL _ RX _ DATA _ REN and entering a FIFO _ FULL _ CLEAN state, performing first delay counting, entering the SEND _ DATA state after the first delay counting is overtime, and pulling up CHNL _ RX _ DATA _ REN to continue to transmit DATA.

According to some embodiments of the invention, the second state machine module further comprises: and the receiving busy simulation module is used for simulating a receiving DATA busy state, if the DATA channel is in an RECV _ DATA state, and the DATA channel detects that the receiving DATA amount reaches the preset FIFO receiving depth and the DATA transmission is not finished, pulling down CHNL _ TX _ DATA _ REN and entering an FIFO _ FULL _ CLEAN state, performing second delay counting, entering the RECV _ DATA state after the second delay counting is overtime, and pulling up CHNL _ TX _ DATA _ REN to continue receiving DATA.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a schematic flow chart of a method according to an embodiment of the present invention;

FIG. 2 is a block schematic diagram of modules of a system of an embodiment of the invention;

FIG. 3 is a schematic diagram of a system building EDA for simulation verification according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a simulation operation performed by the system according to the embodiment of the present invention;

FIG. 5 is a diagram illustrating a first state machine transition in the system according to an embodiment of the present invention;

fig. 6 is a diagram illustrating a second state machine transition in the system according to the embodiment of the present invention.

Reference numerals:

the first conversion module 100, the FIFO transfer verification module 200, the second conversion module 300, the verification processing module 400 and the simulation management module 500;

a first communication module 110, a first control module 120;

a first state machine module 210, a send busy simulation module 211, a second state machine module 220, and a receive busy simulation module 221.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

The noun explains:

FPGA: programmable logic device, a semi-custom application-specific integrated circuit.

GPU: a graphics processor.

A CPU: a central processing unit.

And (4) DSP: a digital signal processor.

NPU: a neural network processor.

EDA (electronic design automation): the electronic design automation software is a general term.

PCIe: a high speed serial computer expansion bus standard.

RTL: register conversion stage circuits, generally refer to circuits described using a hardware description language.

DUT: a target device under test.

Referring to fig. 1, the method of the embodiment of the present invention includes a verification step and a simulation step, wherein the verification step includes: constructing a first conversion model, receiving a simulation request of a host model through a virtual platform based on TLM2.0, converting the simulation request into a first data packet, receiving simulation reply data and returning the simulation reply data to the host model, wherein the simulation request comprises register configuration and excitation data; constructing an FIFO transfer verification model according to a third-party PCIe DMA method, and simulating a data transceiving channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; sequentially connecting a host model, a first conversion model, an FIFO (first in first out) switching verification model, a second conversion model and an RTL (real time L) design DUT (device under test), and building an EDA (electronic design automation) simulation platform for verification; and a simulation step, generating an executable file according to the host model and the first conversion model, storing the executable file into an upper computer for simulation, generating a burning file according to a third-party PCIe DMA method, the second conversion model and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation. The virtual platform is connected with a tlm _ initiator _ socket in a host model through a tlm _ target _ socket class based on TML2.0, receives a simulation request through a tlm _ genetic _ payload class and converts the simulation request into a first data packet; each tlm _ generic _ payload class corresponds to an AHB/AXI request; the first packet includes: and the header part comprises a read-write type, a burst type, a host ID, a trans number (one trans corresponds to a request of an AHB/AXI protocol), and an address and data length of each trans of the load part. The virtual platform receives the reply data through a RIFFA C + + API function, converts the reply data into a data load of a tlm _ genetic _ payload class, and replies the data load to the host through a tlm _ target _ socket class; the emulation reply data does not include the header, and only has the data of the read-only load part. In the embodiment of the invention, the host model on the virtual platform can be an open source CPU model, a third party C + +/SystemC model, or a self-developed host excitation model or a framework exploration model.

In the embodiment of the invention, the RIFFA, a third-party PCIe DMA is taken as an example, a corresponding FIFO transfer verification model is constructed, a plurality of RIFFA data channels can be simulated to communicate with the FPGA, and each data channel comprises a data receiving FIFO interface and a data transmitting FIFO interface which are mutually independent; for a single DATA channel, when the sending DATA amount reaches the preset FIFO sending depth and the DATA transmission is not finished, pulling down CHNL _ RX _ DATA _ REN, marking that the channel is full, and after waiting for the first delay count, pulling up CHNL _ RX _ DATA _ REN to continue sending DATA; when the received DATA amount reaches the preset FIFO receiving depth and the DATA transmission is not finished, the CHNL _ TX _ DATA _ REN is pulled down, the channel is marked to be full, and after waiting for the second delay count, the CHNL _ TX _ DATA _ REN is pulled up to continue receiving DATA.

Referring to fig. 2, the system of the embodiment of the present invention includes: the first conversion module 100 is configured to receive, by the virtual platform, a simulation request of the host model based on TLM2.0, convert the simulation request into a first data packet, receive simulation reply data, and return the simulation reply data to the host model, where the simulation request includes register configuration and excitation data; the FIFO transfer verification module 200 is used for simulating a data channel to receive and transmit data based on a third-party PCIe DMA method; the second conversion module 300 is configured to receive the first data packet, perform parsing according to a preset protocol, send a parsing result to the RTL design DUT according to the AHB/AXI protocol hardware protocol, acquire corresponding simulation reply data, and package the simulation reply data based on the preset protocol; the verification processing module 400 is used for sequentially connecting the host model, the first conversion module 100, the FIFO transfer verification module 200, the second conversion module 300 and the RTL design DUT, and building an EDA simulation platform for verification; and the simulation management module 500 is used for generating an executable file according to the host model and the first conversion module 100, storing the executable file into an upper computer for simulation, generating a burning file according to a third-party PCIe DMA method, the second conversion module 300 and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation.

In the embodiment of the present invention, a packet protocol is constructed to perform data exchange between a virtual platform and an RTL design DUT of an FPGA, wherein a header of a first data packet sent by the virtual platform includes a read-write type, a burst type, a host ID, and a trans number (one trans corresponds to a request of an AHB/AXI protocol), and a load part includes: address and data length of each trans. The simulation reply data returned by the FPGA does not include a packet header and only has loaded read-only data.

A first conversion module 100, configured to convert the TLM2.0 interface into a RIFFA C + + API function, referring to fig. 2, includes: the first communication module 110 is configured to generate a C + + thread for communicating with the FPGA hardware, interact with the FPGA hardware, and receive hardware reply data; the first control module 120 is configured to determine whether hardware reply data needs to be generated according to a simulation task of the host through a systemc thread, and wake up the first communication module 110 according to a determination result. The system mc thread of the first control module 120 generates a C + + thread in the first communication module 110 in the action domain of the sc _ start function call, and the thread is in a dormant state until the first control module 120 determines that the hardware reply data needs to be acquired, the first control module 120 wakes up the first communication module 110, the first communication module 110 requests to receive the hardware reply data, and the communication is completed and the communication enters the dormant state again. The first communication module 110 detects the end of the systemc thread in the first control module 120 and the C + + thread also exits. In the embodiment of the invention, the multithreading of the system mc and the C + + is mixed and programmed to combine the system mc model and the two parts of functions communicated with FPGA hardware, and compared with the common socket which writes the two parts of functions into independent programs for communication, the simulation is simplified by reducing the complexity of function matching; the speed of the systemc simulation is made irrelevant to the rate of the hardware communication parts, reducing the probability of the systemc simulation being blocked.

The FIFO transfer verification module 200 may simulate several data channels corresponding to a pin level model of the system mc. Taking RFIFA as an example, the method can obtain RIFFA _ fifo instance from a global static container and call the data transceiving function of RIFFA _ fifo through a global function which is homonymous with RIFFA API. By declaring a pin level signal having the same name as the hardware protocol, the FIFO transfer verification module can be directly connected with an RTL IP (IO pin) with an RIFFA hardware protocol interface and can be simulated.

The FIFO transfer verification module 200 completes communication with the FPGA through a first path and a second path, wherein the first path is used for sending data to the FPGA, and the second path is used for sending and receiving data from the FPGA; referring to fig. 2, the first state machine module 210 and the second state machine module 220 control the state machines of the first path and the second path, respectively.

The state machine of the first path, with reference to fig. 5, is as follows:

in an IDLE state, entering an RX _ ACK state after a CHNL _ RX signal is pulled up;

in RX _ ACK state, if CHNL _ RX _ ACK is pulled high, SIM _ DMI _ ACCESS state is entered;

simulating a section of random delay in the SIM _ DMI _ ACCESS state, and entering the SEND _ DATA state to transmit DATA after timeout;

and fourthly, in the SEND _ DATA state, entering an IDLE state if the DATA transmission is finished.

In order to simulate that the interior of the RIFFA channel is busy in the middle of transmission, in the embodiment of the present invention, the sending busy simulation module 211 is in the SEND _ DATA state in the state machine of the first path, detects the amount of the sent DATA, and if the sent DATA reaches the preset FIFO sending DATA depth and the transmission is not finished, pulls down CHNL _ RX _ DATA _ REN to enter the FIFO _ FULL _ CLEAN state, performs the first delay count, returns to the SEND _ DATA state after timeout, and pulls up CHNL _ RX _ DATA _ REN to continue sending DATA.

The state machine of the second path, with reference to fig. 6, is as follows:

firstly, if CHNL _ TX is high in an IDLE state, pulling up CHNL _ TX _ ACK and entering a TX _ ACK state;

and secondly, after the TX _ ACK state is entered, pulling down CHNL _ TX _ ACK, clearing the DATA receiving resource and entering an RECV _ DATA state.

And IDLE state is entered when transmission is finished in RECV _ DATA state.

In order to simulate that the interior of the RIFFA channel is busy in the middle of transmission, in the embodiment of the invention, the state machine of the second path is in the RECV _ DATA state through the receiving busy simulation module 221, the received DATA amount is detected, if the received DATA amount reaches the preset FIFO received DATA depth and transmission is not finished, the CHNL _ TX _ DATA _ REN is pulled down to enter the FIFO _ FULL _ CLEAN state, second delay counting is carried out, and the RECV _ DATA state is returned to be pulled up to be continuously used for receiving DATA after time out.

In the system of the embodiment of the present invention, when simulation is applied, verification processing is performed first, taking RIFFA, which is one of third party pci edma methods, as an example, in an EDA environment, referring to fig. 3, a simulation platform of pure EDA is built through a first conversion module 100, a FIFO transfer verification module 200, a second conversion module 300, a host model and an RTL design DUT (hardware design code); the FIFO transfer verification module 200 is an RFFIA FIFO transfer verification module corresponding to RFFIA, which is referred to as RFFIA FIFO module for short. At this time, the virtual platform side is responsible for sending register configuration and excitation data to the first conversion module 100, the first conversion module 100 packages the request into first data, the first data passes through the RFFIA FIFO module and is sent to the second conversion module 300 on the FPGA side for protocol conversion (converting the FIFO interface into AH/AXI RTL), and the received first data packet is unpacked and sent to the RTL design DUT according to the hardware protocol. Reply data of the RTL design DUT is packed in the second conversion module 300 and sent to the first conversion module 100 on the virtual platform side through the RFFIA FIFO module, and the reply data is returned to the host model by the first conversion module 100.

After the EDA simulation environment is verified, next step of simulation operation is carried out, and the method comprises the following steps:

firstly, generating an executable file of an OSCI (an OSCI standard, namely a program developed based on an acellera open source standard and C + + codes) through a host model and a second conversion module, and copying the executable file to an upper computer connected with the FPGA;

secondly, connecting the RTL code and the RTL design code of the RIFFA with a PCIecontroller RTL code provided by an FPGA manufacturer to generate a bin file for burning the FPGA and downloading the bin file to the FPGA;

and thirdly, operating a register and a storage space of an RTL design code on the python debug FPGA.

And fourthly, running the executable program of the OSCI and performing joint simulation on the FPGA. In the system for simulating operation, referring to fig. 4, the virtual platform side is responsible for sending register configuration and excitation data to the first conversion module 100, and the first conversion module 100 packs the request into first data and sends the first data to the FPGA side. The FPGA side receives the first data packet through the RFFIA, performs protocol conversion through the second conversion module 300, unpacks the first data packet, and sends the first data packet to the RTL design DUT according to the AHB/AXI protocol. The emulation reply data is packaged by the second conversion module 300 and then returned to the virtual platform side through the RFFIA.

Although specific embodiments have been described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are equally within the scope of this disclosure. For example, any of the functions and/or processing capabilities described in connection with a particular device or component may be performed by any other device or component. In addition, while various illustrative implementations and architectures have been described in accordance with embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications of the illustrative implementations and architectures described herein are also within the scope of the present disclosure.

Certain aspects of the present disclosure are described above with reference to block diagrams and flowchart illustrations of systems, methods, systems, and/or computer program products according to example embodiments. It will be understood that one or more blocks of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by executing computer-executable program instructions. Also, according to some embodiments, some blocks of the block diagrams and flow diagrams may not necessarily be performed in the order shown, or may not necessarily be performed in their entirety. In addition, additional components and/or operations beyond those shown in the block diagrams and flow diagrams may be present in certain embodiments.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions, elements or steps, or combinations of special purpose hardware and computer instructions.

Program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

The software components may be encoded in any of a variety of programming languages. An illustrative programming language may be a low-level programming language, such as assembly language associated with a particular hardware architecture and/or operating system platform. Software components that include assembly language instructions may need to be converted by an assembler program into executable machine code prior to execution by a hardware architecture and/or platform. Another exemplary programming language may be a higher level programming language, which may be portable across a variety of architectures. Software components that include higher level programming languages may need to be converted to an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages include, but are not limited to, a macro language, a shell or command language, a job control language, a scripting language, a database query or search language, or a report writing language. In one or more exemplary embodiments, a software component containing instructions of one of the above programming language examples may be executed directly by an operating system or other software component without first being converted to another form.

The software components may be stored as files or other data storage constructs. Software components of similar types or related functionality may be stored together, such as in a particular directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims

1. A simulation verification method based on the combination of a virtual platform and an FPGA comprises a verification step and a simulation step, and is characterized in that,

the verifying step includes: the method comprises the steps of constructing a first conversion model, receiving a simulation request of a host model through a virtual platform based on TLM2.0, converting the simulation request into a first data packet, receiving simulation reply data and returning the simulation reply data to the host model, wherein the simulation request comprises register configuration and excitation data; constructing an FIFO transfer verification model according to a third-party PCIe DMA method, and simulating a data transceiving channel; constructing a second conversion model, receiving the first data packet, analyzing according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol; sequentially connecting the host model, the first conversion model, the FIFO transfer verification model, the second conversion model and the RTL design DUT, and building an EDA simulation platform for verification;

and a simulation step, generating an executable file according to the host model and the first conversion model, storing the executable file into an upper computer for simulation, generating a burning file according to the third-party PCIe DMA method, the second conversion model and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation.

2. The simulation verification method based on the combination of the virtual platform and the FPGA according to claim 1, wherein the method for the data interaction between the virtual platform and the host model comprises the following steps:

the virtual platform is connected with a TLM _ initiator _ socket of the host model through a TLM _ target _ socket based on TLM2.0, receives the simulation request through a TLM _ genetic _ payload class, and converts the simulation request into the first data packet, wherein the TLM _ genetic _ payload class corresponds to an AHB/AXI request;

and the virtual platform receives the simulation reply data through a RIFFA C + + API function, converts the simulation reply data into data load of a tlm _ generic _ payload class, and replies the data load to the host model through a tlm _ target _ socket class.

3. The virtual platform and FPGA association based emulation verification system of claim 1, wherein the first data packet comprises a header portion and a payload portion, wherein the header portion comprises a read-write type, a burst type, a host ID and a trans number, and the payload portion comprises an address and a data length for each trans; the reply data is read-only data without a header.

4. The virtual platform and FPGA based emulation verification system of claim 1 wherein said FIFO switchover verification model pulls down CHNL _ RX _ DATA _ REN when the amount of transmitted DATA reaches a predetermined FIFO transmission depth and DATA transmission is not finished, marks that the channel is full, and after waiting for the first latency count, pulls up CHNL _ RX _ DATA _ REN to continue transmitting DATA.

5. The virtual platform and FPGA based emulation verification system of claim 1 wherein said FIFO switchover verification model pulls down CHNL _ TX _ DATA _ REN when the amount of received DATA reaches a predetermined FIFO receive depth and DATA transfer is not complete, marks that the channel is full, and after waiting for a second latency count, pulls up CHNL _ TX _ DATA _ REN to continue receiving DATA.

6. A simulation verification system based on combination of a virtual platform and an FPGA is characterized by comprising:

the system comprises a first conversion module, a second conversion module and a third conversion module, wherein the first conversion module is used for receiving a simulation request of a host model through a virtual platform based on TLM2.0, converting the simulation request into a first data packet, receiving simulation reply data and returning the simulation reply data to the host model, and the simulation request comprises register configuration and excitation data;

the FIFO transfer verification module is used for simulating a data channel to receive and transmit data based on a third-party PCIe DMA method;

the second conversion module is used for receiving the first data packet, analyzing the first data packet according to a preset protocol, sending an analysis result to an RTL design DUT according to an AHB/AXI protocol, acquiring corresponding simulation reply data, and packaging the simulation reply data based on the preset protocol;

the verification processing module is used for sequentially connecting the host model, the first conversion module, the FIFO transfer verification module, the second conversion module and the RTL design DUT and building an EDA simulation platform for verification;

and the simulation management module is used for generating an executable file according to the host model and the first conversion module, storing the executable file into an upper computer for simulation, generating a burning file according to the third-party PCIe DMA method, the second conversion module and the RTL design DUT, downloading the burning file to the FPGA, and operating the executable file by the upper computer to be connected with the FPGA for joint simulation.

7. The virtual platform and FPGA based emulation verification system of claim 6, wherein said first conversion module comprises:

the first communication module is used for generating a C + + thread which is communicated with the FPGA hardware, interacting with the FPGA hardware and receiving the simulation reply data;

and the first control module is used for judging whether the simulation reply data can be generated according to the simulation task of the host through a systemc thread and awakening the first communication module according to a judgment result.

8. The virtual platform and FPGA association based emulation verification system of claim 6 wherein said FIFO switchover verification module simulates said data channel based on RIFFA comprising:

the first state machine module is used for controlling the data transmission time sequence of the data channel and comprises: if the data channel is in an IDLE state, pulling up the CHNL _ RX signal and then entering an RX _ ACK state; if the DATA channel is in an RX _ ACK state, CHNL _ RX _ ACK is pulled high, the DATA channel enters an SIM _ DMI _ ACCESS state, and enters a SEND _ DATA state after random delay to transmit DATA; returning to an IDLE state after the data is sent;

a second state machine module, configured to control a data receiving timing sequence of the data channel, including: if the data channel is in an IDLE state and the CHNL _ TX is high, pulling up a CHNL _ TX _ ACK signal and entering a TX _ ACK state; after entering a TX _ ACK state, pulling down CHNL _ TX _ ACK, clearing received DATA resources, and entering an RECV _ DATA state to receive DATA; and entering an IDLE state after the data is received.

9. The virtual platform and FPGA association based simulation verification system of claim 8 wherein said first state machine module further comprises:

and the transmission busy simulation module is used for simulating a transmission DATA busy state, if the DATA channel is in a SEND _ DATA state, and the DATA channel detects that the transmission DATA amount reaches the preset FIFO transmission depth and DATA transmission is not finished, pulling down CHNL _ RX _ DATA _ REN and entering a FIFO _ FULL _ CLEAN state, performing first delay counting, entering the SEND _ DATA state after the first delay counting is overtime, and pulling up CHNL _ RX _ DATA _ REN to continue to transmit DATA.

10. The virtual platform and FPGA association based simulation verification system of claim 8 wherein said second state machine module further comprises:

and the receiving busy simulation module is used for simulating a receiving DATA busy state, if the DATA channel is in an RECV _ DATA state, and the DATA channel detects that the receiving DATA amount reaches the preset FIFO receiving depth and the DATA transmission is not finished, pulling down CHNL _ TX _ DATA _ REN and entering an FIFO _ FULL _ CLEAN state, performing second delay counting, entering the RECV _ DATA state after the second delay counting is overtime, and pulling up CHNL _ TX _ DATA _ REN to continue receiving DATA.