CN110765715A - GPU chip-oriented rendering output unit performance simulation method and platform - Google Patents
GPU chip-oriented rendering output unit performance simulation method and platform Download PDFInfo
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Abstract
The invention relates to the technical field of computer hardware verification, in particular to a rendering output unit performance verification method and platform for a GPU chip. The method includes the steps of building a graphic processing unit GPU chip TLM virtual prototype platform based on SystemC (the virtual prototype verification platform comprises a rasterization unit, a rendering output unit, a color buffer unit and a depth buffer unit), converting a TLM transaction-level port of the GPU rendering output unit into a hardware signal-level port, embedding a rendering output RTL unit into the TLM virtual prototype platform, and performing module-level and system-level function simulation on the RTL of the GPU to verify whether the rendering output unit meets performance indexes of a corresponding model. Before the FPGA stage, whether the performance of the GPU rendering output unit meets the requirements or not can be verified in advance, and development and verification work of a GPU chip in a subsequent stage is accelerated.
Description
Technical Field
The invention relates to the technical field of computer hardware verification, in particular to a GPU performance simulation method and platform based on SystemC TLM virtual prototype.
Background
With the increasing of graphics applications, it is difficult for early solutions of graphics rendering by CPU alone to meet the graphics Processing requirements of performance and technology growth, and Graphics Processing Units (GPUs) have come into play. From 1999, the first GPU product released by Nvidia to date, the development of GPU technology mainly goes through the fixed function pipeline stage, the separation stainer architecture stage, and the unified stainer architecture stage, the graphics processing capability of the GPU technology is continuously improved, and the application field is gradually expanded from the initial graphics drawing to the general computing field. The GPU pipeline has high speed, parallel characteristics and flexible programmability, and provides a good running platform for graphic processing and general parallel computing.
For the software/hardware architecture and design of a very large scale integrated circuit chip like a GPU, how to complete the crossover from the traditional specification document to the implementation of a hardware RTL circuit becomes an important and urgent problem in the engineering practice process. In order to shorten the huge gap from the system architecture document to the realization of the hardware RTL circuit, the function and the architecture of the whole circuit system must be described by adopting a high-level modeling language between the two stages, and the function and the architecture cannot be trapped in the complicated signal sequence and gate circuit of the hardware circuit.
The Transaction Level Models (TLM) are higher abstraction levels than the RTL Level, and at this Level, the executable specification of hardware can be quickly established and the system model can be quickly created according to the initial functional specification of the system. By adding timing details into the system, the performance of the system can be evaluated, and the structure of the system can be explored.
SystemC is a C + + based modeling platform organized and established and maintained by OSCI (open SystemC initiative), is completely written by C + + language, consists of a C + + class library and a simulation kernel which are well designed, supports hardware modeling and simulation on various abstraction levels such as a gate level, an RTL level and a system level, and is open to source codes. The SystemC supports hardware/software collaborative design, can describe the structure of a complex system consisting of hardware and software, and supports the description of hardware, software and interfaces in a C + + environment. The system C can realize the abstraction of the functional module, the communication module, the software module and the hardware module on various system level levels, and the concepts of data type description, clock and delay of the introduced port and signal are just based on the idea of unifying the description of the software and the hardware into a modeling language. The system C can be used for quickly and effectively establishing an accurate model of a software algorithm, a hardware system structure, an SoC interface and a system-level design, and simulating, verifying and optimizing the design (the simulation speed is generally 10-100 times that of VHDL or Verilog modeling by using the system C). The most basic structural unit of the SystemC is a module (module), which may contain other modules or processes (processes) and methods (methods), and the processes are like functions in C language to realize a certain behavior. The module communicates with other modules through interfaces (ports), and the interfaces are connected through signals (signals). A complete system consists of a plurality of modules, each containing one or more processes and methods, the processes operating in parallel and communicating with each other via signals. Clock is a special signal used to control timing and synchronize processes during simulation. The design method based on SystemC supports designers to model on different levels, reduces code amount and workload, provides higher working efficiency, and can simulate more efficiently and quickly compared with the traditional method.
Disclosure of Invention
In order to solve the problems in the prior art, a GPU chip-oriented rendering output unit performance simulation method is proposed, which includes the following steps:
1) building a performance simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) the port conversion of the rendering output unit in the performance simulation platform only converts the external transaction-level port into a hardware signal-level port. Embedding a rendering output RTL unit into port conversion of a rendering output unit;
3) the input and output time sequences of the rendering output RTL unit are collected through the port conversion of the rendering output unit, the performance efficiency of the rendering output RTL unit is counted, and the purpose of performance simulation verification of the rendering output unit is achieved.
Preferably, the method for implementing conversion into the hardware signal level port includes: and the port of the rendering output unit converts the input transaction of the monitoring sampling rasterization unit, and converts the content of the transaction into hardware signal high-low level drive taking a clock period as a unit according to the read-write attribute of the transaction.
Preferably, the method for realizing the conversion from the embedding of the rendering output RTL unit into the port of the rendering output unit comprises the following steps: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
Preferably, the method for implementing performance simulation on the rendering output RTL unit is as follows:
and the rasterization unit sends the fragment metadata to a GPU chip, the port of the rendering output unit is converted, the received data is sent to the rendering output RTL unit, and meanwhile, the signal output of the rendering output RTL unit is monitored and counted, so that the purpose of simulation verification of the performance of the rendering output unit is achieved.
The invention also provides a GPU chip-oriented rendering output unit performance simulation platform, which comprises a rendering output unit port conversion unit, a rendering output RTL unit, a rasterization unit, a color buffer area unit and a depth buffer area unit;
the port of the rendering output unit receives the fragment metadata sent by the rasterization unit in a conversion way and transmits the fragment metadata to the rendering output RTL unit through the signal level port;
the port of the rendering output unit receives the output of the rendering output RTL unit in a conversion way, counts the data volume and the simulation time, and calculates the performance of the rendering output unit;
the rendering output RTL unit receives the chip metadata from the port conversion of the rendering output unit, performs hardware register transmission level operation and outputs the result to the port conversion of the rendering output unit;
the rasterization unit sends the rasterized fragment data to a rendering output unit for port conversion;
the color buffer unit receives and stores the output of the port conversion of the rendering output unit;
the depth buffer unit receives and stores the output of the port conversion of the rendering output unit;
preferably, the simulation platform comprises a rendering output unit port conversion unit, a rendering output RTL unit, a rasterization unit, a color buffer unit and a depth buffer unit.
The port conversion of the rendering output unit comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit, and the ports are communicated through a RasterIf interface;
the port conversion of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit, and the ports are communicated through a colorBufIf interface;
the port conversion of the rendering output unit comprises a depthBufPort port, the port is connected with a depthBufExport port of the depth buffer unit, and the ports are communicated through a depthBufIf interface;
the rasterization unit comprises a rasterPort port, the rasterPort port is connected with a rasterExport port converted by the rendering output unit port, and the ports are communicated through a RasterIf interface;
the color buffer unit comprises a colorBufExport port, the port is connected with a colorBufPort port converted by a rendering output unit port, and the ports are communicated through a colorBufIf interface;
the depth buffer area unit comprises a depthBufExport port, the depthBufPort is connected with a depthBufPort port converted by a rendering output unit port, and the ports are communicated through a depthBufIf interface.
In conclusion, the beneficial technical effects of the invention are as follows:
1. TLM modeling is carried out on the performance of the GPU according to module division by adopting SystemC, TLM modules of any level in the GPU can be replaced by RTL codes, so that the actual working performance of the RTL is tested in a simulation mode, and whether the performance of the RTL codes meets the requirements or not can be judged by referring to performance indexes of corresponding modules in a virtual prototype;
2. the conventional work of testing the RTL performance in the FPGA stage is advanced to the virtual prototype verification stage, so that the project progress is accelerated, and the cost of later-stage iteration of the project is reduced;
drawings
FIG. 1 is a rendering output unit performance simulation platform of a GPU chip according to the present invention.
Wherein: 1. port conversion of a rendering output unit; 2. a rendering output RTL unit; 1-1, a rasterization unit; 3. a color buffer unit; 4. a depth buffer unit.
Detailed Description
The invention will now be described in detail with reference to the drawings attached hereto.
In an embodiment of the present invention, a GPU chip-oriented rendering output unit performance simulation method is provided, the method including the steps of:
1) building a performance simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) the port conversion of the rendering output unit in the performance simulation platform only converts the external transaction-level port into a hardware signal-level port. Embedding a rendering output RTL unit into port conversion of a rendering output unit;
3) the input and output time sequences of the rendering output RTL unit are collected through the port conversion of the rendering output unit, the performance efficiency of the rendering output RTL unit is counted, and the purpose of performance simulation verification of the rendering output unit is achieved.
In one embodiment, the method for implementing the conversion into the hardware signal level port is as follows: and the port of the rendering output unit converts the input transaction of the monitoring sampling rasterization unit, and converts the content of the transaction into hardware signal high-low level drive taking a clock period as a unit according to the read-write attribute of the transaction.
In one embodiment, the method for implementing port translation from embedding of the rendering output RTL unit into the rendering output unit is as follows: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
In one embodiment, the way to perform performance simulation on the rendering output RTL unit is:
and the rasterization unit sends the fragment metadata to a GPU chip, the port of the rendering output unit is converted, the received data is sent to the rendering output RTL unit, and meanwhile, the signal output of the rendering output RTL unit is monitored and counted, so that the purpose of simulation verification of the performance of the rendering output unit is achieved.
In one embodiment, a GPU chip-oriented rendering output unit performance simulation platform is provided, which includes a rendering output unit port conversion 1, a rendering output RTL unit 1-1, a rasterization unit 2, a color buffer unit 3, and a depth buffer unit 4, and the method further includes:
the port conversion 1 of the rendering output unit receives the fragment metadata sent by the rasterization unit and transmits the fragment metadata to the rendering output RTL unit 1-1 through a signal level port;
the port conversion 1 of the rendering output unit receives the output of the rendering output RTL unit 1-1, counts the data volume and the simulation time, and calculates the performance of the rendering output unit;
the rendering output RTL unit 1-1 receives the chip metadata from the rendering output unit port conversion 1, performs hardware register transmission level operation, and outputs the result to the rendering output unit port conversion 1;
the rasterization unit 2 sends the rasterized fragment data to the rendering output unit port conversion 1;
the color buffer unit 3 receives and stores the output of the port conversion 1 of the rendering output unit;
the depth buffer unit 3 receives and stores the output of the port conversion 1 of the rendering output unit;
in one embodiment, the emulation platform includes a render output unit port conversion 1, a render output RTL unit 1-1, a rasterization unit 2, a color buffer unit 3, and a depth buffer unit 4.
The port conversion 1 of the rendering output unit comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit 2, and the ports are communicated through a RasterIf interface;
the port conversion 1 of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit 3, and the ports communicate with each other through a colorBufIf interface;
the port conversion 1 of the rendering output unit comprises a depthBufPort port, the port is connected with a depthBufExport of the depth buffer unit 4, and the ports communicate with each other through a depthBufIf interface;
the rasterization unit 2 comprises a rasterPort port, the rasterPort port is connected with a rasterExport port of the rendering output unit port conversion 1, and the ports communicate with each other through a RasterIf interface;
the color buffer unit 3 comprises a colorBufExport port, the port is connected with a colorBufPort port of the rendering output unit port conversion 1, and the ports communicate with each other through a colorBufIf interface;
the depth buffer unit 4 includes a depthBufExport port, which is connected to a depthBufPort of the rendering output unit port conversion 1, and the ports communicate with each other through a DepthBufIf interface.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A GPU chip-oriented rendering output unit performance simulation method is characterized by comprising the following steps:
1) building a performance simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) the port conversion of the rendering output unit in the performance simulation platform only converts the external transaction-level port into a hardware signal-level port. Embedding a rendering output RTL unit into port conversion of a rendering output unit;
3) the input and output time sequences of the rendering output RTL unit are collected through the port conversion of the rendering output unit, the performance efficiency of the rendering output RTL unit is counted, and the purpose of performance simulation verification of the rendering output unit is achieved.
2. The method for simulating the performance of the rendering output unit facing the GPU chip as claimed in claim 1, wherein the method for converting the rendering output unit into the hardware signal level port comprises the following steps: and the port of the rendering output unit converts the input transaction of the monitoring sampling rasterization unit, and converts the content of the transaction into hardware signal high-low level drive taking a clock period as a unit according to the read-write attribute of the transaction.
3. The GPU chip-oriented rendering output unit performance simulation method of claim 2, wherein: the method for realizing the conversion from embedding the rendering output RTL unit into the port of the rendering output unit comprises the following steps: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
4. The GPU chip-oriented rendering output unit performance simulation method of claim 3, wherein: the method for realizing performance simulation of the rendering output RTL unit comprises the following steps:
and the rasterization unit sends the fragment metadata to a GPU chip, the port of the rendering output unit is converted, the received data is sent to the rendering output RTL unit, and meanwhile, the signal output of the rendering output RTL unit is monitored and counted, so that the purpose of simulation verification of the performance of the rendering output unit is achieved.
5. A GPU chip-oriented rendering output unit performance simulation platform is characterized in that: the simulation platform comprises a rendering output unit port conversion unit (1), a rendering output RTL unit (1-1), a rasterization unit (2), a color buffer unit (3) and a depth buffer unit (4);
the port conversion (1) of the rendering output unit is used for receiving the fragment metadata sent by the rasterization unit and transmitting the fragment metadata to the rendering output RTL unit (1-1) through a signal level port;
the port conversion (1) of the rendering output unit is used for receiving the output of the rendering output RTL unit (1-1), counting the data volume and the simulation time and calculating the performance of the rendering output unit;
the rendering output RTL unit (1-1) is used for receiving the fragment metadata from the rendering output unit port conversion (1), performing hardware register transmission level operation and outputting a result to the rendering output unit port conversion (1);
the rasterization unit (2) is used for sending the rasterized fragment data to the rendering output unit for port conversion (1);
the color buffer unit (3) is used for receiving and storing the output of the port conversion (1) of the rendering output unit;
and the depth buffer unit (3) is used for receiving and storing the output of the port conversion (1) of the rendering output unit.
6. The GPU chip-oriented host interface unit performance simulation platform of claim 5, wherein:
the port conversion (1) of the rendering output unit comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit (2), and the ports are communicated through a RasterIf interface;
the port conversion (1) of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit (3), and the ports are communicated through a colorBufIf interface;
the port conversion (1) of the rendering output unit comprises a depthBufPort port, the port is connected with a depthBufExport port of the depth buffer unit (4), and the ports are communicated through a depthBufIf interface;
the rasterization unit (2) comprises a rasterPort port, the rasterPort port is connected with a rasterExport port of the rendering output unit port conversion unit (1), and the ports are communicated through a RasterIf interface;
the color buffer unit (3) comprises a colorBufExport port, the port is connected with a colorBufPort port of the rendering output unit port conversion (1), and the ports are communicated through a colorBufIf interface;
the depth buffer area unit (4) comprises a depthBufExport port, the port is connected with a depthBufPort port of the rendering output unit port conversion (1), and the ports are communicated through a depthBufIf interface.
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