CN111062173A - GPU chip-oriented rendering output unit function simulation method and platform - Google Patents
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Abstract
The invention relates to the technical field of computer hardware verification, in particular to a rendering output unit function simulation method and platform for a GPU chip. The method comprises the steps of building a GPU chip-oriented rendering output unit function simulation platform, converting a TLM transaction-level port into a hardware signal-level port through rendering output unit port conversion, embedding a rendering output RTL unit into the rendering output unit port conversion, and performing module-level and system-level function simulation on the rendering output unit. Therefore, the problem that two simulation environments of a rendering output unit module level and a system level are not uniform is solved, the reusability of the simulation environments is improved, and RTL development and verification work of a GPU chip is accelerated.
Description
Technical Field
The invention relates to the technical field of computer hardware verification, in particular to a GPU (graphics processing unit) chip-oriented rendering output unit function simulation method and platform.
Background
With the increasing of graphics applications, it is difficult for early solutions of graphics rendering by CPU alone to meet the graphics Processing requirements of performance and technology growth, and Graphics Processing Units (GPUs) have come into play. From 1999, the first GPU product released by Nvidia to date, the development of GPU technology mainly goes through the fixed function pipeline stage, the separation stainer architecture stage, and the unified stainer architecture stage, the graphics processing capability of the GPU technology is continuously improved, and the application field is gradually expanded from the initial graphics drawing to the general computing field. The GPU pipeline has high speed, parallel characteristics and flexible programmability, and provides a good running platform for graphic processing and general parallel computing.
For the software/hardware architecture and design of a very large scale integrated circuit chip like a GPU, how to complete the crossover from the traditional specification document to the implementation of a hardware RTL circuit becomes an important and urgent problem in the engineering practice process. In order to shorten the huge gap from the system architecture document to the realization of the hardware RTL circuit, the function and the architecture of the whole circuit system must be described by adopting a high-level modeling language between the two stages, and the function and the architecture cannot be trapped in the complicated signal sequence and gate circuit of the hardware circuit.
The Transaction Level Models (TLM) are higher abstraction levels than the RTL Level, and at this Level, the executable specification of hardware can be quickly established and the system model can be quickly created according to the initial functional specification of the system. By adding timing details into the system, the performance of the system can be evaluated, and the structure of the system can be explored.
SystemC is a C + + based modeling platform organized and established and maintained by OSCI (open SystemC initiative), is completely written by C + + language, consists of a C + + class library and a simulation kernel which are well designed, supports hardware modeling and simulation on various abstraction levels such as a gate level, an RTL level and a system level, and is open to source codes. The SystemC supports hardware/software collaborative design, can describe the structure of a complex system consisting of hardware and software, and supports the description of hardware, software and interfaces in a C + + environment. The system C can realize the abstraction of the functional module, the communication module, the software module and the hardware module on various system level levels, and the concepts of data type description, clock and delay of the introduced port and signal are just based on the idea of unifying the description of the software and the hardware into a modeling language. The system C can be used for quickly and effectively establishing an accurate model of a software algorithm, a hardware system structure, an SoC interface and a system-level design, and simulating, verifying and optimizing the design (the simulation speed is generally 10-100 times that of VHDL or Verilog modeling by using the system C). The most basic structural unit of the SystemC is a module (module), which may contain other modules or processes (processes) and methods (methods), and the processes are like functions in C language to realize a certain behavior. The module communicates with other modules through interfaces (ports), and the interfaces are connected through signals (signals). A complete system consists of a plurality of modules, each containing one or more processes and methods, the processes operating in parallel and communicating with each other via signals. Clock is a special signal used to control timing and synchronize processes during simulation. The design method based on SystemC supports designers to model on different levels, reduces code amount and workload, provides higher working efficiency, and can simulate more efficiently and quickly compared with the traditional method.
Disclosure of Invention
Based on the problems in the background art, the rendering output unit function simulation method and the rendering output unit function simulation platform for the GPU chip can rapidly obtain the RTL module level and the system level simulation platform of the GPU with the minimum development cost by means of the TLM virtual prototype platform of the GPU, solve the problem that the module level and the system level RTL simulation platform of the GPU are not easy to build, and can rapidly perform RTL simulation on the GPU module level and the system level. Therefore, work among software personnel, hardware module RTL developers and simulation verification personnel can be coordinated conveniently, and unnecessary iteration is reduced.
The invention provides a GPU chip-oriented rendering output unit function simulation method and platform, wherein the method comprises the following steps: the method comprises the following steps:
1) building a functional simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) and the port of the rendering output unit in the functional simulation platform is converted and reserved with an external transaction-level port, and the external transaction-level port is converted into a hardware signal-level port. Embedding a rendering output TLM unit and a rendering output RTL unit into port conversion of a rendering output unit;
3) and comparing output results of the rendering output TLM unit and the rendering output RTL unit through function simulation, thereby achieving the purpose of function simulation verification of the rendering output unit.
Preferably, the method for implementing conversion into the hardware signal level port includes: and the port of the rendering output unit converts and monitors the input transaction of the external rasterization unit, and converts the content of the transaction into hardware signal high-low level driving which takes a clock period as a unit according to the read-write attribute of the transaction.
Preferably, the method for realizing the conversion from the embedding of the rendering output RTL unit into the port of the rendering output unit comprises the following steps: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
Preferably, the method for implementing the function simulation of the rendering output RTL unit is as follows:
the rasterization unit sends the rasterized thick fragment metadata to a GPU chip for port conversion, and the port conversion of the rendering output unit sends the received data to a rendering output TLM unit and a rendering output RTL unit at the same time; meanwhile, the port of the rendering output unit converts and monitors the outputs of the rendering output TLM unit and the rendering output RTL unit, and the outputs of the two are compared, so that the purpose of simulation verification of the functions of the rendering output unit is achieved.
The invention also provides a GPU chip-oriented rendering output unit function simulation platform, which comprises a rendering output unit port conversion unit, a rendering output RTL unit, a rendering output TLM unit, a rasterization unit, a color buffer unit and a depth buffer unit, and the method also comprises the following steps:
the port of the rendering output unit receives the fragment metadata sent by the rasterization unit in a conversion way and transmits the fragment metadata to the rendering output RTL unit through the signal level port;
the port of the rendering output unit is used for converting and receiving the fragment metadata sent by the rasterization unit and transmitting the fragment metadata to the rendering output TLM unit through the transaction-level port;
and the port of the rendering output unit receives the outputs of the rendering output RTL unit and the rendering output TLM unit, and compares the results. If the results are consistent, the results are transmitted to a color buffer unit and a depth buffer unit; if the results are not consistent, terminating the simulation;
the rendering output RTL unit receives the chip metadata from the port conversion of the rendering output unit, performs hardware register transmission level operation and outputs the result to the port conversion of the rendering output unit;
the rendering output TLM unit receives the chip metadata from the port conversion of the rendering output unit, performs hardware transaction-level operation and outputs the result to the port conversion of the rendering output unit;
the rasterization unit sends the rasterized fragment data to a rendering output unit for port conversion;
the color buffer unit receives and stores the output of the port conversion of the rendering output unit;
the depth buffer unit receives and stores the output of the port conversion of the rendering output unit;
preferably, the port conversion of the rendering output unit comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit, and the ports communicate with each other through a RasterIf interface;
the port conversion of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit, and the ports are communicated through a colorBufIf interface;
the port conversion of the rendering output unit comprises a depthBufPort port, the port is connected with a depthBufExport port of the depth buffer unit, and the ports are communicated through a depthBufIf interface;
the rasterization unit comprises a rasterPort port, the rasterPort port is connected with a rasterExport port converted by the rendering output unit port, and the ports are communicated through a RasterIf interface;
the color buffer unit comprises a colorBufExport port, the port is connected with a colorBufPort port converted by a rendering output unit port, and the ports are communicated through a colorBufIf interface;
the depth buffer area unit comprises a depthBufExport port, the depthBufPort is connected with a depthBufPort port converted by a rendering output unit port, and the ports are communicated through a depthBufIf interface.
In conclusion, the beneficial technical effects of the invention are as follows:
1. TLM modeling is carried out on the functions of the GPU according to module division by adopting SystemC, and TLM modules of any scale and any level in the GPU can be replaced by RTL codes, so that the RTL module simulation platform of the GPU can multiplex a GPU virtual prototype platform;
2. TLM modeling is carried out on functions of the GPU according to module division by adopting SystemC, and the TLM model of the GPU can be entirely replaced by RTL codes, so that the RTL system simulation platform of the GPU is reused for a GPU virtual prototype platform.
Drawings
FIG. 1 is a functional simulation platform of a rendering output unit of a GPU chip according to the present invention.
Wherein: 1. port conversion of a rendering output unit; 1-1, rendering output RTL unit; 1-2, a render output TLM unit; 2. a rasterization unit; 3. a color buffer unit; 4. a depth buffer unit.
Detailed Description
The invention will now be described in detail with reference to the drawings attached hereto.
In one embodiment of the invention, a GPU chip-oriented rendering output unit function simulation method and platform are provided, and the method comprises the following steps:
1) building a functional simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) and the port of the rendering output unit in the functional simulation platform is converted and reserved with an external transaction-level port, and the external transaction-level port is converted into a hardware signal-level port. Embedding a rendering output TLM unit and a rendering output RTL unit into port conversion of a rendering output unit;
3) and comparing output results of the rendering output TLM unit and the rendering output RTL unit through function simulation, thereby achieving the purpose of function simulation verification of the rendering output unit.
In one embodiment, the method for implementing the conversion into the hardware signal level port is as follows: and the port of the rendering output unit converts and monitors the input transaction of the external rasterization unit, and converts the content of the transaction into hardware signal high-low level driving which takes a clock period as a unit according to the read-write attribute of the transaction.
In one embodiment, the method for realizing the port conversion from embedding the rendering output RTL unit into the rendering output unit comprises the following steps: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
In one embodiment, the way of implementing the function simulation of the rendering output RTL unit is as follows:
the rasterization unit sends the rasterized thick fragment metadata to a GPU chip for port conversion, and the port conversion of the rendering output unit sends the received data to a rendering output TLM unit and a rendering output RTL unit at the same time; meanwhile, the port of the rendering output unit converts and monitors the outputs of the rendering output TLM unit and the rendering output RTL unit, and the outputs of the two are compared, so that the purpose of simulation verification of the functions of the rendering output unit is achieved.
In one embodiment, the invention further provides a simulation platform for the functions of the GPU-oriented rendering output unit, wherein the simulation platform comprises a rendering output unit port conversion 1, a rendering output RTL unit 1-1, a rendering output TLM unit 1-2, a rasterization unit 2, a color buffer unit 3 and a depth buffer unit 4,
a rendering output unit port conversion 1 receives the fragment metadata sent by the rasterization unit and transmits the fragment metadata to a rendering output RTL unit 1-1 through a signal level port;
a port conversion 1 of a rendering output unit receives the fragment metadata sent by the rasterization unit and transmits the fragment metadata to a rendering output TLM unit 1-2 through a transaction-level port;
the port conversion 1 of the rendering output unit receives the outputs of the rendering output RTL unit 1-1 and the rendering output TLM unit 1-2, and the results are compared. If the results are consistent, the results are passed to the color buffer unit 3 and the depth buffer unit 4; if the results are not consistent, terminating the simulation;
the rendering output RTL unit 1-1 receives the fragment metadata from the rendering output unit port conversion 1, performs hardware register transmission level operation, and outputs the result to the rendering output unit port conversion 1;
the rendering output TLM unit 1-2 receives the fragment metadata from the rendering output unit port conversion 1, performs hardware transaction-level operation, and outputs the result to the rendering output unit port conversion 1;
the rasterization unit 2 sends the rasterized fragment data to the rendering output unit port conversion 1;
the color buffer unit 3 receives and stores the output of the port conversion 1 of the rendering output unit;
the depth buffer unit 3 receives and stores the output of the port conversion 1 of the rendering output unit;
in one embodiment, the emulation platform includes a render output unit port conversion 1, a render output RTL unit 1-1, a render output TLM unit 1-2, a rasterization unit 2, a color buffer unit 3, and a depth buffer unit 4.
The rendering output unit port conversion 1 comprises a rasterExport port, the ports are connected with a rasterPort port of the rasterization unit 2, and the ports communicate with each other through a RasterIf interface;
the port conversion 1 of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit 3, and the ports communicate with each other through a colorBufIf interface;
the rendering output unit port conversion 1 comprises a depthBufPort port, the port is connected with a depthBufExport port of the depth buffer unit 4, and the ports communicate with each other through a depthBufIf interface;
the rasterization unit 2 comprises a rasterPort port, the rasterPort port is connected with a rasterExport port of the rendering output unit port conversion 1, and the ports communicate with each other through a RasterIf interface;
the color buffer unit 3 comprises a colorBufExport port, the port is connected with the colorBufPort port of the rendering output unit port conversion 1, and the ports communicate with each other through a colorBufIf interface;
the depth buffer unit 4 includes a depthBufExport port, which is connected to a depthBufPort of the rendering output unit port conversion 1, and the ports communicate with each other through a DepthBufIf interface.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A GPU chip-oriented rendering output unit function simulation method is characterized by comprising the following steps:
1) building a functional simulation platform for a GPU-oriented chip rendering output unit by adopting a SystemC language and a transaction-level modeling TLM method;
2) and the port of the rendering output unit in the functional simulation platform is converted and reserved with an external transaction-level port, and the external transaction-level port is converted into a hardware signal-level port. Embedding a rendering output TLM unit and a rendering output RTL unit into port conversion of a rendering output unit;
3) and comparing output results of the rendering output TLM unit and the rendering output RTL unit through function simulation, thereby achieving the purpose of function simulation verification of the rendering output unit.
2. The GPU chip-oriented rendering output unit function simulation method of claim 1, wherein the method for converting the rendering output unit function into the hardware signal level port comprises the following steps: and the port of the rendering output unit converts and monitors the input transaction of the external rasterization unit, and converts the content of the transaction into hardware signal high-low level driving which takes a clock period as a unit according to the read-write attribute of the transaction.
3. The GPU chip-oriented rendering output unit function simulation method of claim 2, wherein: the method for realizing the conversion from embedding the rendering output RTL unit into the port of the rendering output unit comprises the following steps: and embedding the rendering output RTL unit into the port conversion of the rendering output unit through signal docking.
4. The GPU chip-oriented rendering output unit function simulation method of claim 3, wherein: the method for realizing the function simulation of the rendering output RTL unit comprises the following steps:
the rasterization unit sends the rasterized thick fragment metadata to a GPU chip for port conversion, and the port conversion of the rendering output unit sends the received data to a rendering output TLM unit and a rendering output RTL unit at the same time; meanwhile, the port of the rendering output unit converts and monitors the outputs of the rendering output TLM unit and the rendering output RTL unit, and the outputs of the two are compared, so that the purpose of simulation verification of the functions of the rendering output unit is achieved.
5. The utility model provides a render output unit function simulation platform towards GPU chip which characterized in that: the simulation platform comprises a rendering output unit port conversion unit (1), a rendering output RTL unit (1-1), a rendering output TLM unit (1-2), a rasterization unit (2), a color buffer unit (3) and a depth buffer unit (4);
the port conversion (1) of the rendering output unit is used for receiving the fragment metadata sent by the rasterization unit and transmitting the fragment metadata to the rendering output RTL unit (1-1) through a signal level port;
the port conversion (1) of the rendering output unit is used for receiving the fragment metadata sent by the rasterization unit and transmitting the fragment metadata to the rendering output TLM unit (1-2) through a transaction-level port;
and the port conversion (1) of the rendering output unit is used for receiving the outputs of the rendering output RTL unit (1-1) and the rendering output TLM unit (1-2) and comparing the results. If the results are consistent, the results are transmitted to a color buffer unit (3) and a depth buffer unit (4); if the results are not consistent, terminating the simulation;
the rendering output RTL unit (1-1) is used for receiving the fragment metadata from the rendering output unit port conversion (1), performing hardware register transmission level operation and outputting a result to the rendering output unit port conversion (1);
the rendering output TLM unit (1-2) is used for receiving the fragment metadata from the rendering output unit port conversion (1), performing hardware transaction-level operation and outputting a result to the rendering output unit port conversion (1);
the rasterization unit (2) is used for sending the rasterized fragment data to the rendering output unit for port conversion (1);
the color buffer unit (3) is used for receiving and storing the output of the port conversion (1) of the rendering output unit;
and the depth buffer unit (3) is used for receiving and storing the output of the port conversion (1) of the rendering output unit.
6. The GPU chip-oriented rendering output unit function emulation real platform of claim 5, wherein:
the port conversion (1) of the rendering output unit comprises a rasterExport port, the port is connected with a rasterPort port of the rasterization unit (2), and the ports are communicated through a RasterIf interface;
the port conversion (1) of the rendering output unit comprises a colorBufPort port, the port is connected with a colorBufExport port of the color buffer unit (3), and the ports are communicated through a colorBufIf interface;
the port conversion (1) of the rendering output unit comprises a depthBufPort port, the port is connected with a depthBufExport port of the depth buffer unit (4), and the ports are communicated through a depthBufIf interface;
the rasterization unit (2) comprises a rasterPort port, the rasterPort port is connected with a rasterExport port of the rendering output unit port conversion unit (1), and the ports are communicated through a RasterIf interface;
the color buffer unit (3) comprises a colorBufExport port, the port is connected with a colorBufPort port of the rendering output unit port conversion (1), and the ports are communicated through a colorBufIf interface;
the depth buffer area unit (4) comprises a depthBufExport port, the port is connected with a depthBufPort port of the rendering output unit port conversion (1), and the ports are communicated through a depthBufIf interface.
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