CN116933699A - Method, electronic device and storage medium for generating and storing waveform data in a circuit simulation process - Google Patents

Abstract

The present disclosure relates to a method for generating and storing waveform data in a circuit simulation process. The method comprises the following steps: a circuit file representing a circuit is compiled to generate a hierarchical dataset for the circuit in a compilation database. The method further includes simulating the circuit based on the hierarchical dataset and the circuit file to selectively generate a target waveform dataset in the waveform database. The waveform database is configured to provide an interface to access the compiled database. The method further includes storing at least a portion of the target waveform dataset in a memory. Since the dedicated compilation database is provided to store the hierarchical data set in the compilation stage, and the compilation database can be accessed through the dedicated waveform database in the simulation stage to selectively generate corresponding waveform data and selectively store the waveform data during the simulation based on the digital circuit traffic characteristics, the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be correspondingly reduced.

Description

Method, electronic device and storage medium for generating and storing waveform data in a circuit simulation process

Technical Field

The present disclosure relates to the field of electronics, and more particularly to methods, electronic devices, computer programs, and storage media for generating and storing waveform data in a circuit simulation process.

Background

In the course of circuit design, it is often necessary to verify the correctness of the circuit design. In some cases, it is desirable to use a digital circuit simulator to satisfy the function of simulation debugging. To meet the need for simulation debugging, it is often necessary to generate some accurate and efficient waveform signals. The generation of waveforms requires monitoring the relevant signals during the simulation process and preserving the change in their values, which will produce a large number of parameter passes and event records, greatly affecting the simulation performance.

The institute of electrical and electronics engineers (institute of electrical and electronics engineers, IEEE) defines files in the format of value change transfer (value change dump, VCD) in the IEEE1364 standard. The VCD file includes header information, predefined variables, and variation information of variable values. Since the VCD file contains information of the change of the signal, which corresponds to the information of the entire simulation recorded, it can reproduce the simulation with this file, i.e., can display waveforms. In addition, since the VCD file is part of the Verilog hardware description language standard, all Verilog simulators need to be able to do this, as well as allow the user to save (dump) the VCD file in the Verilog code via system functions.

In some conventional schemes, effective information extraction is performed for VCD files, removing redundant information. This is similar to huffman encoding of VCD data. Therefore, the data file size will be reduced to some extent, but in the actual simulation process, the actual waveform data size is still relatively large due to the limited encoding and decoding capability. Furthermore, the simulation time is also long.

Disclosure of Invention

In light of the foregoing, embodiments of the present disclosure are directed to a method, an electronic device, a computer program, and a storage medium for generating and storing waveform data in a circuit simulation process for reducing the amount of data and simulation time generated by the circuit simulation.

According to a first aspect of the present disclosure, a method for generating and storing waveform data in a circuit simulation process is provided. The method comprises the following steps: a circuit file representing a circuit is compiled to generate a hierarchical (hierarchy) dataset for the circuit in a compilation database, the hierarchical dataset being associated with a plurality of signals at a plurality of nodes in the circuit. The method further includes simulating the circuit based on the hierarchical dataset and the circuit file to selectively generate a target waveform dataset in the waveform database. The waveform database is configured to provide an interface to access the compiled database. The method further includes storing at least a portion of the target waveform dataset in a memory. Since a dedicated compilation database is provided to store the hierarchical data set at the compilation stage, and the compilation database can be accessed by the dedicated waveform database to selectively generate corresponding waveform data based on the digital circuit traffic characteristics and further selectively store the waveform data at the simulation stage, the amount of waveform data generated and saved during the simulation process can be reduced and the simulation time can be reduced accordingly. Compared with the conventional digital simulation tool which directly performs operations such as signal connection relation construction, waveform information recording and the like in the simulation stage scheduling execution process and full waveform file output, the technical scheme of the present disclosure can greatly reduce the file size to be saved before waveform file compression and storage through preprocessing in the compiling stage. The feature extraction in combination with the service level can be implemented to remove redundant information during the compilation phase. On the premise of avoiding the loss of effective information, the size of a waveform file is reduced from the source before the compression algorithm is performed, so that the pressure of encoding and decoding on simulation time is reduced and the simulation time is correspondingly reduced. In one implementation of the first aspect, the method further includes storing all data of the target waveform dataset in a memory.

In one implementation of the first aspect, the circuit file for representing the circuit includes a register transfer level description file. In one implementation of the first aspect, the hierarchical data set is organized in a hierarchical tree form and the hierarchical data set includes at least one of: sequence information for representing serialization of a plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing the hierarchical data sets in the form of a hierarchical tree, it is possible to facilitate finding, modifying, and saving hierarchical data based on various attributes (such as driving relationships, load relationships, memory addresses, module calls, etc.), and accordingly, to facilitate selective signal generation and storage.

In one implementation of the first aspect, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. Generating a hierarchical data set for a circuit in a compilation database includes: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal.

In one implementation of the first aspect, selectively generating the target waveform dataset in the waveform database includes: determining a target signal set based on the hierarchical mapping relationship, the target signal set including the first signal and the target signal set not including the second signal; based on the determined set of target signals, the circuit is simulated to selectively generate a set of target waveform data in the waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal. By establishing a hierarchical mapping relationship between a plurality of associated signals, a relationship of another signal may be determined based on a single signal, which may avoid computation and storage of waveform datasets for the plurality of signals, thereby further reducing simulation time and reducing storage capacity of the simulated signals.

In one implementation manner of the first aspect, the method further includes: a storage time indication for a target signal is received. Storing at least a portion of the target waveform dataset in a memory includes: a data portion of a time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set is stored in the memory. By setting the time period in which the waveform needs to be processed and saved by the user, the waveform data processing amount and time can be further reduced compared to the simulation and data storage of the entire period.

In one implementation of the first aspect, the plurality of signals includes a third signal. Selectively generating the target waveform dataset in the waveform database includes: based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in the waveform database, wherein the simulated waveform data for the third signal includes spur data. In one implementation of the first aspect, the spur data comprises a plurality of spur values for the third signal within a unit time period; and storing at least a portion of the target waveform dataset in the memory comprises: a plurality of spur values are stored in a memory in chronological order. By providing a glitch recording function, more accurate and detailed waveform information can be provided to circuit designers to facilitate determining the accuracy of the circuit design.

In one implementation of the first aspect, storing the plurality of spur values in time-sequentially in the memory includes: determining whether adjacent ones of the plurality of spur values are the same; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. By combining multiple adjacent spur values into a single spur value, the amount of waveform data can be further reduced.

In one implementation manner of the first aspect, the method further includes: based on the user input, the hierarchical dataset is adjusted. By adjusting the hierarchical data set, the designer may be given flexibility in circuit verification. In addition, in the case where the designer adjusts the hierarchical data set to retain only the signal of interest to himself, the time of circuit simulation and the data amount of the waveform signal can be further reduced.

According to a second aspect of the present disclosure, there is provided a computer-readable storage medium storing a plurality of programs. The plurality of programs are configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method of the first aspect.

According to a third aspect of the present disclosure, a computer program product is provided. The computer program product comprises a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method of the first aspect.

According to a fourth aspect of the present disclosure, an electronic device is provided. An electronic device includes: one or more processors; a memory comprising computer instructions that, when executed by one or more processors of an electronic device, cause the electronic device to perform the method of the first aspect.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a compiling unit, a simulation unit and a storage unit. The compiling unit is configured to compile a circuit file representing the circuit to generate a hierarchical data set for the circuit in a compiling database, the hierarchical data set being associated with a plurality of signals at a plurality of nodes in the circuit. The simulation unit is configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database configured to access the compiled database. The storage unit is configured to store at least a portion of the target waveform dataset in a memory. Since the dedicated compilation database is provided to store the hierarchical data set in the compilation stage, and the compilation database can be accessed through the dedicated waveform database in the simulation stage to selectively generate corresponding waveform data and selectively store the waveform data during the simulation based on the digital circuit traffic characteristics, the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be correspondingly reduced. Compared with the conventional digital simulation tool which directly performs operations such as signal connection relation construction, waveform information recording and the like in the simulation stage scheduling execution process and full waveform file output, the waveform file size to be saved can be greatly reduced before waveform file compression and storage by preprocessing in the compiling stage. The feature extraction in combination with the service level can be implemented to remove redundant information during the compilation phase. On the premise of avoiding the loss of effective information, the size of a waveform file is reduced from the source before the compression algorithm is performed, so that the pressure of encoding and decoding on simulation time is reduced and the simulation time is correspondingly reduced.

In one implementation of the fifth aspect, the circuit file for representing the circuit includes a register transfer level description file. In one implementation of the fifth aspect, the hierarchical data set is organized in a hierarchical tree form and the hierarchical data set includes at least one of: sequence information for representing serialization of a plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing the hierarchical data sets in the form of a hierarchical tree, it is possible to facilitate finding, modifying, and saving the hierarchical data based on various attributes (such as driving relationships, load relationships, memory addresses, module calls, etc.), and accordingly, to make selective signal simulation and storage easier.

In one implementation of the fifth aspect, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. The compiling unit is further configured to: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal.

In an implementation manner of the fifth aspect, the simulation unit is further configured to: determining a target signal set based on the hierarchical mapping relationship, the target signal set including the first signal and the target signal set not including the second signal; based on the determined set of target signals, the circuit is simulated to selectively generate a set of target waveform data in the waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal. By establishing a hierarchical mapping relationship between a plurality of associated signals, a relationship of another signal can be determined based on a single signal, which can avoid simulation calculation and storage of the plurality of signals, thereby further reducing simulation time and reducing storage capacity of signal waveforms.

In an implementation manner of the fifth aspect, the electronic device further includes a receiving unit. The receiving unit is configured to receive a storage time indication for the target signal. The memory unit is further configured to: a data portion of a time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set is stored in the memory. By setting the waveforms of the time periods to be simulated and stored by the user, the amount of data and time can be further reduced compared to the simulation and data storage of the entire period.

In one implementation of the fifth aspect, the plurality of signals includes a third signal. The simulation unit is further configured to: based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in the waveform database, wherein the simulated waveform data for the third signal includes spur data.

In one implementation of the fifth aspect, the spur data includes a plurality of spur values for the third signal within a unit time period. The memory unit is further configured to: a plurality of spur values are stored in a memory in chronological order. In an implementation manner of the fifth aspect, the storage unit is further configured to: determining whether adjacent ones of the plurality of spur values are the same; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. By providing a glitch recording function, more accurate and detailed waveform information can be provided to circuit designers to facilitate determining the accuracy of the circuit design.

In an implementation manner of the fifth aspect, the storage unit is further configured to determine whether adjacent burr values of the plurality of burr values are identical; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. By combining multiple adjacent spur values into a single spur value, the amount of waveform data can be further reduced.

In an implementation manner of the fifth aspect, the electronic device further includes an adjustment unit. The adjustment unit is configured to adjust the hierarchical data set based on user input. By adjusting the hierarchical data set, the designer may be given flexibility in circuit verification. In addition, in the case where the designer adjusts the hierarchical data set to retain only the signal waveform of interest to himself, the time and data amount of waveform processing in the circuit simulation process can be further reduced.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

fig. 1 shows a schematic diagram of a conventional circuit simulation process.

Fig. 2 illustrates a circuit simulation schematic according to some embodiments of the present disclosure.

Fig. 3 illustrates a schematic flow diagram of a method for generating and storing waveform data in a circuit simulation process, according to some embodiments of the present disclosure.

Fig. 4 illustrates a schematic diagram of a circuit simulation process, according to some embodiments of the present disclosure.

Fig. 5 illustrates a schematic diagram of glitch signals, according to some embodiments of the present disclosure.

Fig. 6 illustrates a schematic diagram of a signal writing process according to some embodiments of the present disclosure.

Fig. 7 illustrates a schematic diagram of a signal reading process according to some embodiments of the present disclosure.

Fig. 8 illustrates a schematic block diagram of an electronic device, according to some embodiments of the present disclosure.

FIG. 9 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Fig. 1 shows a schematic diagram of a conventional circuit simulation process. At 102, an electronic device, such as a computer, receives a file, such as a register transfer level (register transmit level, RTL) file, for describing or representing a circuit, and compiles the RTL file. At 104, the electronic device performs a simulated run of the compiled file. During the simulation run, the electronics can generate a full-scale waveform 114, i.e., a collection of waveform signals at various nodes in the circuit. At 116, the electronic device may store the full-scale waveform. Optionally, during waveform storage, the electronic device may compress 116 the generated waveform data to generate a dedicated waveform format file, thereby achieving the purpose of reducing the size of the waveform file. In some conventional schemes, in order to pursue an extreme compression ratio, it may even be possible to cause the compressed codec time to greatly affect the simulation performance, e.g., the codec time increases significantly. After storing the waveforms in memory, the electronic device may display the waveforms at 108 at any time in response to designer input.

As described above, in the conventional scheme, the simulation of the circuit does not normally perform processing related to waveform information of signals at the compiling side, but schedules execution processes at the time of simulation run to perform operations of building signal connection relationships, recording waveform information, and the like, and performing waveform file output. This brings about a large degradation of the simulation time. Furthermore, in some conventional schemes, although effective information extraction is performed on waveform files such as VCD files, redundant information is removed, in actual simulation, the actual data amount is relatively large and simulation time is long due to limited codec capability.

In the present disclosure, a dedicated compilation database (compiledatabase) and a waveform database (waveform database) are respectively set on the compiling side and the simulation running side to perform transmission and storage of hierarchical data sets. Since the dedicated compilation database is provided to store the hierarchical data set in the compilation stage, and the compilation database can be accessed through the dedicated waveform database in the simulation stage to selectively generate corresponding waveform data and selectively store the waveform data during the simulation based on the digital circuit traffic characteristics, the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be correspondingly reduced. Compared with the conventional digital simulation tool which directly performs operations such as signal connection relation construction, waveform information recording and the like in the simulation stage scheduling execution process and full waveform file output, the waveform file size to be saved can be greatly reduced before waveform file compression and storage by preprocessing in the compiling stage. The feature extraction in combination with the service level can be implemented to remove redundant information during the compilation phase. On the premise of avoiding the loss of effective information, the size of a waveform file is reduced from the source before the compression algorithm is performed, so that the pressure of encoding and decoding on simulation time is reduced and the simulation time is correspondingly reduced. In one implementation of the first aspect, the method further includes storing all data of the target waveform dataset in a memory.

Fig. 2 illustrates a schematic diagram of a circuit simulation 200, according to some embodiments of the present disclosure. An electronic device with computing capabilities, such as a computer, may receive a file 201, such as an RTL file, describing a circuit, and at 202 the electronic device may compile the file 201. Alternatively, the file 201 may be compiled after a preliminary analysis (parser). It will be appreciated that preliminary analysis is not necessary. In some embodiments, the preliminary analysis may be performed integrally with the compilation. In one embodiment, a specialized compilation database 212 may be provided at the compilation side. The compiled database 212 may be used to store information related to signal waveforms of the circuit to be emulated. In one embodiment, compilation database 212 may store hierarchical data sets. In one embodiment, the hierarchical data set is organized in a hierarchical tree (i.e., a hierarchical tree), and the hierarchical data set includes at least one of: sequence information for representing serialization of a plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. The hierarchical dataset may be used by the Verilog programming language interface (Verilog programming language interface, VPI) to obtain this information when looking back at the signals. This can be used to build hierarchical information of the chip design code when generating the waveform file. In one embodiment, this may select a chip level and select a signal at a certain level for waveform presentation at circuit debug (debug). In one embodiment, compilation database 212 may also provide serialization and de-serialization for signals. For example, the compilation database 212 may serialize a plurality of signals and pass the serialized information to the simulation side. The simulation side may de-serialize the serialized plurality of signals to determine the desired signal.

Specifically, the compilation database 212 may extract relevant information for the hierarchical tree from the construction of abstract syntax trees (abstract syntax tree, AST) and intermediate expressions (intermediate representation, IR) and store the relevant information in the compilation database 212 after serialization of the respective information. Although the hierarchical data sets are organized herein in the form of a hierarchical tree, this is merely illustrative and is not limiting of the scope of the present disclosure. Other forms of data structures may also be used to organize the hierarchical data sets. By organizing the hierarchical data sets in the form of a hierarchical tree, it is possible to facilitate finding, modifying, and saving the hierarchical data based on various attributes (such as driving relationships, load relationships, memory addresses, module calls, etc.), and accordingly, to make selective signal simulation and storage easier. Although described herein in terms of simulation run 204, it is understood that other tool chains 212 (e.g., circuit debuggers) may also access compilation database 212 and/or waveform database 214. The present disclosure is not limited in this regard.

At 204, the electronic device may perform a simulation run on the compiled file. During the simulation run, the electronics can generate waveforms for the various signals and can store the desired target waveform data set in waveform database 214. The waveform database 214 is configured to access the compilation database 212. The compilation database 212 may thus efficiently pass hierarchical data sets to the waveform database 214. Other tool chains 220, such as debuggers, may also read and/or modify the hierarchical data set.

Specifically, during the simulation process, the electronic device may continuously generate target simulation data such as waveform data. The waveform database 214 is configured to provide waveform writing services to record target simulation data in the simulation process into the waveform database 214. The waveform database 214 supports the generation of waveform files in a variety of formats, such as a rapid signal database (fast signal database, FSDB) format, VCD format, and the like. The waveform files in various formats can be converted with each other. After the simulation is completed, the waveform database 214 may provide a read service to read the data in the waveform file generated by the simulation.

In one embodiment, waveform database 214 is further configured to provide an interface to access hierarchical data sets in compilation database 212. The designer can control the dump range through input options based on the hierarchical dataset. Based on the hierarchical data set, the electronic device may dynamically resolve the dump range through an interface, such as a command line interface. Correspondingly, only the target waveform data is saved in the waveform file, and the waveform data of each signal in the complete hierarchy is not required to be saved. Therefore, repeated reading and writing of useless signals can be avoided, and simulation overhead is reduced.

Further, in some embodiments, the waveform database 214 is also configured to hold glitch (glitch) information for a unit time period of the signal. For example, the simulation result changes the value of the same signal a plurality of times within a unit time period, or the simulation result gives a plurality of values to the same signal. In one embodiment, the values may be stored in the waveform database 214 in real time after each domain (region) update. By preserving the glitch information, more accurate and detailed waveform information can be provided to circuit designers to facilitate determining the accuracy of the circuit design.

Fig. 3 illustrates a schematic flow diagram of a method 300 for generating and storing waveform data in a circuit simulation process, according to some embodiments of the present disclosure. It will be appreciated that the various aspects described above with respect to fig. 2 may be selectively adapted for use with the method 300, and thus relevant portions are not described in detail herein. The method 300 may be performed by an electronic device, such as a computer. Alternatively, the method 300 may also be performed by other electronic devices having computing capabilities, which are not described in detail in this disclosure.

At 302, the electronic device compiles a circuit file representing the circuit to generate a hierarchical dataset for the circuit in the compilation database 212, the hierarchical dataset being associated with a plurality of signals at a plurality of nodes in the circuit. In some embodiments, the circuit file used to represent the circuit includes a register transfer level description file. In some embodiments, the hierarchical data set is organized in a hierarchical tree form, and the hierarchical data set includes at least one of: sequence information for representing serialization of a plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing the hierarchical data sets in the form of a hierarchical tree, it is possible to facilitate finding, modifying, and saving the hierarchical data based on various attributes (such as driving relationships, load relationships, memory addresses, module calls, etc.), and accordingly, to make selective signal simulation and storage easier.

Fig. 4 illustrates a schematic diagram of a circuit simulation process 400, according to some embodiments of the present disclosure. At 402, hierarchical data 412 may be generated by compiling a circuit file. In one embodiment, the hierarchy data 412 may be a hierarchy tree as described above. In one embodiment, the hierarchical tree may be intercepted or saved on an AST that results after being parsed. The hierarchical tree may be organized by various parameters and each tree node may include a range of signal sets and individual signal parameters (leaf nodes) within the signal sets. In other words, the hierarchy data 412 may include node data branching by one or more of signal type, transfer path, address allocation, driving relationship, load relationship, and the like.

It will be appreciated that in some embodiments, during compilation, the compiler performs gradual analysis (isolation) of the signal key information during layer-by-layer intermediate expression degradation (IR lower). In addition, the compiler allocates corresponding memory space for all signals. In other embodiments, the compiling database 212 may further implement serialization of signals, and save key information such as driving information, load information, module call relationships, memory address allocation, etc. on corresponding nodes of the tree structure for subsequent searching.

Further, the hierarchical data 412 may be further categorized or branched by one or more of the items described above. For example, for signal types, some or all of the hierarchical data 412 may be further divided into repeating signals, regular signals, combinational logic signals, delayed signals, periodic signals, and the like. For example, the clock signal may be classified as a repeated signal, a regular signal, or a periodic signal. The output signal of the and gate may be categorized as a combinational logic signal. The output of the buffer may be classified as a delayed signal. It will be appreciated that the above divisions are merely illustrative and not limiting on the scope of the present disclosure, and that corresponding divisions may be made as desired.

In some embodiments, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. For example, the first signal may be an input of an inverter and the second signal is an output of the inverter. Therefore, the waveform of the second signal can be obtained by a simple inverting operation with knowledge of the waveform of the first signal. In this case, the hierarchical mapping relationship may be expressed as a negation operation. In another embodiment, the hierarchical data set comprises a hierarchical mapping relationship between the first signal and the fourth signal and the second signal. For example, the first signal and the fourth signal are two inputs of an and gate, and the second signal is an output of the and gate. Therefore, the waveforms of the second signal can be obtained by a simple logical AND operation with knowledge of the waveforms of the first signal and the fourth signal. Although described herein using an inverter and an and gate, the present disclosure is not limited thereto. The case of having a predictable hierarchical mapping relationship between two or more signals is also applicable. In particular, the electronic device may include a model library that includes various signal mapping models, such as signal mapping models for inverters, AND gates, OR gates, and the like. On the other hand, a plurality of circuit modules, logic gate devices and other sub-circuit modules which can be split can be included in the circuit design. Each circuit sub-circuit module may include a respective signal input and output. Thus, generating a hierarchical data set for a circuit in the compilation database 212 includes: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal. For example, signals of modules representing and gate functions in the circuit file are compared with signals for and gates in the model library to determine a hierarchical mapping relationship of signals in the circuit file.

In some embodiments, the method further comprises: based on the user input, the hierarchical dataset is adjusted. During compilation, a user may invoke the interface of compilation database 212 to delete, add, or modify signal nodes of the hierarchical tree. For example, information such as drive information, load information, module call information, address information, etc. may be modified. By adjusting the hierarchical data set, the designer may be given flexibility in circuit verification. In addition, in the case where the designer adjusts the hierarchical data set to retain only the signal of interest to himself, the time of circuit simulation and the data amount of the waveform signal can be further reduced.

Returning to FIG. 3, at 304, the electronic device simulates a circuit to selectively generate a target waveform dataset in the waveform database 214 based on the hierarchical dataset and the circuit file, wherein the waveform database 214 has an interface for accessing the compilation database 212. In some embodiments, waveform database 214 is configured to store and read simulation data, such as simulated waveform data, in a digital chip design. In other embodiments, waveform database 214 is also configured to read waveform data on the debug side. The waveform database 214 may, for example, include three modules: the device comprises a writing module, a reading module and an accessory tool module, wherein each module provides independent functions. In one embodiment, the writing module is configured to transfer waveform data entered by the emulator or accessory tool into a waveform file. The read module is configured to convert the waveform data into memory waveform data and return to the upper layer caller through the API form. The accessory tool module is configured to support the user to input parameters at the terminal, and conduct operations such as export, statistics, modification, format conversion and the like on the waveform file.

In some embodiments, the electronic device may obtain some or all of the information in the hierarchical data set, such as memory address information or other critical information, from the compilation database 212. For example, the electronic device is configured to invoke a read application program interface (application program interface, API) of the compilation database 212 to deserialize to implement the read function. In some embodiments, waveform information may be filtered and simulated at the chip level, at simulation time, at simulation event, etc. dimensions and partially saved at 406, as shown in block 414, so that only the critical information needed is retained. For example, for signals at a first node and a second node in a circuit node, a user may use an option or through input to determine whether the signal at the first node is a desired or target signal and the signal at the second node is an undesired or unwanted signal. The electronic device may thus only perform a simulated output and storage of the signal at the first node. This may significantly reduce the file size that needs to be processed before compression in block 416, reducing the need for extreme compression ratios, and may greatly improve simulation efficiency. After the waveform is saved, the electronic device may display the waveform data at 408 as desired (e.g., user input or command).

In some embodiments, the electronic device is configured to determine the target signal set based on the hierarchical mapping relationship. The target signal set includes the first signal and the target signal set does not include the second signal. Based on the determined set of target signals, the circuit is simulated to selectively generate a set of target waveform data in the waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal. In one embodiment, for example, the first signal is an input signal of an inverter and the second signal is an output signal of the inverter. It is understood that the second signal is the inverse of the first signal. In this case, although both the first signal and the second signal are desired signals, since there is a fixed-level mapping relationship between the second signal and the first signal (in other words, the second signal can be determined based on the first signal), simulation output and storage of the second signal are not actually required. By establishing a hierarchical mapping relationship between a plurality of associated signals, a relationship of another signal can be determined based on a single signal, which can avoid waveform computation and storage of the plurality of signals, thereby further reducing the time for waveform processing and storage and reducing waveform storage capacity.

It will be appreciated that in some simulations, glitch signals may be present. The glitch signal may be important to verify the correctness of the circuit design, and thus in some cases it may be desirable to record the glitch signal in the signal. Circuit simulations are typically performed by successive approximation or multiple assignments over a time period or time slot (e.g., a unit time period) to obtain a final value of the simulation over the time period or time slot. In some cases the signal may have multiple values during this period. To ensure accuracy of circuit simulation, in some embodiments, multiple values may be simulated output and stored. For example, the plurality of signals may include a third signal. Selectively generating the target waveform dataset in the waveform database includes: based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in the waveform database, wherein the simulated waveform data for the third signal includes spur data. Specifically, the spur data may include a plurality of spur values for the third signal within a unit time period. The electronic device stores a plurality of spur values in a memory in chronological order.

Fig. 5 illustrates a schematic diagram 500 of glitch signals according to some embodiments of the disclosure in which hexagons, rectangles, and circles represent first, second, and third signals, respectively. The waveform database 214 may hold signal values that change multiple times over various time periods. For example, during the period T1, the waveform database 214 sequentially obtains the first value (1), the second value (2), the third value (3), and the third value (3) by simulation for the third signal. It will be appreciated that during the time period T1, the third signal is changed 2 times, i.e. from the first value (1) to the second value (2) and from the second value (2) to the third value (3). The waveform database 214 may store a first value (1), a second value (2), and a third value (3) for a time period T1. By providing a glitch recording function, more accurate and detailed waveform information can be provided to circuit designers to facilitate determining the accuracy of the circuit design.

In some embodiments, the electronic device may be further configured to determine whether adjacent ones of the plurality of spur values are the same; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. As shown in fig. 5, during the period T1, two third values (3) are simulated. The waveform database 214 may hold only one third value (3). By combining multiple adjacent spur values into a single spur value, the amount of waveform data can be further reduced. In another embodiment, if there are further values between the two third values (3) during the time period T1, then the two third values (3) and the further values between them need to be saved.

Returning to FIG. 3, at 306, at least a portion of the target waveform dataset is stored in memory. In some embodiments, the electronic device, upon emulation, the emulation-generated waveform data may be located in a cache, for example, and the user may select the emulated waveform data to be stored in a memory, such as a non-volatile memory, according to an option or command input selected on the image interface. Further, in order to further reduce the amount of data stored, the electronic device may store in the memory a data portion of the time period corresponding to the storage time indication in the simulated waveform data of the target signal in the target waveform data set. For example, the user may only be concerned about the waveform from the start of the simulation to the end of the period T2. In this case, the waveform database 214 may store only signals of at least a part of all signals from the start of the simulation to the end of the period T2 based on the user's option or input command. By setting the waveform time periods to be simulated and stored by the user, the amount of data and time can be further reduced compared to the simulation and data storage of the entire period. Although described herein using time period T2, it is to be understood that this is by way of illustration only and is not limiting as to the scope of the present disclosure. In other embodiments, the user may select some or all of the signals during other time periods. For example, the user may select a portion or all of the signals, e.g., a square second signal, for a period of time from the end of T1 to the end of T3. Furthermore, in some embodiments, signals of non-continuous time periods may also be selected. For example, a signal from the start of the simulation to the end of the period T1 and a signal from the end of the period T2 to the end of the period T3 may be selected. The electronic device may correspondingly transfer the signals of the selected intervals into the non-volatile memory.

In summary, since the dedicated compilation database is provided to store the hierarchical data set in the compilation stage, and the compilation database can be accessed through the dedicated waveform database in the simulation stage to selectively generate corresponding waveform data and selectively store the waveform data during the simulation based on the digital circuit business characteristics, the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be correspondingly reduced. Compared with the conventional digital simulation tool which directly performs operations such as signal connection relation construction, waveform information recording and the like in the simulation stage scheduling execution process and full waveform file output, the technical scheme of the present disclosure can greatly reduce the file size to be saved before waveform file compression and storage through preprocessing in the compiling stage. The feature extraction in combination with the service level can be implemented to remove redundant information during the compilation phase. On the premise of avoiding the loss of effective information, the size of a waveform file is reduced from the source before the compression algorithm is performed, so that the pressure of encoding and decoding on simulation time is reduced and the simulation time is correspondingly reduced.

Some aspects of the present disclosure described above for various embodiments, exemplary signal writing and reading processes are described below. Fig. 6 illustrates a schematic diagram of a signal writing process according to some embodiments of the present disclosure. An upper layer calling module, such as an emulator or debugger, may stream the data to a waveform writing module in the waveform database. The data processing module in the waveform writing module has a Database (DB) interface. The data processing module may perform processes such as checking, deduplication, and encoding on the data after it is received via the DB interface, and put the processed data into the data buffer. The waveform writing module then analyzes the data in the cache to determine basic information, design structure, analog signals, digital signals, or other attributes or parameters of the data. After this, data classification and partitioning may be performed, and the data is classified or partitioned by category. The resulting data blocks may be compressed in blocks and an index built to obtain a waveform file. The waveform file may be stored in a non-volatile memory. Although a specific waveform writing scheme is shown herein, it is to be understood that this is by way of illustration only and is not limiting as to the scope of the present disclosure. Other waveform writing schemes may be used as desired.

Fig. 7 illustrates a schematic diagram of a signal reading process according to some embodiments of the present disclosure. The upper display module is configured to display waveforms on the waveform display interface. The display module may transmit the control parameters to the underlying processing module. The processing module comprises a data processing module and a waveform processing module. After the data processing module receives the control parameters via its data interface, it may export them to the waveform processing module. After the waveform processing module receives the processed parameters through the DB interface, the waveform data in the first format or the second format may be read from the memory, decompressed, decoded, and/or transferred to the buffer, and transferred to the data processing module via the DB interface. Alternatively, in this process, the waveform data may also be format-converted as needed. For example, waveform data may be converted from a third format to the first format or the second format. The data processing module samples, looks up, counts and/or calculates the data from the waveform processing module and displays the data stream on the waveform interface via the data interface. It will be appreciated that the modules shown in fig. 6 and 7 may be implemented by a program, and that the various modules may be combined, separated, invoked, or nested as desired, and this disclosure is not limited in this regard. For example, the waveform writing module of fig. 6 may be embedded in the waveform processing module of fig. 7. Furthermore, each of the modules shown in fig. 6 and 7 may include more or less modules as desired, and are not limited to the functions or sub-modules shown. For example, the data processing modules shown in fig. 6 and 7 only show a portion of the data processing module, and the data processing module may include more items.

Fig. 8 illustrates a schematic block diagram of an electronic device 800, according to some embodiments of the present disclosure. The electronic device 800 may comprise a plurality of modules for performing corresponding steps in the method as discussed in fig. 3. The electronic device 800 comprises a compiling unit 802, an emulation unit 804 and a storage unit 806. The compiling unit 802 is configured to compile a circuit file representing a circuit to generate a hierarchical data set for the circuit in a compiling database, the hierarchical data set being associated with a plurality of signals at a plurality of nodes in the circuit. The simulation unit 804 is configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database configured to provide an interface for accessing the compiled database. The storage unit 806 is configured to store at least a portion of the target waveform dataset in a memory. Since the dedicated compilation database is provided to store the hierarchical data set in the compilation stage, and the compilation database can be accessed through the dedicated waveform database in the simulation stage to selectively generate corresponding waveform data and selectively store the waveform data during the simulation based on the digital circuit traffic characteristics, the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be correspondingly reduced. Compared with the conventional digital simulation tool which directly performs operations such as signal connection relation construction, waveform information recording and the like in the simulation stage scheduling execution process and full waveform file output, the technical scheme of the present disclosure can greatly reduce the file size to be saved before waveform file compression and storage through preprocessing in the compiling stage. The feature extraction in combination with the service level can be implemented to remove redundant information during the compilation phase. On the premise of avoiding the loss of effective information, the size of a waveform file is reduced from the source before the compression algorithm is performed, so that the pressure of encoding and decoding on simulation time is reduced and the simulation time is correspondingly reduced.

In some embodiments, the circuit file used to represent the circuit includes a register transfer level description file. In some embodiments, the hierarchical data set is organized in a hierarchical tree form, and the hierarchical data set includes at least one of: sequence information for representing serialization of a plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing the hierarchical data sets in the form of a hierarchical tree, it is possible to facilitate finding, modifying, and saving the hierarchical data based on various attributes (such as driving relationships, load relationships, memory addresses, module calls, etc.), and accordingly, to make selective signal simulation and storage easier.

In some embodiments, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. The compiling unit 802 is further configured to: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal.

In some embodiments, the simulation unit 804 is further configured to: determining a target signal set based on the hierarchical mapping relationship, the target signal set including the first signal and the target signal set not including the second signal; based on the determined set of target signals, the circuit is simulated to selectively generate a set of target waveform data in the waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal. By establishing a hierarchical mapping relationship between a plurality of associated signals, a relationship of another signal can be determined based on a single signal, which can avoid simulation calculation and storage of the plurality of signals, thereby further reducing simulation time and reducing the storage capacity of the simulated signals.

In some embodiments, the electronic device 800 further comprises a receiving unit. The receiving unit is configured to receive a storage time indication for the target signal. The storage unit 806 is further configured to: a data portion of a time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set is stored in the memory. By setting the waveforms of the time periods to be simulated and stored by the user, the amount of data and time can be further reduced compared to the simulation and data storage of the entire period.

In some embodiments, the plurality of signals includes a third signal. The simulation unit 804 is further configured to: based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in the waveform database, wherein the simulated waveform data for the third signal includes spur data.

In some embodiments, the spur data includes a plurality of spur values for the third signal within a unit time period. The storage unit 806 is further configured to: a plurality of spur values are stored in a memory in chronological order. In some embodiments, the storage unit 806 is further configured to: determining whether adjacent ones of the plurality of spur values are the same; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. By providing a glitch recording function, more accurate and detailed waveform information can be provided to circuit designers to facilitate determining the accuracy of the circuit design.

In some embodiments, the storage unit 806 is further configured to determine whether adjacent ones of the plurality of spur values are the same; and if the adjacent spur values are the same, storing any one of the adjacent spur values in the memory without storing another one of the adjacent spur values. By combining multiple adjacent spur values into a single spur value, the amount of waveform data can be further reduced.

In some embodiments, the electronic device 800 further comprises an adjustment unit. The adjustment unit is configured to adjust the hierarchical data set based on user input. By adjusting the hierarchical data set, the designer may be given flexibility in circuit verification. In addition, in the case where the designer adjusts the hierarchical data set to retain only the signal of interest to himself, the time of circuit simulation and the data amount of the waveform signal can be further reduced.

Fig. 9 shows a schematic block diagram of an example device 900 that may be used to implement embodiments of the present disclosure. Fig. 9 shows a schematic block diagram of an example device 900 that may be used to implement embodiments of the present disclosure. As shown, device 900 includes a computing unit 901 that can perform various suitable actions and processes in accordance with computer program instructions stored in Random Access Memory (RAM) and/or Read Only Memory (ROM) 902 or loaded from storage unit 908 into RAM 903 and/or ROM 902. In the RAM 903 and/or ROM 902, various programs and data required for the operation of the device 900 may also be stored. The computing unit 901 and the RAM 903 and/or ROM 902 are connected to each other by a bus 904. An input/output (I/O) interface 905 is also connected to the bus 904.

Various components in device 900 are connected to I/O interface 905, including: an input unit 906 such as a keyboard, a mouse, or the like; an output unit 907 such as various types of displays, speakers, and the like; a storage unit 908 such as a magnetic disk, an optical disk, or the like; and a communication unit 909 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 909 allows the device 900 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunications networks.

The computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 901 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as method 300. For example, in some embodiments, the method 300 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 908. In some embodiments, some or all of the computer program may be loaded and/or installed onto device 900 via RAM and/or ROM and/or communication unit 909. One or more of the steps of method 300 described above may be performed when a computer program is loaded into RAM and/or ROM and executed by computing unit 901. Alternatively, in other embodiments, computing unit 901 may be configured to perform method 300 by any other suitable means (e.g., by means of firmware).

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims (22)

1. A method for generating and storing waveform data in a circuit simulation process, comprising:

compiling a circuit file representing a circuit to generate a hierarchical dataset for the circuit in a compiled database, the hierarchical dataset being associated with a plurality of signals at a plurality of nodes in the circuit;

Simulating the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database configured to provide an interface to access the compiled database; and

at least a portion of the target waveform dataset is stored in a memory.

2. The method of claim 1, wherein the hierarchical dataset is organized in a hierarchical tree form and the hierarchical dataset comprises at least one of: sequence information for representing serialization of the plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals.

3. The method of claim 1 or 2, wherein the plurality of signals comprises a first signal and a second signal, the hierarchical dataset comprising a hierarchical mapping relationship between the first signal and the second signal; and

generating a hierarchical dataset for the circuit in a compilation database includes: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine the mapping relationship between the first signal and the second signal.

4. The method of claim 3, wherein selectively generating the target waveform dataset in the waveform database comprises:

determining a target signal set based on the mapping relationship, the target signal set including the first signal and the target signal set not including the second signal; and

the circuit is simulated based on the determined set of target signals to selectively generate a set of target waveform data in a waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal.

5. The method of any of claims 1-4, further comprising: receiving a storage time indication for a target signal; and

wherein storing the at least a portion of the target waveform dataset in the memory comprises:

a data portion of a time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set is stored in the memory.

6. The method of any of claims 1-5, wherein the plurality of signals comprises a third signal; and

Wherein selectively generating the target waveform dataset in the waveform database comprises:

based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in a waveform database, wherein the simulated waveform data for the third signal includes spur data.

7. The method of claim 6, wherein the spur data comprises a plurality of spur values for a third signal within a unit time period; and

storing at least a portion of the target waveform dataset in a memory includes: the plurality of spur values are stored in the memory in chronological order.

8. The method of claim 7, wherein storing the plurality of spur values in the memory in chronological order comprises:

determining whether adjacent ones of the plurality of spur values are the same; and

if the adjacent spur values are the same, any one of the adjacent spur values is stored in the memory without storing another one of the adjacent spur values.

9. The method of any of claims 1-8, further comprising:

based on user input, the hierarchical dataset is adjusted.

10. The method of any of claims 1-9, wherein the circuit file to represent a circuit comprises a register transfer level description file.

11. A computer readable storage medium storing a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method of any of claims 1-10.

12. A computer program product comprising a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method of any of claims 1-10.

13. An electronic device, comprising:

one or more processors;

a memory comprising computer instructions that, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any of claims 1-8.

14. An electronic device, comprising:

a compiling unit configured to compile a circuit file representing a circuit to generate a hierarchical dataset for the circuit in a compiling database, the hierarchical dataset being associated with a plurality of signals at a plurality of nodes in the circuit;

A simulation unit configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database configured to provide an interface to access the compiled database; and

a storage unit configured to store at least a portion of the target waveform dataset in a memory.

15. The electronic device of claim 14, wherein the hierarchical dataset is organized in a hierarchical tree form and the hierarchical dataset comprises at least one of: sequence information for representing serialization of the plurality of signals, path information for representing transmission paths of the plurality of signals, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals.

16. The electronic device of claim 14 or 15, wherein the plurality of signals includes a first signal and a second signal, the hierarchical dataset including a hierarchical mapping relationship between the first signal and the second signal; and

the compiling unit is further configured to: the first signal and the second signal are matched with signals in a set of circuit models in a register transfer level description file to determine the mapping relationship between the first signal and the second signal.

17. The electronic device of claim 16, wherein the emulation unit is further configured to:

determining a target signal set based on the mapping relationship, the target signal set including the first signal and the target signal set not including the second signal; and

the circuit is simulated based on the determined set of target signals to selectively generate a set of target waveform data in a waveform database, the set of target waveform data including simulated waveform data of the first signal and the set of target waveform data not including simulated waveform data of the second signal.

18. The electronic device of any of claims 14-17, further comprising: a receiving unit configured to receive a storage time indication for a target signal; and

the memory unit is further configured to:

a data portion of a time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set is stored in the memory.

19. The electronic device of any of claims 14-18, wherein the plurality of signals includes a third signal; and

The simulation unit is further configured to:

based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in a waveform database, wherein the simulated waveform data for the third signal includes spur data.

20. The electronic device of claim 19, wherein the spur data comprises a plurality of spur values for a third signal over a unit time period; and

the memory unit is further configured to: the plurality of spur values are stored in the memory in chronological order.

21. The electronic device of claim 20, wherein the storage unit is further configured to:

determining whether adjacent ones of the plurality of spur values are the same; and

if the adjacent spur values are the same, any one of the adjacent spur values is stored in the memory without storing another one of the adjacent spur values.

22. The electronic device of any of claims 14-21, further comprising:

an adjustment unit configured to adjust the hierarchical data set based on user input.