WO2023193547A1 - Method for generating and storing waveform data during circuit simulation, electronic device and storage medium - Google Patents

Abstract

A method for generating and storing waveform data during circuit simulation. The method comprises: compiling a circuit file which is used for representing a circuit, so as to generate a hierarchy data set for the circuit in a compilation database; simulating the circuit on the basis of the hierarchy data set and the circuit file, so as to selectively generate a target waveform data set in a waveform database, wherein the waveform database is configured to provide an interface to access the compilation database; and storing at least part of the target waveform data set in a memory. A dedicated compilation database is set in a compilation stage, so as to store a hierarchy data set; and in a simulation stage, the compilation database can be accessed by means of a dedicated waveform database, so that during simulation, corresponding waveform data is selectively generated on the basis of a digital circuit service feature, and the waveform data is selectively stored. Therefore, the amount of waveform data generated and stored during simulation can be reduced, thereby correspondingly reducing simulation time.

Description

Method, electronic device and storage medium for generating and storing waveform data during circuit simulation

This application is required to be submitted to the China Patent Office on April 8, 2022, with the application number 202210369305.4 and the invention title "Method, electronic device and storage medium for generating and storing waveform data in the circuit simulation process". priority, the entire contents of which are incorporated into this application by reference.

Technical field

The present disclosure relates to the field of electronics, and more particularly to methods, electronic devices, computer programs, and storage media for generating and storing waveform data during circuit simulation.

Background technique

During the circuit design process, it is usually necessary to verify the correctness of the circuit design. In some cases, it is necessary to use a digital circuit simulator to meet the simulation debugging function. In order to meet the needs of simulation debugging, it is usually necessary to generate some accurate and efficient waveform signals. The generation of waveforms requires monitoring relevant signals during the simulation process and saving the change process of their values. This will generate a large number of parameter transfers and event records, which greatly affects the simulation performance.

The Institute of Electrical and Electronics Engineers (IEEE) defines a value change dump (VCD) format file in the IEEE1364 standard. The VCD file includes header information, predefinition of variables and change information of variable values. Since the VCD file contains signal change information, which is equivalent to recording the entire simulation information, it can use this file to reproduce the simulation and display the waveform. In addition, since VCD files are part of the Verilog hardware description language standard, all Verilog simulators must be able to implement this function and also allow users to dump VCD files through system functions in Verilog code.

In some conventional solutions, effective information extraction is performed on VCD files and redundant information is removed. This is similar to Huffman encoding of VCD data. Therefore, the data file size will decrease to a certain extent, but in the actual simulation process, due to the limited encoding and decoding capabilities, the actual amount of waveform data is still relatively large. In addition, the simulation time is still long.

Contents of the invention

Based on the above problems, embodiments of the present disclosure aim to provide a method, electronic device, computer program and storage medium for generating and storing waveform data during circuit simulation, so as to reduce the amount of data generated by circuit simulation and the simulation time. .

According to a first aspect of the present disclosure, a method for generating and storing waveform data during circuit simulation is provided. The method includes compiling a circuit file representing the circuit to generate a hierarchy data set for the circuit in a compiled database, the hierarchy data set being associated with a plurality of signals at a plurality of nodes in the circuit. The method also includes simulating the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in the waveform database. The waveform database is configured to provide an interface to access the compiled database. The method also includes storing at least a portion of the target waveform data set in a memory. Since a dedicated compilation database is set up in the compilation phase to store hierarchical data sets, and in the simulation phase, the compilation database can be accessed through the dedicated waveform database to selectively generate corresponding waveform data based on the digital circuit business characteristics and further selectively store the waveform data. , thus reducing the amount of waveform data generated and saved during simulation and correspondingly reducing simulation time. Compared with conventional digital simulation tools that directly schedule the execution process in the simulation phase to construct signal connection relationships, record waveform information, and output full waveform files, the technical solution of the present disclosure can perform waveform file processing through preprocessing in the compilation phase. Compression and storage have previously greatly reduced the size of files that need to be saved. Combined with business-level feature extraction, redundant information can be removed during the compilation phase. Avoiding On the premise of avoiding the loss of effective information, the waveform file size has been reduced from the source before performing the compression algorithm, thereby reducing the pressure of encoding and decoding on simulation time and reducing the simulation time accordingly. In an implementation of the first aspect, the method further includes storing all data of the target waveform data set in the memory.

In an implementation of the first aspect, the circuit file used to represent the circuit includes a register transfer level description file. In an implementation of the first aspect, the hierarchical data set is organized in the form of a hierarchical tree, and the hierarchical data set includes at least one of the following: serialized sequence information used to represent multiple signals, Path information of the transmission path, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing hierarchical data sets in the form of a hierarchical tree, it is easier to find, modify, and save hierarchical data based on individual attributes (such as driver relationships, load relationships, memory addresses, module calls, etc.), and accordingly it is easier to do so selectively. Signal generation and storage.

In an implementation manner of the first aspect, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. Generating a hierarchical data set for the circuit in the compiled database includes matching the first signal and the second signal with signals in the circuit model set in the register transfer level description file to determine the hierarchical level between the first signal and the second signal. Mapping relations.

In an implementation manner of the first aspect, selectively generating the target waveform data set in the waveform database includes: determining the target signal set based on the hierarchical mapping relationship, the target signal set includes the first signal, and the target signal set does not include the third signal. Two signals; based on the determined target signal set, simulate the circuit to selectively generate a target waveform data set in the waveform database, the target waveform data set includes the simulated waveform data of the first signal, and the target waveform data set does not include Simulated waveform data of the second signal. By establishing a hierarchical mapping relationship between multiple associated signals, the relationship of another signal can be determined based on a single signal, which can avoid the calculation and storage of waveform data sets for multiple signals, thereby further reducing simulation time and reducing simulation signals. storage capacity.

In an implementation of the first aspect, the method further includes: receiving a storage time indication for the target signal. Storing at least a portion of the target waveform data set in the memory includes: storing in the memory a data portion of a time period corresponding to the storage time indication in the simulated waveform data of the target signal in the target waveform data set. By allowing the user to set the time period during which waveforms need to be processed and saved, the amount and time of waveform data processing can be further reduced compared to simulation and data storage for the entire period.

In an implementation of the first aspect, the plurality of signals includes a third signal. Selectively generating the target waveform data set in the waveform database includes: simulating the circuit based on the hierarchical data set and the circuit file to generate simulated waveform data for the third signal in the waveform database, where the simulated waveform for the third signal The data includes glitch data. In an implementation of the first aspect, the glitch data includes a plurality of glitch values for the third signal within a unit time period; and storing at least a part of the target waveform data set in the memory includes: converting the plurality of glitch values according to The chronological order is stored in memory. By providing glitch signal recording function, circuit designers can be provided with more accurate and detailed waveform information to determine the accuracy of circuit design.

In an implementation of the first aspect, storing the plurality of glitch values in a memory in time sequence includes: determining whether adjacent glitch values in the plurality of glitch values are the same; and if the adjacent glitch values are the same, then Either one of the adjacent glitch values is stored in memory without the other one of the adjacent glitch values. Waveform data volume can be further reduced by merging multiple adjacent glitch values into a single glitch value.

In an implementation of the first aspect, the method further includes: adjusting the hierarchical data set based on user input. Adjustments to hierarchical data sets give designers flexibility in circuit verification. In addition, circuit simulation time and waveform signal data volume can be further reduced when designers adjust the hierarchical data set to retain only the signals of interest.

According to a second aspect of the present disclosure, a computer-readable storage medium is provided that stores a plurality of programs. A plurality of programs is configured for execution by one or more processors, the plurality of programs including instructions for performing the method of the first aspect.

According to a third aspect of the present disclosure, a computer program product is provided. The computer program product includes a plurality of programs configured for execution by one or more processors, the plurality of programs comprising instructions for performing the method of the first aspect.

According to a fourth aspect of the present disclosure, an electronic device is provided. The electronic device includes: one or more processors; and a memory including computer instructions that, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of the first aspect.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic equipment includes a compilation unit, a simulation unit and a storage unit. The compilation unit is configured to compile a circuit file representing the circuit to generate a hierarchical data set for the circuit in the compilation database, the hierarchical data set being associated with a plurality of signals at a plurality of nodes in the circuit. The simulation unit is configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate the target waveform data set in the waveform database, and the waveform database is configured to access the compilation database. The storage unit is configured to store at least a portion of the target waveform data set in the memory. Since a dedicated compilation database is set up in the compilation phase to store hierarchical data sets, and the compilation database can be accessed through a dedicated waveform database in the simulation phase, corresponding waveform data can be selectively generated and stored selectively during the simulation process based on the business characteristics of the digital circuit. Waveform data, thus reducing the amount of waveform data generated and saved during simulation and correspondingly reducing simulation time. Compared with conventional digital simulation tools that directly schedule the execution process in the simulation phase to construct signal connection relationships, record waveform information, and output full waveform files, the technical solution of the present disclosure can perform waveform file processing through preprocessing in the compilation phase. Compression and storage have previously greatly reduced the size of waveform files that need to be saved. Combined with business-level feature extraction, redundant information can be removed during the compilation phase. On the premise of avoiding the loss of effective information, the waveform file size has been reduced from the source before performing the compression algorithm, thereby reducing the pressure of encoding and decoding on simulation time and reducing the simulation time accordingly.

In an implementation of the fifth aspect, the circuit file used to represent the circuit includes a register transfer level description file. In an implementation of the fifth aspect, the hierarchical data set is organized in the form of a hierarchical tree, and the hierarchical data set includes at least one of the following: serialized sequence information used to represent multiple signals, Path information of the transmission path, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing hierarchical data sets in the form of a hierarchical tree, it is easier to find, modify, and save hierarchical data based on individual attributes (such as driver relationships, load relationships, memory addresses, module calls, etc.), and accordingly it is easier to do so selectively. Signal simulation and storage.

In an implementation manner of the fifth aspect, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. The compilation unit is further configured to: match the first signal and the second signal with signals in the circuit model set in the register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal.

In an implementation manner of the fifth aspect, the simulation unit is further configured to: determine the target signal set based on the hierarchical mapping relationship, the target signal set includes the first signal, and the target signal set does not include the second signal; based on the determined a target signal set, simulating the circuit to selectively generate a target waveform data set in the waveform database, the target waveform data set includes simulated waveform data of the first signal, and the target waveform data set does not include simulated waveform data of the second signal . By establishing a hierarchical mapping relationship between multiple associated signals, the relationship of another signal can be determined based on a single signal, which can avoid the simulation calculation and storage of multiple signals, thereby further reducing simulation time and reducing the storage capacity of signal waveforms. .

In an implementation manner of the fifth aspect, the electronic device further includes a receiving unit. The receiving unit is configured to receive a storage time indication for the target signal. The storage unit is further configured to: store in the memory a data portion of the time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set. By setting by user The waveforms of the time period to be simulated and stored can further reduce the amount of data and time compared to the simulation and data storage of the entire period.

In an implementation of the fifth aspect, the plurality of signals includes a third signal. The simulation unit is further configured to: simulate the circuit based on the hierarchical data set and the circuit file to generate simulated waveform data for the third signal in the waveform database, where the simulated waveform data for the third signal includes glitch data.

In an implementation manner of the fifth aspect, the glitch data includes a plurality of glitch values for the third signal within a unit time period. The storage unit is further configured to store the plurality of glitch values in the memory in time sequence. In an implementation manner of the fifth aspect, the storage unit is further configured to: determine whether adjacent glitch values among the plurality of glitch values are the same; and if the adjacent glitch values are the same, convert any of the adjacent glitch values to A glitch value is stored in memory without storing another glitch value within an adjacent glitch value. By providing glitch signal recording function, circuit designers can be provided with more accurate and detailed waveform information to determine the accuracy of circuit design.

In an implementation manner of the fifth aspect, the storage unit is further configured to determine whether adjacent glitch values among the plurality of glitch values are the same; and if the adjacent glitch values are the same, then convert any one of the adjacent glitch values into The value is stored in memory without storing another glitch value within the adjacent glitch value. Waveform data volume can be further reduced by merging multiple adjacent glitch values into a single glitch value.

In an implementation manner of the fifth aspect, the electronic device further includes an adjustment unit. The adjustment unit is configured to adjust the hierarchical data set based on user input. Adjustments to hierarchical data sets give designers flexibility in circuit verification. In addition, when designers adjust the hierarchical data set to retain only the signal waveforms they are interested in, the time and data volume of waveform processing during circuit simulation can be further reduced.

It should be understood that what is described in this summary is not intended to identify key or important features of the embodiments of the disclosure, nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the description below.

Description of the drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent with reference to the following detailed description taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numbers represent the same or similar elements, where:

Figure 1 shows a schematic diagram of a conventional circuit simulation process.

Figure 2 shows a circuit simulation schematic in accordance with some embodiments of the present disclosure.

3 illustrates a schematic flowchart of a method for generating and storing waveform data during circuit simulation in accordance with some embodiments of the present disclosure.

Figure 4 shows a schematic diagram of a circuit simulation process according to some embodiments of the present disclosure.

Figure 5 shows a schematic diagram of a glitch signal according to some embodiments of the present disclosure.

Figure 6 shows a schematic diagram of a signal writing process according to some embodiments of the present disclosure.

Figure 7 shows a schematic diagram of a signal reading process according to some embodiments of the present disclosure.

Figure 8 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.

Figure 9 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, which rather are provided for A more thorough and complete understanding of this disclosure. It should be understood that this disclosure The drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

In the description of embodiments of the present disclosure, the term "including" and similar expressions shall be understood as an open inclusion, that is, "including but not limited to." The term "based on" should be understood to mean "based at least in part on." The terms "one embodiment" or "the embodiment" should be understood to mean "at least one embodiment". The terms "first," "second," etc. may refer to different or the same object. Other explicit and implicit definitions may be included below.

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As used herein, the term "include" and its variations mean an open inclusion, ie, "including but not limited to." Unless otherwise stated, the term "or" means "and/or". The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," etc. may refer to different or the same object. Other explicit and implicit definitions may be included below.

Figure 1 shows a schematic diagram of a conventional circuit simulation process. At 102, an electronic device, such as a computer, receives a file describing or representing a circuit, such as a register transfer level (RTL) file, and compiles the RTL file. At 104, the electronic device performs a simulation run on the compiled file. During the simulation run, the electronic device may generate a full waveform 114, that is, a collection of waveform signals at various nodes in the circuit. At 116, the electronic device can store the full waveform. Optionally, during the process of waveform storage, the electronic device can compress 116 the generated waveform data to generate a dedicated waveform format file, thereby achieving the purpose of reducing the size of the waveform file. In some conventional solutions, the pursuit of the ultimate compression ratio may even cause the compressed encoding and decoding time to greatly affect the simulation performance, for example, the encoding and decoding time increases significantly. After the waveform is stored in memory, the electronic device may display the waveform at 108 at any time in response to input from the designer.

As mentioned above, in conventional solutions, circuit simulation usually does not perform processing related to signal waveform information on the compilation side. Instead, the execution process is scheduled during the simulation runtime to construct signal connection relationships, record waveform information, and other operations, and perform waveform files. output. This brings great degradation to the simulation time. In addition, in some conventional solutions, although effective information extraction and redundant information are removed from waveform files such as VCD files, in the actual simulation process, due to limited encoding and decoding capabilities, the actual amount of data is still relatively small. is large and the simulation time is still long.

In the present disclosure, a dedicated compile database (compile database) and a waveform database are respectively set up on the compilation side and the simulation running side to transmit and store hierarchical data sets. Since a dedicated compilation database is set up in the compilation phase to store hierarchical data sets, and the compilation database can be accessed through a dedicated waveform database in the simulation phase, corresponding waveform data can be selectively generated and stored selectively during the simulation process based on the business characteristics of the digital circuit. Waveform data, thus reducing the amount of waveform data generated and saved during simulation and correspondingly reducing simulation time. Compared with conventional digital simulation tools that directly schedule the execution process in the simulation phase to construct signal connection relationships, record waveform information, and output full waveform files, the technical solution of the present disclosure can perform waveform file processing through preprocessing in the compilation phase. Compression and storage have previously greatly reduced the size of waveform files that need to be saved. Combined with business-level feature extraction, redundant information can be removed during the compilation phase. On the premise of avoiding the loss of effective information, the waveform file size has been reduced from the source before performing the compression algorithm, thereby reducing the pressure of encoding and decoding on simulation time and reducing the simulation time accordingly. In an implementation of the first aspect, the method further includes storing all data of the target waveform data set in the memory.

Figure 2 shows a schematic diagram of a circuit simulation 200 in accordance with some embodiments of the present disclosure. An electronic device with computing capabilities, such as a computer, may receive a file 201 such as an RTL file describing a circuit, and at 202 The electronic device can compile file 201. Optionally, the file 201 may be parsed and then compiled. Understandably, preliminary analysis is not necessary. In some embodiments, preliminary analysis may be performed integrated with compilation. In one embodiment, on the compilation side, a dedicated compilation database 212 may be provided. The compilation database 212 may be used to store information related to signal waveforms of the circuit to be simulated. In one embodiment, compilation database 212 may store hierarchical data sets. In one embodiment, the hierarchical data set is organized in a hierarchical tree (i.e., a hierarchical tree), and the hierarchical data set includes at least one of the following: serialized sequence information for representing a plurality of signals; Path information of the transmission path of the signals, address information corresponding to the plurality of signals, drive information for driving the plurality of signals, and load information for being driven by the plurality of signals. The hierarchical data set can be used to obtain the above information when back-checking the signal using the Verilog programming language interface (VPI). This can be used to build hierarchical structure information of the chip design code when generating waveform files. In one embodiment, this can be done by selecting the chip level during circuit debugging and selecting signals at a certain level for waveform display. In one embodiment, compilation database 212 may also provide serialization and deserialization of signals. For example, the compilation database 212 may serialize multiple signals and pass the serialized information to the simulation side. The emulation side can deserialize multiple serialized signals to determine the expected signal.

Specifically, the compilation database 212 can extract the relevant information of the hierarchical tree from the construction process of the abstract syntax tree (AST) and the intermediate representation (IR), and store it in the compilation database after serializing each information. in database 212. Although the hierarchical data set is organized in the form of a hierarchical tree here, this is only illustrative and does not limit the scope of the present disclosure. Other data structures can also be used to organize hierarchical data sets. By organizing hierarchical data sets in the form of a hierarchical tree, it is easier to find, modify, and save hierarchical data based on individual attributes (such as driver relationships, load relationships, memory addresses, module calls, etc.), and accordingly it is easier to do so selectively. Signal simulation and storage. Although described here as simulation run 204, it is understood that other tool chains 212 (such as circuit debuggers) may also access the compilation database 212 and/or the waveform database 214. This disclosure does not limit this.

At 204, the electronic device can perform simulation operation on the compiled file. During the simulation run, the electronic device may generate waveforms of each signal, and may store the desired target waveform data set in the waveform database 214 . Waveform database 214 is configured to access compilation database 212 . Compiled database 212 can therefore efficiently transfer hierarchical data sets to waveform database 214. Other tool chains 220 such as debuggers may also read and/or modify hierarchical data sets.

Specifically, during the simulation process, the electronic device can continuously generate target simulation data such as waveform data. The waveform database 214 is configured to provide a waveform writing service and record the target simulation data in the simulation process into the waveform database 214 . The waveform database 214 supports generating waveform files in multiple formats, such as fast signal database (FSDB) format, VCD format, etc. Waveform files in various formats can be converted to each other. After the simulation is completed, the waveform database 214 can provide a reading service to read data in the waveform file generated by the simulation.

In one embodiment, waveform database 214 is also configured to provide an interface to access hierarchical data sets in compiled database 212 . Designers can control the dump scope through input options based on hierarchical datasets. Based on the hierarchical data set, the electronic device can dynamically resolve the dump range through an interface such as a command line interface. Correspondingly, only the target waveform data is saved in the waveform file, and there is no need to save the waveform data of each signal in the complete hierarchy. As a result, repeated reading and writing of useless signals can be avoided and simulation overhead can be reduced.

In addition, in some embodiments, the waveform database 214 is also configured to save glitch information within a unit time period of the signal. For example, within a unit time period, the simulation result changes the value of the same signal multiple times, or the simulation result assigns multiple values to the same signal. In one embodiment, values may be saved in the waveform database 214 in real time after each region is updated. By saving glitch information, circuit designers can be provided with more accurate and detailed waveform information to determine the accuracy of circuit design.

Figure 3 illustrates a method for generating and storing waveform data during circuit simulation in accordance with some embodiments of the present disclosure. Schematic flow chart of Method 300. It can be understood that various aspects described above with respect to FIG. 2 can be selectively applied to the method 300, so the relevant parts will not be described again here. Method 300 may be performed by an electronic device such as a computer. Alternatively, the method 300 may also be executed by other electronic devices with computing capabilities, which will not be described in detail in this disclosure.

At 302, the electronic device compiles a circuit file representing the circuit to generate a hierarchical data set for the circuit in the compilation database 212, the hierarchical data set being associated with a plurality of signals at a plurality of nodes in the circuit. In some embodiments, circuit files representing circuits include register transfer level description files. In some embodiments, the hierarchical data set is organized in the form of a hierarchical tree, and the hierarchical data set includes at least one of the following: sequence information representing the serialization of a plurality of signals, a path representing a transmission path of the plurality of signals information, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By organizing hierarchical data sets in the form of a hierarchical tree, it is easier to find, modify, and save hierarchical data based on individual attributes (such as driver relationships, load relationships, memory addresses, module calls, etc.), and accordingly it is easier to do so selectively. Signal simulation and storage.

Figure 4 shows a schematic diagram of a circuit simulation process 400 in accordance with some embodiments of the present disclosure. At 402, through compilation of the circuit file, hierarchical data 412 may be generated. In one embodiment, hierarchical data 412 may be a hierarchical tree as described above. In one embodiment, the hierarchical tree can be intercepted or saved on the AST obtained after being parsed. The hierarchical tree can be organized according to various parameters, and each tree node can include a certain range of signal sets and each signal parameter (leaf node) within the signal set. In other words, the hierarchical data 412 may include node data branched by one or more of signal types, transfer paths, address assignments, driving relationships, load relationships, and the like.

It can be understood that in some embodiments, during the compilation process, the compiler performs step-by-step analysis (elaboration) of signal key information in the layer-by-layer intermediate expression downgrading (IR lowering) process. In addition, the compiler will also allocate corresponding memory space for all signals. In other embodiments, the compilation database 212 can also implement serialization of signals, and save key information such as driver information, load information, module calling relationships, memory address allocation, etc. on the corresponding nodes of the tree structure, so as to Find it later.

Further, the hierarchical data 412 may be further classified or branched by one or more of the above items. For example, with respect to signal types, part or all of the hierarchical data 412 may be further divided into repetitive signals, regular signals, combinational logic signals, delayed signals, periodic signals, etc. For example, a clock signal may be classified as a repetitive, regular, or periodic signal. The output signals of AND gates can be classified as combinational logic signals. The output of the buffer can be classified as a delayed signal. It can be understood that the above divisions are only illustrative and do not limit the scope of the present disclosure, and corresponding divisions can be made as needed.

In some embodiments, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. For example, the first signal may be the input of an inverter and the second signal be the output of the inverter. Therefore, when the waveform of the first signal is known, the waveform of the second signal can be obtained through a simple inversion operation. In this case, the hierarchical mapping relationship can be expressed as a negation operation. In another embodiment, the hierarchical data set includes hierarchical mapping relationships between the first signal and the fourth signal and the second signal. For example, the first signal and the fourth signal are the two inputs of the AND gate, while the second signal is the output of the AND gate. Therefore, when the waveforms of the first signal and the fourth signal are known, the waveform of the second signal can be obtained through a simple logical AND operation. Although described herein using inverters and AND gates, the disclosure is not limited thereto. This also applies when there is a predictable hierarchical mapping between two or more signals. Specifically, the electronic device may include a model library that includes various signal mapping models, such as signal mapping models for inverters, AND gates, OR gates, and the like. On the other hand, the circuit design may include multiple circuit modules, logic gate devices and other sub-circuit modules that can be split. Each circuit sub-circuit module may include respective signal inputs and outputs. Accordingly, generating the hierarchical data set for the circuit in the compilation database 212 includes matching the first signal and the second signal with the signals in the circuit model set in the register transfer level description file to determine the relationship between the first signal and the second signal. hierarchical mapping relationship between. For example, combine the signal of the module used to represent the AND gate function in the circuit file with the signal in the model library. Compare the AND gate signals to determine the hierarchical mapping relationship of the signals in the circuit file.

In some embodiments, the method further includes adjusting the hierarchical data set based on user input. During the compilation process, the user can call the interface of the compilation database 212 to delete, add or modify the signal nodes of the hierarchical tree. For example, driver information, load information, module call information, address information and other information can be modified. Adjustments to hierarchical data sets give designers flexibility in circuit verification. In addition, circuit simulation time and waveform signal data volume can be further reduced when designers adjust the hierarchical data set to retain only the signals of interest.

Returning to FIG. 3 , at 304 , the electronic device simulates the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in the waveform database 214 , where the waveform database 214 has a function for performing compilation database 212 Access interface. In some embodiments, waveform database 214 is configured to store and read simulation data, such as simulation waveform data, in a digital chip design. In other embodiments, the waveform database 214 is also configured to read waveform data on the debug side. The waveform database 214 may include, for example, three modules: a writing module, a reading module and an auxiliary tool module, each module providing independent functions to the outside world. In one embodiment, the writing module is configured to dump the waveform data input by the emulator or accessory tool into a waveform file. The reading module is configured to convert waveform data into memory waveform data and return it to the upper-layer caller through API form. The accessory tool module is configured to support users to input parameters on the terminal and perform operations such as exporting, statistics, modification, and format conversion of waveform files.

In some embodiments, the electronic device may obtain some or all information in the hierarchical data set from the compilation database 212, such as memory address information or other key information. For example, the electronic device is configured to call a reading application program interface (API) of the compiled database 212 to perform deserialization to implement the reading function. In some embodiments, as shown in block 414, the waveform information can be filtered and simulated by chip level, by simulation time, by simulation events and other dimensions and partially saved at 406, so that only the required key information is retained. For example, for signals at a first node and a second node in a circuit node, the user can use options or input to determine whether the signal at the first node is a desired signal or a target signal, and the signal at the second node is an undesired signal. Signal or unwanted signal. The electronic device can thereby simulate, output and store only the signal at the first node. This can greatly reduce the file size that needs to be processed before compression in the 416 box, reduces the need for the ultimate compression ratio, and can greatly improve simulation efficiency. After saving the waveform, the electronic device can display the waveform data at 408 as needed (such as user input or command).

In some embodiments, the electronic device is configured to determine the target signal set based on the hierarchical mapping relationship. The target signal set includes the first signal, and the target signal set does not include the second signal. Based on the determined target signal set, the circuit is simulated to selectively generate a target waveform data set in the waveform database, the target waveform data set includes simulated waveform data of the first signal, and the target waveform data set does not include the second signal simulation waveform data. In one embodiment, for example, the first signal is the input signal of the inverter and the second signal is the output signal of the inverter. It can be understood that the second signal is the inverted signal of the first signal. In this case, although the first signal and the second signal are both desired signals, since there is a fixed hierarchical mapping relationship between the second signal and the first signal (in other words, the second signal can be determined based on the first signal), therefore In fact, there is no need to simulate output and store the second signal. By establishing a hierarchical mapping relationship between multiple associated signals, the relationship of another signal can be determined based on a single signal, which can avoid the waveform calculation and storage of multiple signals, thereby further reducing the time of waveform processing and storage and reducing the size of the waveform. storage capacity.

It is understood that in some simulations, glitches may exist. Glitch signals can be important to verify the correctness of a circuit design, so in some cases it is necessary to record the glitches in the signal. Circuit simulation usually obtains the final simulation value in a time period or time slot (such as a unit time period) through gradual approximation or multiple assignments. But in some cases, the signal may have multiple values during this time period. To ensure the accuracy of circuit simulation, in some embodiments, multiple values may be simulated and output and stored. For example, the plurality of signals may include a third signal. Selectively generating target waveform data sets in the waveform database includes: simulating the circuit based on the hierarchical data set and circuit files, To generate simulated waveform data for the third signal in the waveform database, where the simulated waveform data for the third signal includes glitch data. Specifically, the glitch data may include a plurality of glitch values for the third signal within a unit time period. Electronic devices store multiple glitch values in memory in chronological order.

5 shows a schematic diagram 500 of a glitch signal according to some embodiments of the present disclosure, in which hexagons, rectangles, and circles represent the first signal, the second signal, and the third signal, respectively. The waveform database 214 may store signal values that change multiple times within each time period. For example, during the time period T1, for the third signal, the waveform database 214 sequentially obtains the first value ①, the second value ②, the third value ③ and the third value ③ through simulation. It can be understood that during the time period T1, the third signal changes twice, that is, from the first value ① to the second value ②, and from the second value ② to the third value ③. The waveform database 214 may store the first value ①, the second value ②, and the third value ③ for the time period T1. By providing glitch signal recording function, circuit designers can be provided with more accurate and detailed waveform information to determine the accuracy of circuit design.

In some embodiments, the electronic device may be further configured to determine whether adjacent glitch values among the plurality of glitch values are the same; and if the adjacent glitch values are the same, store any one of the adjacent glitch values in the memory , without storing another glitch value within an adjacent glitch value. As shown in Figure 5, during the time period T1, the simulation obtains two third values ③. The waveform database 214 may only store one third value ③. Waveform data volume can be further reduced by merging multiple adjacent glitch values into a single glitch value. In another embodiment, if there are other values between the two third values ③ during the time period T1, the two third values ③ and other values between them need to be saved.

Returning to Figure 3, at 306, at least a portion of the target waveform data set is stored in memory. In some embodiments, when the electronic device is being simulated, the waveform data generated by the simulation can be located in a cache, for example, and the user can choose to be stored in a non-volatile memory such as a non-volatile memory based on options selected on the graphical interface or command input. simulation waveform data in the memory. In addition, in order to further reduce the amount of stored data, the electronic device may store in the memory a data portion of the time period corresponding to the storage time indication in the simulated waveform data of the target signal in the target waveform data set. For example, the user may only be interested in the waveform from the beginning of the simulation to the end of time period T2. In this case, the waveform database 214 may store only at least a portion of all signals from the start of the simulation to the end of the time period T2 based on the user's options or input commands. By setting the waveform time period to be simulated and stored by the user, the amount of data and time can be further reduced compared to simulation and data storage for the entire period. Although the time period T2 is used for description here, it can be understood that this is only illustrative and does not limit the scope of the present disclosure. In other embodiments, the user may select some or all of the signal during other time periods. For example, the user can select part or all of the signals within the time period from the end of T1 to the end of T3, such as the second signal of the square. In addition, in some embodiments, signals of non-consecutive time periods may also be selected. For example, you can select a signal from the start of the simulation to the end of time period T1 and a signal from the end of time period T2 to the end of time period T3. The electronic device can correspondingly transfer the signal of the selected interval to the non-volatile memory.

To sum up, since a dedicated compilation database is set up in the compilation phase to store hierarchical data sets, and the compilation database can be accessed through a dedicated waveform database in the simulation phase, corresponding waveform data can be selectively generated during the simulation process based on the business characteristics of the digital circuit. And the waveform data is selectively stored, so the amount of waveform data generated and saved during the simulation can be reduced and the simulation time can be reduced accordingly. Compared with conventional digital simulation tools that directly schedule the execution process in the simulation phase to construct signal connection relationships, record waveform information, and output full waveform files, the technical solution of the present disclosure can perform waveform file processing through preprocessing in the compilation phase. Compression and storage have previously greatly reduced the size of files that need to be saved. Combined with business-level feature extraction, redundant information can be removed during the compilation phase. On the premise of avoiding the loss of effective information, the waveform file size has been reduced from the source before performing the compression algorithm, thereby reducing the pressure of encoding and decoding on simulation time and reducing the simulation time accordingly.

Some aspects of the present disclosure are described above with respect to various embodiments, and exemplary signal writing and reading processes are described below. Figure 6 shows a schematic diagram of a signal writing process according to some embodiments of the present disclosure. such as an emulator or debugger The upper calling module of the class can transmit the data stream to the waveform writing module in the waveform database. The data processing module in the waveform writing module has a database (database, DB) interface. After receiving the data through the DB interface, the data processing module can perform verification, deduplication, encoding and other processing on it, and put the processed data into the data cache. The waveform writing module then analyzes the data in the cache to determine the basic information of the data, design structure, analog signal or digital signal and other attributes or parameters. After this, the data can be classified and partitioned, and the data divided or chunked into categories. The resulting data blocks can be chunked, compressed and indexed to obtain a wave file. Waveform files can be stored in non-volatile memory. Although a specific waveform writing method is shown here, it can be understood that this is only illustrative and does not limit the scope of the present disclosure. Other waveform writing methods can be used as needed.

Figure 7 shows a schematic diagram of a signal reading process according to some embodiments of the present disclosure. The upper display module is configured to display waveforms on the waveform display interface. The display module can transmit control parameters to the underlying processing module. The processing module includes a data processing module and a waveform processing module. After the data processing module receives the control parameters via its data interface, it can export them to the waveform processing module. After receiving the processed parameters through the DB interface, the waveform processing module can read the waveform data in the first format or the second format from the memory, decompress, decode and/or transfer it to the cache, and transmit it through the DB interface to the data processing module. Alternatively, during this process, the waveform data can also be format-converted as needed. For example, the waveform data may be converted from the third format to the first format or the second format. The data processing module samples, searches, counts and/or calculates the data from the waveform processing module, and displays the data flow on the waveform interface through the data interface. It can be understood that the modules shown in Figures 6 and 7 can be implemented by programs, and each module can be combined, separated, called or nested as needed, and this disclosure is not limiting. For example, the waveform writing module of FIG. 6 can be embedded in the waveform processing module of FIG. 7 . Furthermore, each module shown in FIGS. 6 and 7 may include functions or sub-modules that are not limited to those shown, but may include more or fewer modules as needed. For example, the data processing module shown in FIGS. 6 and 7 only shows a part of the data processing module, and the data processing module may include more items.

Figure 8 shows a schematic block diagram of an electronic device 800 in accordance with some embodiments of the present disclosure. Electronic device 800 may include a plurality of modules for performing corresponding steps in the method as discussed in FIG. 3 . The electronic device 800 includes a compilation unit 802, a simulation unit 804, and a storage unit 806. The compilation unit 802 is configured to compile a circuit file representing the circuit to generate a hierarchical data set for the circuit in the compilation database, the hierarchical data set being associated with a plurality of signals at a plurality of nodes in the circuit. The simulation unit 804 is configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate the target waveform data set in the waveform database, and the waveform database is configured to provide an interface for accessing the compiled database. The storage unit 806 is configured to store at least a portion of the target waveform data set in a memory. Since a dedicated compilation database is set up in the compilation phase to store hierarchical data sets, and the compilation database can be accessed through a dedicated waveform database in the simulation phase, corresponding waveform data can be selectively generated and stored selectively during the simulation process based on the business characteristics of the digital circuit. Waveform data, thus reducing the amount of waveform data generated and saved during simulation and correspondingly reducing simulation time. Compared with conventional digital simulation tools that directly schedule the execution process in the simulation phase to construct signal connection relationships, record waveform information, and output full waveform files, the technical solution of the present disclosure can perform waveform file processing through preprocessing in the compilation phase. Compression and storage have previously greatly reduced the size of files that need to be saved. Combined with business-level feature extraction, redundant information can be removed during the compilation phase. On the premise of avoiding the loss of effective information, the waveform file size has been reduced from the source before performing the compression algorithm, thereby reducing the pressure of encoding and decoding on simulation time and reducing the simulation time accordingly.

In some embodiments, circuit files representing circuits include register transfer level description files. In some embodiments, the hierarchical data set is organized in the form of a hierarchical tree, and the hierarchical data set includes at least one of the following: sequence information representing the serialization of a plurality of signals, a path representing a transmission path of the plurality of signals information, address information corresponding to the plurality of signals, driving information for driving the plurality of signals, and load information for being driven by the plurality of signals. By converting the hierarchical dataset Organized in the form of a hierarchical tree, it is easy to find, modify and save hierarchical data based on individual attributes (such as driver relationships, load relationships, memory addresses, module calls, etc.), and accordingly it is easier to selectively simulate and store signals.

In some embodiments, the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. The compilation unit 802 is further configured to: match the first signal and the second signal with signals in the circuit model set in the register transfer level description file to determine a hierarchical mapping relationship between the first signal and the second signal.

In some embodiments, the simulation unit 804 is further configured to: determine a target signal set based on the hierarchical mapping relationship, the target signal set includes the first signal, and the target signal set does not include the second signal; based on the determined target signal set, The circuit is simulated to selectively generate a target waveform data set in the waveform database, the target waveform data set includes simulated waveform data of the first signal, and the target waveform data set does not include simulated waveform data of the second signal. By establishing a hierarchical mapping relationship between multiple associated signals, the relationship of another signal can be determined based on a single signal, which can avoid the simulation calculation and storage of multiple signals, thereby further reducing simulation time and reducing the storage capacity of simulation signals. .

In some embodiments, the electronic device 800 further includes a receiving unit. The receiving unit is configured to receive a storage time indication for the target signal. The storage unit 806 is further configured to store in the memory a data portion of the time period corresponding to the storage time indication in the simulation waveform data of the target signal in the target waveform data set. By letting the user set the waveforms for the time period to be simulated and stored, the amount of data and time can be further reduced compared to simulation and data storage for the entire period.

In some embodiments, the plurality of signals includes a third signal. The simulation unit 804 is further configured to: simulate the circuit based on the hierarchical data set and the circuit file to generate simulated waveform data for the third signal in the waveform database, where the simulated waveform data for the third signal includes glitch data.

In some embodiments, the glitch data includes a plurality of glitch values for the third signal within a unit time period. The storage unit 806 is further configured to store the plurality of glitch values in the memory in chronological order. In some embodiments, the storage unit 806 is further configured to: determine whether adjacent glitch values among the plurality of glitch values are the same; and if the adjacent glitch values are the same, store any one of the adjacent glitch values in memory without storing another glitch value within an adjacent glitch value. By providing glitch signal recording function, circuit designers can be provided with more accurate and detailed waveform information to determine the accuracy of circuit design.

In some embodiments, the storage unit 806 is further configured to determine whether adjacent glitch values among the plurality of glitch values are the same; and if the adjacent glitch values are the same, store any of the adjacent glitch values in the memory , without storing another glitch value within an adjacent glitch value. Waveform data volume can be further reduced by merging multiple adjacent glitch values into a single glitch value.

In some embodiments, the electronic device 800 further includes an adjustment unit. The adjustment unit is configured to adjust the hierarchical data set based on user input. Adjustments to hierarchical data sets give designers flexibility in circuit verification. In addition, circuit simulation time and waveform signal data volume can be further reduced when designers adjust the hierarchical data set to retain only the signals of interest.

Figure 9 shows a schematic block diagram of an example device 900 that may be used to implement embodiments of the present disclosure. Figure 9 shows a schematic block diagram of an example device 900 that may be used to implement embodiments of the present disclosure. As shown, device 900 includes a computing unit 901 that may be loaded into RAM 903 and/or from storage unit 908 in accordance with computer program instructions stored in random access memory (RAM) and/or read only memory (ROM) 902 Computer program instructions in ROM 902 to perform various appropriate actions and processes. In RAM 903 and/or ROM 902, various programs and data required for operation of device 900 may also be stored. Computing unit 901 and RAM 903 and/or ROM 902 are connected to each other via bus 904 . An input/output (I/O) interface 905 is also connected to bus 904.

Multiple components in device 900 are connected to I/O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of displays, speakers, etc.; storage unit 908, such as magnetic disk, optical disk, etc. ; and communication unit 909, such as a network card, modem, wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information/data with other devices through computer networks such as the Internet and/or various telecommunications networks.

Computing unit 901 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processing processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 901 performs various methods and processes described above, such as method 300. For example, in some embodiments, method 300 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 900 via RAM and/or ROM and/or communication unit 909 . When a computer program is loaded into RAM and/or ROM and executed by computing unit 901, one or more steps of method 300 described above may be performed. Alternatively, in other embodiments, computing unit 901 may be configured to perform method 300 in any other suitable manner (eg, by means of firmware).

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions specified in the flowcharts and/or block diagrams/ The operation is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, laptop disks, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

The embodiments of the present disclosure have been described above. The above description is illustrative, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications, or technical improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims (22)

1. A method for generating and storing waveform data during circuit simulation, including:

   Compiling a circuit file representing a circuit to generate a hierarchical data set for the circuit in a compiled database, the hierarchical data set associated with a plurality of signals at a plurality of nodes in the circuit;

   Simulating the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database configured to provide an interface to access the compiled database ;as well as

   At least a portion of the target waveform data set is stored in memory.
2. The method of claim 1, wherein the hierarchical data set is organized in a hierarchical tree, and the hierarchical data set includes at least one of the following: sequence information representing serialization of the plurality of signals, Path information indicating transmission paths of the plurality of signals, address information corresponding to the plurality of signals, drive information for driving the plurality of signals, and load information for being driven by the plurality of signals.
3. The method according to claim 1 or 2, wherein the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping relationship between the first signal and the second signal. ;as well as

   Generating a hierarchical data set for the circuit in a compiled database includes matching the first signal and the second signal with signals in a circuit model set in a register transfer level description file to determine whether the first signal is and the mapping relationship between the second signal.
4. The method of claim 3, wherein selectively generating the target waveform data set in the waveform database includes:

   Based on the mapping relationship, a target signal set is determined, the target signal set includes the first signal, and the target signal set does not include the second signal; and

   Based on the determined target signal set, the circuit is simulated to selectively generate a target waveform data set in a waveform database, the target waveform data set includes simulated waveform data of the first signal, and the target waveform data set is The waveform data set does not include simulated waveform data of the second signal.
5. The method of any one of claims 1-4, further comprising: receiving a storage time indication for the target signal; and

   wherein storing the at least a portion of the target waveform data set in the memory includes:

   A data portion of a time period corresponding to the storage time indication in the simulated waveform data of the target signal in the target waveform data set is stored in the memory.
6. The method of any one of claims 1-5, wherein the plurality of signals includes a third signal; and

   Selectively generating target waveform data sets in the waveform database includes:

   Based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in a waveform database, wherein the simulated waveform data for the third signal includes glitch data .
7. The method of claim 6, wherein the glitch data includes a plurality of glitch values for the third signal within a unit time period; and

   Storing at least a portion of the target waveform data set in the memory includes storing the plurality of glitch values in the memory in chronological order.
8. The method of claim 7, wherein storing the plurality of glitch values in the memory in chronological order includes:

   Determine whether adjacent glitch values in the plurality of glitch values are the same; and

   If the adjacent glitch values are the same, any one of the adjacent glitch values is stored in the memory without storing the other one of the adjacent glitch values.
9. The method according to any one of claims 1-8, further comprising:

   Based on user input, the hierarchical data set is adjusted.
10. The method of any one of claims 1-9, wherein the circuit file representing the circuit includes a register transfer level description file.
11. A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including a method for executing the method described in any one of claims 1-10. Method instructions.
12. A computer program product comprising a plurality of programs configured to be executed by one or more processors, the plurality of programs including a program for executing any one of claims 1-10 instructions for the method described.
13. An electronic device including:

    one or more processors;

    A memory comprising computer instructions that when executed by the one or more processors of the electronic device cause the electronic device to perform the method of any one of claims 1-8.
14. An electronic device including:

    A compilation unit configured to compile a circuit file used to represent a circuit to generate a hierarchical data set for the circuit in a compilation database, the hierarchical data set being consistent with a plurality of nodes at a plurality of nodes in the circuit. signal correlation;

    a simulation unit configured to simulate the circuit based on the hierarchical data set and the circuit file to selectively generate a target waveform data set in a waveform database, the waveform database being configured to provide an interface to The compiled database is accessed; and

    A storage unit configured to store at least a portion of the target waveform data set in a memory.
15. The electronic device of claim 14, wherein the hierarchical data set is organized in a hierarchical tree, and the hierarchical data set includes at least one of: sequence information representing serialization of the plurality of signals, Path information indicating transmission paths of the plurality of signals, address information corresponding to the plurality of signals, drive information for driving the plurality of signals, and load information for being driven by the plurality of signals. .
16. The electronic device of claim 14 or 15, wherein the plurality of signals includes a first signal and a second signal, and the hierarchical data set includes a hierarchical mapping between the first signal and the second signal. relationship; and

    The compilation unit is further configured to: match the first signal and the second signal with signals in a circuit model set in the register transfer level description file to determine whether the first signal and the second signal are the mapping relationship between them.
17. The electronic device of claim 16, wherein the simulation unit is further configured to:

    Based on the mapping relationship, a target signal set is determined, the target signal set includes the first signal, and the target signal set does not include the second signal; and

    Based on the determined target signal set, the circuit is simulated to selectively generate a target waveform data set in a waveform database, the target waveform data set includes simulated waveform data of the first signal, and the target waveform data set is The waveform data set does not include simulated waveform data of the second signal.
18. The electronic device according to any one of claims 14-17, further comprising: a receiving unit configured to receive the storage time indication for the target signal; and

    The storage unit is further configured to:

    Store in the memory the simulated waveform data of the target signal in the target waveform data set and the The storage time indicates the data portion of the corresponding time period.
19. The electronic device of any one of claims 14-18, wherein the plurality of signals includes a third signal; and

    The simulation unit is further configured to:

    Based on the hierarchical data set and the circuit file, the circuit is simulated to generate simulated waveform data for the third signal in a waveform database, wherein the simulated waveform data for the third signal includes glitch data .
20. The electronic device of claim 19, wherein the glitch data includes a plurality of glitch values for the third signal within a unit time period; and

    The storage unit is further configured to store the plurality of glitch values in the memory in chronological order.
21. The electronic device of claim 20, wherein the storage unit is further configured to:

    Determine whether adjacent glitch values in the plurality of glitch values are the same; and

    If the adjacent glitch values are the same, any one of the adjacent glitch values is stored in the memory without storing the other one of the adjacent glitch values.
22. The electronic device according to any one of claims 14-21, further comprising:

    The adjustment unit is configured to adjust the hierarchical data set based on user input.