CN109598077A - A kind of graphics pipeline device and modeling method based on GPU chip - Google Patents
A kind of graphics pipeline device and modeling method based on GPU chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The embodiment of the invention provides a kind of graphics pipeline devices and modeling method in GPU chip.The GPU graphics chip line device includes task scheduling unit, rasterization unit, coloring units, piece member test cell, texture mapping unit and register cell.The method that the present invention uses is to carry out transaction-level modeling to GPU graphics chip line device module using UML view language, it avoids describing hardware structure using traditional documents form be easy to causeing the inaccuracy of verbal description and ambiguity that the cumbersome circuit signal of hardware bottom layer is also avoided to design simultaneously, it can be designed and developed with the framework of the extensive hardware system of rapid evaluation, the system-level architecture suitable for integrated circuit early stage.
Description
Technical field
The present invention relates to computer hardware modeling technique field more particularly to a kind of figure tube based on GPU chip are traditional thread binding
It sets and modeling method.
Background technique
As that graphically applies is continuously increased, central processing unit (Central Processing is depended merely in early days
Unit, CPU) solution that carries out graphic plotting has been difficult to meet the graphics process demand that achievement and technology increase, figure
Processor (Graphic Processing Unit, GPU) comes into being.From Nvidia in 1999 issue first item GPU product to
The present, the development of GPU technology mainly experienced fixed function flow line stage, separation stainer framework stage, unified stainer frame
Structure stage, graphics capability are constantly promoted, and application field also gradually expands to general-purpose computations neck from initial graphic plotting
Domain.GPU assembly line high speed, parallel feature and flexible programmability, provide for graphics process and universal parallel calculating
Good operation platform.
For be similar to GPU as VLSI chip software/hardware framework, design, how to complete from
Traditional description document is realized to hardware register transmitting stage (Register Transfer Level, RTL) circuit
Across becoming an important, anxious to be resolved problem during engineering practice.
Summary of the invention
The problem of based on background technique, a kind of graphics pipeline device based on GPU chip provided by the invention and
Modeling method is able to solve the IC system framework stage quick representation function, structure the problem of.
In a first aspect, the present invention provides one kind to be based on graphics processing unit GPU (Graph Process Unit, figure
Processing unit) chip graphics pipeline device modeling method, comprising: modeled according to unitive search and transaction-level
(TLM, Transaction Level Modeling) method carries out transaction-level to the graphics pipeline device of the GPU chip and builds
Mould.
Second aspect, the present invention provides a kind of graphics pipeline device based on graphics processing unit GPU chip, the dresses
It sets including task scheduling unit 1, rasterization unit 2, coloring units 3, piece member test cell 4, texture mapping unit 5 and register
Unit 6, in which:
The task scheduling unit 1, realizes the scheduling of vertex rendering order task and fragment data processing task；
The rasterization unit 2 realizes the coordinate transform of vertex data, three-dimensional is cut out and rasterizes function；
The coloring units 3, realize vertex coloring and fragment colouring function；
Described first test cell 4 realizes fragment and cuts test, alpha test, template test and depth test
Function；
The texture mapping unit 5 realizes fragment texture mapping function；
The register cell 6 realizes the buffer status parameter management of figure 3D engine.
Optionally, the task scheduling unit 1, includes the port cmd2SguGraphExport, which passes through
Cmd2SguGraphIf interface is communicated with outside；
The task scheduling unit 1, includes the port jsu2PcieIntPort, which passes through
PcieBackendIntIf interface is communicated with outside；
The task scheduling unit 1 includes the port fragmentExport, the port and the rasterization unit 2
The port fragmentPort carries out connected, is communicated between port by FragmentTaskIf interface；
The task scheduling unit 1 includes the port jsu2UsaPort, with the coloring units 3
The port jsu2UsaExport carries out connected, is communicated between port by ShadeIf interface.
Optionally, the rasterization unit 2, includes the port geu2PcieIntPort, which passes through
PcieBackendIntIf interface is communicated with outside；
The rasterization unit 2 includes the port rasterExport, the port and the coloring units 3
The port rasterPort carries out connected, is communicated between port by RasterIf interface.
Optionally, the coloring units 3, include the port usa2AxiPort, which passes through AxiMasterIf interface
It is communicated with outside；
The coloring units 3, include the port fragTestPort, the port and described first test cell 4
The port fragTestExport carries out connected, is communicated between port by FragmentTestIf interface；
The coloring units 3 include the port texMapPort, the port and the texture mapping unit 5
The port texMapExport carries out connected, is communicated between port by TextureMapIf interface.
Optionally, described first test cell 4, includes the port frameCachePort, port passes through
FrameCacheIf interface is communicated with outside；
Described first test cell 4, includes the port rou2PcieIntPort, port passes through PcieBackendIntIf
Interface is communicated with outside.
Optionally, the texture mapping unit 5, includes the port texCachePort, and port passes through
TextureCacheIf interface is communicated with outside.
Optionally, the register cell 6, includes the port archRegExport, and port passes through
PcieBackendRegIf interface is communicated with outside；
The register cell 6, include jsu2SpmuExport, geu2SpmuExport, usa2SpmuExport,
The port rou2SpmuExport, tau2SpmuExport, by SpmuIf interface respectively with the task scheduling unit 1
Jsu2SpmuPort, the geu2SpmuPort of the rasterization unit 2, the usa2SpmuPort of the coloring units 3, described
The rou2SpmuPort of first test cell 4, the port tau2SpmuPort of the texture mapping unit 5 are connected.
As it can be seen that the graphics pipeline device and modeling method based on GPU chip provided through the invention, is able to solve and is collecting
The problem of at circuit system framework stage quick representation function, structure, compensates for system specification specification and hardware RTL circuit is real
Huge wide gap between existing forms hardware RTL circuit convenient for the top-down continuous refinement of system architecture, assists convenient for software and hardware personnel
Work is adjusted, unnecessary iteration is reduced.GPU graphics chip line device hardware TLM model based on UML, can also be according to figure
Shape view automatic code generating frame.Accessible technical effect includes:
1, using UML Unified Modeling Language, can be got rid of by view conventional text describe document inaccuracy and
Ambiguity, convenient for the exchange of technology between project team member；
2, it is modeled using the function call communication mode transaction-level of TLM, avoids letter cumbersome between hardware circuit module
Number connection description, can quickly to model carry out adaptation；
3, the model through the invention, can be fitted with rapid discovery, assessment GPU large scale integrated circuit hardware structure
System-level architecture for integrated circuit early stage is designed and developed；
4, the model through the invention, exploitation can be provided for the TLM modelling of project later period and is inputted.
Detailed description of the invention
Fig. 1 is the GPU graphics chip line device hardware TLM model structure block diagram the present invention is based on UML.
Specific embodiment
In the following with reference to the drawings and specific embodiments, technical solution of the present invention is clearly and completely stated.Obviously,
The embodiment stated is only a part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention,
Those skilled in the art are not making creative work premise every other embodiment obtained, belong to guarantor of the invention
Protect range.
In the present invention, in order to shorten the huge wide gap realizing from system architecture document to hardware RTL circuit, it is necessary to
The function of entire circuit system, framework are described using a kind of advanced modeling language between the two stages, while again
The many and diverse signal sequence of hardware circuit cannot be fallen into, among gate circuit.
Transaction-level model (Transaction Level Models, TLM) is abstraction level more higher than RTL level, herein
Rank can quickly establish the executable specification of hardware according to the Elementary Function specification of system, quickly create system model.Pass through
Timing details is added wherein, it can be estimated that performance, the structure of searching system of system.
UML (Unified Modeling Language) is also known as Unified Modeling Language or Modeling language, begins at
OMG standard in 1997, it is the graphical language of a support model and software system development, for the institute of software development
There is the stage to provide modelling and visualization support.
Embodiment one
The present invention provides one kind to be based on graphics processing unit GPU (Graph Process Unit, graphics processing unit)
The modeling method of the graphics pipeline device of chip, comprising: according to unitive search and transaction-level modeling (TLM,
Transaction Level Modeling) method, transaction-level modeling is carried out to the graphics pipeline device of the GPU chip.
Optionally, the method also includes:
The Graphic drawing commands and graphing capability order that task scheduling unit (1) receiving host is sent, according to deposit
Vertex data is sent to rasterization unit (2) or coloring by format and vertex data in the Command Line Parsing order of device unit (6)
Unit (3), while operation state is updated to register cell (6)；
The graphic register resource visit order that task scheduling unit (1) receiving host is sent, to register cell
(6) register in is written and read access；
The rasterization unit (2) receives the vertex data from task scheduling unit (1) or coloring units (3), according to
The configuration opposite vertexes data of register cell (6) carry out pel assembling, Plane Crop, perspective projection transformation, the viewport transform, the back side
Blanking, rasterisation calculate, and convert vertex data in visual coordinate system to piece metadata to be shown on two-dimensional screen, and by piece
Metadata is sent to coloring units (3), while operation state is updated to register cell (6)；
The coloring units (3) receive Graphic drawing commands and graphing capability order from task scheduling unit (1), root
According to register cell (6) configuration opposite vertexes data carry out vertex coloring calculating (including texture coordinate calculate, model view become
Change, color calculates), the vertex data in visual coordinate system is converted by the vertex data in geometric space coordinate system, and will top
Point data is sent to rasterization unit (2), while operation state is updated to register cell (6)；
The coloring units (3) receive the piece metadata for coming from rasterization unit (2), according to matching for register cell (6)
It sets progress piece member coloring and calculates (including texture mapping, domain color are cumulative, mist calculates), piece metadata is sent to piece by treated
First test cell (4), while operation state is updated to register cell (6)；
Described first test cell (4) receives the piece metadata for coming from coloring units (3), according to register cell (6)
Configuration carries out cutting test, alpha test, depth test and template test, and sends frame for the piece metadata after passing through is tested
Cache unit is buffered, while operation state is updated to register cell (6)；
The texture mapping unit (5) receives the texture mapping from coloring units (3) and requests, from texture cache unit
It retrieves textures color and carries out texture mapping calculating, the colouring information after textures is returned to coloring units (3), while by operation shape
State is updated to register cell (6)；
The register cell (6), which receives, comes from task scheduling unit (1), rasterization unit (2), coloring units (3), piece
First test cell (4), texture mapping unit (5) operating status more new information.
Embodiment two
The present invention provides a kind of graphics pipeline devices based on graphics processing unit GPU chip, as shown in Figure 1, described
Device includes task scheduling unit 1, rasterization unit 2, coloring units 3, piece member test cell 4, texture mapping unit 5 and deposit
Device unit 6, in which:
The task scheduling unit 1, realizes the scheduling of vertex rendering order task and fragment data processing task；
The rasterization unit 2 realizes the coordinate transform of vertex data, three-dimensional is cut out and rasterizes function；
The coloring units 3, realize vertex coloring and fragment colouring function；
Described first test cell 4 realizes fragment and cuts test, alpha test, template test and depth test
Function；
The texture mapping unit 5 realizes fragment texture mapping function；
The register cell 6 realizes the buffer status parameter management of figure 3D engine.
Optionally, the task scheduling unit 1, includes the port cmd2SguGraphExport, which passes through
Cmd2SguGraphIf interface is communicated with outside；
The task scheduling unit 1, includes the port jsu2PcieIntPort, which passes through
PcieBackendIntIf interface is communicated with outside；
The task scheduling unit 1 includes the port fragmentExport, the port and the rasterization unit 2
The port fragmentPort carries out connected, is communicated between port by FragmentTaskIf interface；
The task scheduling unit 1 includes the port jsu2UsaPort, with the coloring units 3
The port jsu2UsaExport carries out connected, is communicated between port by ShadeIf interface.
Optionally, the rasterization unit 2, includes the port geu2PcieIntPort, which passes through
PcieBackendIntIf interface is communicated with outside；
The rasterization unit 2 includes the port rasterExport, the port and the coloring units 3
The port rasterPort carries out connected, is communicated between port by RasterIf interface.
Optionally, the coloring units 3, include the port usa2AxiPort, which passes through AxiMasterIf interface
It is communicated with outside；
The coloring units 3, include the port fragTestPort, the port and described first test cell 4
The port fragTestExport carries out connected, is communicated between port by FragmentTestIf interface；
The coloring units 3 include the port texMapPort, the port and the texture mapping unit 5
The port texMapExport carries out connected, is communicated between port by TextureMapIf interface.
Optionally, described first test cell 4, includes the port frameCachePort, port passes through
FrameCacheIf interface is communicated with outside；
Described first test cell 4, includes the port rou2PcieIntPort, port passes through PcieBackendIntIf
Interface is communicated with outside.
Optionally, the texture mapping unit 5, includes the port texCachePort, and port passes through
TextureCacheIf interface is communicated with outside.
Optionally, the register cell 6, includes the port archRegExport, and port passes through
PcieBackendRegIf interface is communicated with outside；
The register cell 6, include jsu2SpmuExport, geu2SpmuExport, usa2SpmuExport,
The port rou2SpmuExport, tau2SpmuExport, by SpmuIf interface respectively with the task scheduling unit 1
Jsu2SpmuPort, the geu2SpmuPort of the rasterization unit 2, the usa2SpmuPort of the coloring units 3, described
The rou2SpmuPort of first test cell 4, the port tau2SpmuPort of the texture mapping unit 5 are connected.
Illustratively, the interface service that intermodule communication is included is described as follows:
The task scheduling unit 1 includes the port cmd2SguGraphExport, and port passes through Cmd2SguGraphIf
Interface is communicated with outside.Wherein, Cmd2SguGraphIf interface provides Get_Graph_Draw_Service, Get_
Graph_Func_Service、Get_Graph_Reg_Service、Put_Graph_Draw_Command、Put_Graph_
Function_Code, Put_Graph_Reg_Access service；
The task scheduling unit 1 includes the port jsu2PcieIntPort, and port is connect by PcieBackendIntIf
Mouth is communicated with outside.Wherein, PcieBackendIntIf interface provides Report_Interrupt service；
The task scheduling unit 1 includes the port fragmentExport, with rasterization unit 2
The port fragmentPort carries out connected, is communicated between port by FragmentTaskIf interface.Wherein,
FragmentTaskIf interface provides Get_Fragment_Send_Service and Send_Fragment_Task service；
The task scheduling unit 1 includes the port jsu2UsaPort, the end jsu2UsaExport with coloring units 3
Mouth carries out connected, is communicated between port by ShadeIf interface.Wherein, ShadeIf interface provides Send_
Fragment_Shade_Data and Send_Vertex_Shade_Data service；
The rasterization unit 2 includes the port geu2PcieIntPort, and port passes through PcieBackendIntIf interface
It is communicated with outside.Wherein, PcieBackendIntIf interface provides Report_Interrupt service；
The rasterization unit 2 includes the port rasterExport, with the ports rasterPort of coloring units 3 into
Row is connected, and is communicated between port by RasterIf interface.Wherein, RasterIf interface provides Send_Vertex_
Raster service；
The coloring units 3 include the port usa2AxiPort, and port passes through AxiMasterIf interface and external progress
Communication.Wherein, AxiMasterIf interface provides Request_Bus, Release_Bus, Read_Bus, Write_Bus clothes
Business；
The coloring units 3 include the port fragTestPort, the fragTestExport with piece member test cell 4
Port carries out connected, is communicated between port by FragmentTestIf interface.Wherein, FragmentTestIf interface mentions
Get_Fragment_Test_Service and Send_Fragment_To_Test has been supplied to service；
The coloring units 3 include the port texMapPort, the port texMapExport with texture mapping unit 5
It carries out connected, is communicated between port by TextureMapIf interface.Wherein, TextureMapIf interface provides Get_
Texture_Service and Get_Texture_Data service；
Described first test cell 4 includes the port frameCachePort, port by FrameCacheIf interface with
Outside is communicated.Wherein, FrameCacheIf interface provides Get_Frame_Buffer_Data service；
Described first test cell 4 includes the port rou2PcieIntPort, and port is connect by PcieBackendIntIf
Mouth is communicated with outside.Wherein, PcieBackendIntIf interface provides Report_Interrupt service；
The texture mapping unit 5 includes the port texCachePort, port by TextureCacheIf interface with
Outside is communicated.Wherein, TextureCacheIf interface provides Get_Texture_Data service；
The register cell 6 includes the port archRegExport, port by PcieBackendRegIf interface with
Outside is communicated.Wherein, PcieBackendRegIf interface provides Arch_Reg_Read, Arch_Reg_Write service；
The register cell 6 include jsu2SpmuExport, geu2SpmuExport, usa2SpmuExport,
The port rou2SpmuExport, tau2SpmuExport, by SpmuIf interface respectively with task scheduling unit 1
Jsu2SpmuPort, the geu2SpmuPort of rasterization unit 2, the usa2SpmuPort of coloring units 3, piece member test cell 4
Rou2SpmuPort, texture mapping unit 5 the port tau2SpmuPort be connected.Wherein, SpmuIf interface provides
Report_Exception、Set_Texture_Map_Unit、Set_Vertex_Attribute、Query_Texture_
Enable_Mode、Query_Vertex_Simple_Complex_Mode、Query_Fragment_Simple_Complex_
Mode、Query_Vertex_Attribute_On_Off_Status、Query_Fragment_Attribute_On_Off_
Status、Query_Texture_Interformat、Get_Coordinate_Attribute、Get_Non_Coordinate_
Attribute, Get_Frament_Attribute, Get_Texture_Map_Type, Get_Texture_Object_Id clothes
Business；
As it can be seen that the graphics pipeline device and modeling method based on GPU chip provided through the invention, is able to solve and is collecting
The problem of at circuit system framework stage quick representation function, structure, compensates for system specification specification and hardware RTL circuit is real
Huge wide gap between existing forms hardware RTL circuit convenient for the top-down continuous refinement of system architecture, assists convenient for software and hardware personnel
Work is adjusted, unnecessary iteration is reduced.GPU graphics chip line device hardware TLM model based on UML, can also be according to figure
Shape view automatic code generating frame.Accessible technical effect includes:
1, using UML Unified Modeling Language, can be got rid of by view conventional text describe document inaccuracy and
Ambiguity, convenient for the exchange of technology between project team member；
2, it is modeled using the function call communication mode transaction-level of TLM, avoids letter cumbersome between hardware circuit module
Number connection description, can quickly to model carry out adaptation；
3, the model through the invention, can be fitted with rapid discovery, assessment GPU large scale integrated circuit hardware structure
System-level architecture for integrated circuit early stage is designed and developed；
4, the model through the invention, exploitation can be provided for the TLM modelling of project later period and is inputted.
Finally it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that；It still may be used
To modify to the technical solution that foregoing embodiments are recorded or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit and model of technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (9)
1. a kind of modeling method of the graphics pipeline device based on graphics processing unit GPU chip, it is characterised in that:
TLM method is modeled according to unitive search and transaction-level, thing is carried out to the graphics pipeline device of the GPU chip
Grade of being engaged in modeling.
2. the method according to claim 1, wherein the method is applied to be based on graphics processing unit GPU core
The graphics pipeline device of piece, described device include task scheduling unit (1), rasterization unit (2), coloring units (3), piece member
Test cell (4), texture mapping unit (5) and register cell (6), the method also includes:
The Graphic drawing commands and graphing capability order that task scheduling unit (1) receiving host is sent, according to register list
Format and vertex data in the Command Line Parsing order of first (6), are sent to rasterization unit (2) or coloring units for vertex data
(3), register cell (6) while by operation state are updated to；
The graphic register resource visit order that task scheduling unit (1) receiving host is sent, in register cell (6)
Register be written and read access；
The rasterization unit (2) receives the vertex data from task scheduling unit (1) or coloring units (3), according to deposit
The configuration opposite vertexes data progress pel assembling of device unit (6), Plane Crop, perspective projection transformation, the viewport transform, the back side disappear
Hidden, rasterisation calculates, and converts vertex data in visual coordinate system to piece metadata to be shown on two-dimensional screen, and piece is first
Data are sent to coloring units (3), while operation state is updated to register cell (6)；
The coloring units (3) receive Graphic drawing commands and graphing capability order from task scheduling unit (1), according to posting
The configuration opposite vertexes data of storage unit (6) carry out vertex coloring calculating (including texture coordinate calculating, model view transform, face
Color calculates), the vertex data in visual coordinate system is converted by the vertex data in geometric space coordinate system, and by vertex data
It is sent to rasterization unit (2), while operation state is updated to register cell (6)；
The coloring units (3) receive the piece metadata for coming from rasterization unit (2), according to the configuration of register cell (6) into
The coloring of row piece member calculates (including texture mapping, domain color are cumulative, mist calculates), and by treated, piece metadata is sent to the survey of piece member
It tries unit (4), while operation state is updated to register cell (6)；
Described first test cell (4) receives the piece metadata for coming from coloring units (3), according to the configuration of register cell (6)
Cutting test, alpha test, depth test and template test are carried out, and the piece metadata after passing through will be tested and send frame buffering
Cache unit, while operation state is updated to register cell (6)；
The texture mapping unit (5) receives the texture mapping from coloring units (3) and requests, and retrieves from texture cache unit
Textures color carries out texture mapping calculating, the colouring information after textures is returned to coloring units (3), while more by operation state
Newly to register cell (6)；
The register cell (6) receives surveys from task scheduling unit (1), rasterization unit (2), coloring units (3), piece member
Try the operating status more new information of unit (4), texture mapping unit (5).
3. a kind of graphics pipeline device based on graphics processing unit GPU chip, it is characterised in that: described device includes task tune
Spend unit (1), rasterization unit (2), coloring units (3), piece member test cell (4), texture mapping unit (5) and register list
First (6), in which:
The task scheduling unit (1), realizes the scheduling of vertex rendering order task and fragment data processing task；
The rasterization unit (2), realizes the coordinate transform of vertex data, three-dimensional is cut out and rasterizes function；
The coloring units (3), realize vertex coloring and fragment colouring function；
Described first test cell (4) realizes fragment and cuts test, alpha test, template test and depth test function
Energy；
The texture mapping unit (5), realizes fragment texture mapping function；
The register cell (6), realizes the buffer status parameter management of figure 3D engine.
4. graphics pipeline device according to claim 2, it is characterised in that:
The task scheduling unit (1), includes the port cmd2SguGraphExport, which passes through Cmd2SguGraphIf
Interface is communicated with outside；
The task scheduling unit (1), includes the port jsu2PcieIntPort, which passes through PcieBackendIntIf
Interface is communicated with outside；
The task scheduling unit (1), includes the port fragmentExport, the port and the rasterization unit (2)
The port fragmentPort carries out connected, is communicated between port by FragmentTaskIf interface；
The task scheduling unit (1), includes the port jsu2UsaPort, with the coloring units (3)
The port jsu2UsaExport carries out connected, is communicated between port by ShadeIf interface.
5. graphics pipeline device according to claim 2, it is characterised in that:
The rasterization unit (2), includes the port geu2PcieIntPort, which is connect by PcieBackendIntIf
Mouth is communicated with outside；
The rasterization unit (2), includes the port rasterExport, the port and the coloring units (3)
The port rasterPort carries out connected, is communicated between port by RasterIf interface.
6. graphics pipeline device according to claim 2, it is characterised in that:
The coloring units (3), include the port usa2AxiPort, which passes through AxiMasterIf interface and external progress
Communication；
The coloring units (3), include the port fragTestPort, the port and described first test cell (4)
The port fragTestExport carries out connected, is communicated between port by FragmentTestIf interface；
The coloring units (3) include the port texMapPort, the port and the texture mapping unit (5)
The port texMapExport carries out connected, is communicated between port by TextureMapIf interface.
7. graphics pipeline device according to claim 2, it is characterised in that:
Described first test cell (4) includes the port frameCachePort, and port is by FrameCacheIf interface and outside
Portion is communicated；
Described first test cell (4), includes the port rou2PcieIntPort, port is connect by PcieBackendIntIf
Mouth is communicated with outside.
8. graphics pipeline device according to claim 2, it is characterised in that:
The texture mapping unit (5) includes the port texCachePort, and port is by TextureCacheIf interface and outside
Portion is communicated.
9. graphics pipeline device according to claim 2, it is characterised in that:
The register cell (6), includes the port archRegExport, port by PcieBackendRegIf interface with
Outside is communicated；
The register cell (6), include jsu2SpmuExport, geu2SpmuExport, usa2SpmuExport,
The port rou2SpmuExport, tau2SpmuExport, by SpmuIf interface respectively with the task scheduling unit (1)
Jsu2SpmuPort, the geu2SpmuPort of the rasterization unit (2), the usa2SpmuPort of the coloring units (3), institute
The port tau2SpmuPort of the rou2SpmuPort, the texture mapping unit (5) that state piece member test cell (4) are connected.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN112233159B (en) * | 2020-09-23 | 2021-07-16 | 华夏芯（北京）通用处理器技术有限公司 | Texture processing method and device |
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| CN115719047A (en) * | 2022-11-14 | 2023-02-28 | 沐曦集成电路(上海)有限公司 | Joint simulation system based on waveform GPU |
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