CN101963934A - Method for debugging 8051 core-based system on chip (SOC) on line - Google Patents
Method for debugging 8051 core-based system on chip (SOC) on line Download PDFInfo
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Abstract
The invention relates to a method for debugging an 8051 core-based system on chip (SOC) on line, and belongs to the technical field of integrated circuit design. On-line debugging software on a personal computer (PC) finishes communication with an asynchronous serial interface in the SOC through a serial line so as to realize on-line debugging. The system comprises the on-line debugging software on the PC, an RS232 conversion circuit and the 8051 core-based SOC. The method realizes the 51 instruction analysis, breakpoint processing, operation processing and content debugging of the SOC. Software codes are debugged on line by a few data lines after the mass production of chips is realized, so that the debugging work of the system is greatly simplified, the debugging time is shortened, the function optimization of the system is facilitated and the fault tolerance of the system is enhanced. Meanwhile, the scheme is simple and reliable, avoids using a logic analyzer and automatic test equipment to cause high cost, and can be applied to various SOCs taking an 8051 core as a control core.
Description
Technical field
The present invention relates to a kind of on-line debugging method, belong to the integrated circuit (IC) design technical field based on 8051 SOC (system on a chip) of examining.
Background technology
Along with the development of SIC (semiconductor integrated circuit), the scope of integrated circuit (IC) design not only concentrates on DRAM, the product of MPU and ASIC class, and (System on Chip, SOC) design becomes the emphasis of present integrated circuit (IC) design to SOC (system on a chip) gradually.The technology of other system driving class has been inherited in the SOC design, is the very wide high complexity of a kind of scope, high value semiconductor product.It generally is defined as microprocessor, Simulation with I P nuclear, digital IP kernel and storer (perhaps sheet external memory control interface) is integrated on the one chip.It is the inexorable trend of integrated circuit technique development.Reducing design cost and improving level of integrated system is the main target of SOC.Realize SOC cheaply, need to adopt IP kernel to reuse and, emphasize the consistance that silicon is realized, generally adopt new circuit and system architecture based on the designing technique of platform.Based on the design of platform be a kind of can reach system reuse at utmost towards integrated method for designing, can share IP kernel exploitation and system integration achievement.And in SOC design link now, test and validation becomes link complicated, the most consuming time in the SOC design cycle.
At present, more and more control the SOC chip design of class and come out, be applied in tame electric control, field of consumer electronics.System-on-chip designs based on 8051 nuclear platforms has very big application space at present on market.How to improve based on the test of 8051 SOC (system on a chip) of examining and the efficient of checking, improve test coverage, make chip, become research emphasis making moderate progress aspect yield rate, reliability, the cost.
After a plurality of IP kernels, storer and logic, analogue unit concentrate on a system, there has not been direct mode to remove to visit inner signal.The mechanical testability of the inner some logical ORs of circuit unit reduces not even possibility greatly, and processor can not go to replace with emulator again and debug.At the uniqueness of SOC design, the final purpose of various debugging mainly is to improve the observability and the debug time of chip internal point.Present SOC (system on a chip) is carried out adjustment method and is mainly contained:
Method one: utilize " tying up equipment " (Bond-out device) to draw the internal signal of SOC product.This method will change the SOC indoor design, causes system to have than more number of pins in the original design.The pin of these increases is mainly used in the signal of observing SOC inside, and the debugging support to software development is provided.This " tying up out equipment " needs the number of pins of increase many more along with the increase of system design scale, obviously be not suitable in extensive SOC design.
Method two: along with SOC design integrated level is more and more higher, design is debugged the SOC chip by limited pin at the debugging interface of SOC (system on a chip) special use, and this method has become the trend of Future Development.
As at " a kind of software-hardware synergism SOC debugging interface " (Liu Yang based on JTAG, " microelectronics and computing machine ", 2007 the 24th 34 pages-37 pages of o. 11ths of volume) point out in the literary composition, but it is a kind of based on debug system on the software-hardware synergism sheet of JTAG to be with the MIPS processor that example has proposed in the literary composition.This system architecture complexity need design the JTAG module of occupying big system area resource in SOC, the SOC that the scale that is applicable to is bigger is for inapplicable as the SOC that with 51 nuclears serves as the processing core.
Summary of the invention
For overcoming defective and the deficiency that exists in the prior art, the invention provides a kind of SOC (system on a chip) on-line debugging method based on 8051 nuclears, adopt the serial row communication pin of 8051 nuclears that the SOC chip is debugged, improved the observability of chip circuit internal point, the reason that the function of being convenient to find out hardware or software and the function of design code do not conform to, debug.
Technical scheme of the present invention is as follows:
A kind of on-line debugging method based on 8051 SOC (system on a chip) of examining, with the SOC (system on a chip) of 8051 core processors as application platform, this system comprises host computer (PC), 232 level shifting circuits and SOC (system on a chip), this SOC (system on a chip) comprises 8051 core processors, storer or external memory interface, clock-reset circuit and asynchronous serial communication module, and the clock-reset circuit provides clock and reset signal for SOC (system on a chip); 8051 core processors link to each other with storer or external memory interface, clock-reset circuit and asynchronous serial communication module respectively by data line, address wire and read-write control lead-in wire; Host computer (PC) by the computing machine serial line interface, utilize serial data line to be connected on 232 level shifting circuits, carry out level conversion through 232 level shifting circuits, its output terminal is connected on the serial line interface of SOC (system on a chip), this method step is as follows:
(1) debug system design:
(1) in 8051 core processors of SOC (system on a chip), utilize hardware design language according to the asynchronous serial communication module of RS232 communication protocol foundation based on the RS232 serial communication protocol;
(2) host computer (PC) is set up the Monitor-51 Integrated Development Environment, as online monitoring system, the Monitor-51 system of Keil company is installed, and this development environment comprises instruction analysis module, breakpoint processing module, operation module, the single step run module of command analysis module, 51 series monolithics; Debugging PC serial communication interface guarantees that serial line interface can operate as normal;
(3) create 232 level shifting circuits;
(4) at the interface protocol and the system monitor that will download to the program file interpolation Monitor-51 in the chip, the program of moving on the SOC (system on a chip) is downloaded in the on-chip memory by programmable device;
(2) debugging:
By Serial Port Line host computer is connected with 232 change-over circuits, serial transmission signal, the received signal of the output of 232 level shifting circuits are connected on the SOC chip serial communication interface (sending signal, received signal) of having downloaded program, utilize Monitor-51 that system is debugged, rely on program breakpoint, single step run method, observing system test platform result on the Monitor-51 operation interface, function contrast with the design prediction, determine software or hardware error, debugging normally moves or finds out chip design mistake place up to system repeatedly.
The application platform of proposition method is among the present invention: based on the SOC (system on a chip) of 8051 core processors, can comprise storer (or external memory interface), clock-reset module.
Fig. 1 is this structural representation of realizing embodiment based on the technology of the on-chip system debug method of 8051 nuclears.As shown in Figure 1, this debug system comprises PC, 232 level shifting circuits, SOC system three parts composition.Debug system on the PC is connected on 232 level shifting circuits through Serial Port Line by serial ports, finishes the level conversion of serial communication signal (sending signal, received signal).232 output ground serial communication signals are connected by transmission, received signal with the SOC system, and three parts are coordinated mutually, and co-operation is finished debugging work.Specific embodiments is as follows:
PC among the present invention is the core place of finishing debugging as the host computer of system debug.PC need be equipped with Keil software, and this software provides powerful in-circuit emulation debugger Monitor-51, by an Integrated Development Environment these is partly combined.Operation Monitor-51 needs Pentium or above CPU, 16MB or more RAM, 20M above idle hard drive space, WIN98, NT, WIN2000, WINXP operating system.Require PC need possess serial line interface simultaneously.In debug process, serial line interface promptly is the tie that PC is connected with SOC (system on a chip) SOC.
The purpose of creating 232 level shifting circuits is because RS232 interface level and Transistor-Transistor Logic level are incompatible, thus relate to this level shifting circuit, in order to finish the mutual conversion between computer level and the SOC level.
SOC (system on a chip) SOC among the present invention serves as the control core with 51 nuclears, is made up of storer, asynchronous serial communication module.Can pass through the function of software setting baud rate, full-duplex/half-duplex communication conventional asynchronous serial communication module by the asynchronous serial communication module of 51 nuclear control.Transmission signal pins (Tr), the received signal pin (Re) of being drawn by this module is connected respectively to the received signal pin that 232 level shifting circuits draw and sends on the signal pins, thereby finishes docking of PC and SOC (system on a chip) SOC.Need to utilize programmable device that the compiled working procedure that has watchdog routine is downloaded in the SOC (system on a chip) simultaneously, make system works.
At last, by Serial Port Line host computer and the SOC chip of having downloaded program are connected, utilize command analysis module, the instruction analysis module of 51 series monolithics, breakpoint processing module, operation module, the single step run module of Keil that system is debugged.The test target of debug system is SOC chip and chip periphery environment, comprises target SOC, other design cells of storer.The software programming language can adopt c language, assembly language or hardware description language, according to the complexity of debugging software, realizes debugging coverage rate adjustable size.Determine software or hardware error according to program breakpoint, debugging normally moves up to system repeatedly.
The present invention is in the SOC debug processs based on 8051 nuclears, and need not increases too much pin, utilizes that existing Keil integrating and developing platform is integrated finishes system debug, has saved time and manpower, simply and easily the unmatched problem of resolution system software and hardware.
Description of drawings
Fig. 1 realizes block diagram for hardware of the present invention.Wherein: 1 is online monitoring system; 2 is PC; 3 is 232 level shifting circuits; 4 is the clock-reset circuit; 5 is 8051 nuclear control devices; 6 is storer; 7 are the asynchronous serial communication module.
Embodiment
Below in conjunction with drawings and Examples the present invention is further specified, but be not limited thereto.
Embodiment:
A kind of on-line debugging method based on 8051 SOC (system on a chip) of examining, as shown in Figure 1, with the SOC (system on a chip) of 8051 core processors as application platform, this system comprises host computer (PC) 2,232 level shifting circuit 3 and SOC (system on a chip), this SOC (system on a chip) comprises 8051 core processors 5, storer 6, clock-reset circuit 4 and asynchronous serial communication module 7, and clock-reset circuit 4 provides clock and reset signal for SOC (system on a chip); 8051 core processors 5 link to each other with storer 6, clock-reset circuit 4 and asynchronous serial communication module 7 respectively by data line, address wire and read-write control lead-in wire; Host computer (PC) 2 by the computing machine serial line interface, utilize serial data line to be connected on 232 level shifting circuits 3, carry out level conversion through 232 level shifting circuits 3, its output terminal is connected on the serial line interface of SOC (system on a chip), this method step is as follows:
(1) debug system design:
(1) in 8051 core processors 5 of SOC (system on a chip), utilize hardware design language according to the asynchronous serial communication module of RS232 communication protocol foundation based on the RS232 serial communication protocol;
(2) host computer (PC) 2 is set up the Monitor-51 Integrated Development Environment, as online monitoring system 1, the Monitor-51 system of Keil company is installed, and this development environment comprises instruction analysis module, breakpoint processing module, operation module, the single step run module of command analysis module, 51 series monolithics; Debugging PC 2 serial communication interfaces guarantee that serial line interface can operate as normal;
(3) create 232 level shifting circuits 3;
(4) at the interface protocol and the system monitor that will download to the program file interpolation Monitor-51 in the chip, the program of moving on the SOC (system on a chip) is downloaded in the on-chip memory 6 by programmable device;
(2) debugging:
By Serial Port Line host computer 2 is connected with 232 change-over circuits 3, serial transmission signal, the received signal of 3 outputs of 232 level shifting circuits are connected on the SOC chip serial communication interface (sending signal, received signal) of having downloaded program, utilize Monitor-51 that system is debugged, rely on program breakpoint, single step run method observing system test platform result on the Monitor-51 operation interface, function contrast with the design prediction, determine software or hardware error, debugging normally moves or finds out chip design mistake place up to system repeatedly.
(this chip system data sees patent " SOC chip of oiling machine control system " for details to above embodiment at the tax control fuel oil adding machine control system SOC chip that with Synopsys DW8051 nuclear serves as the control core, application number 200910014565) verifies on, and achieve success.The present invention has adopted the tradition 8051 asynchronous serial communication module interfaces that possessed---send signal and received signal, two data lines have been finished the system communication of on-line debugging system and SOC in the host computer, thereby utilize the power of Monitor-51, be implemented in on-line debugging software code after the chip volume production, this has just simplified system debug work greatly, shorten debug time, helped the optimization system function, strengthened the fault-tolerance of system.Simultaneously, scheme is simple and reliable, has avoided employing logic analyser, ATE (automatic test equipment) high cost, and can be applied in 8051 nuclears is in all kinds of SOC system of basic platform.
Claims (1)
1. on-line debugging method of SOC (system on a chip) based on 8051 nuclears, with the SOC (system on a chip) of 8051 core processors as application platform, this system comprises host computer, 232 level shifting circuits and SOC (system on a chip), this SOC (system on a chip) comprises 8051 core processors, storer or external memory interface, clock-reset circuit and asynchronous serial communication module, and the clock-reset circuit provides clock and reset signal for SOC (system on a chip); 8051 core processors link to each other with storer or external memory interface, clock-reset circuit and asynchronous serial communication module respectively by data line, address wire and read-write control lead-in wire; Host computer by the computing machine serial line interface, utilize serial data line to be connected on 232 level shifting circuits, carry out level conversion through 232 level shifting circuits, its output terminal is connected on the serial line interface of SOC (system on a chip), this method step is as follows:
(1) debug system design:
(1) in 8051 core processors of SOC (system on a chip), utilize hardware design language according to the asynchronous serial communication module of RS232 communication protocol foundation based on the RS232 serial communication protocol;
(2) host computer is set up the Monitor-51 Integrated Development Environment, as online monitoring system, the Monitor-51 system of Keil company is installed, and this development environment comprises instruction analysis module, breakpoint processing module, operation module, the single step run module of command analysis module, 51 series monolithics; Debugging PC serial communication interface guarantees that serial line interface can operate as normal;
(3) create 232 level shifting circuits;
(4) at the interface protocol and the system monitor that will download to the program file interpolation Monitor-51 in the chip, the program of moving on the SOC (system on a chip) is downloaded in the on-chip memory by programmable device;
(2) debugging:
By Serial Port Line host computer is connected with 232 change-over circuits, serial transmission signal, the received signal of the output of 232 level shifting circuits are connected on the SOC chip serial communication interface of having downloaded program, utilize Monitor-51 that system is debugged, rely on program breakpoint, single step run method, observing system test platform result on the Monitor-51 operation interface, function contrast with the design prediction, determine software or hardware error, debugging normally moves or finds out chip design mistake place up to system repeatedly.
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Cited By (11)
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| CN102306137A (en) * | 2011-08-16 | 2012-01-04 | 苏州瀚瑞微电子有限公司 | Method for simulating on-chip system bus by utilizing serial communication |
| CN102662811A (en) * | 2012-03-31 | 2012-09-12 | 电子科技大学 | Method for realizing online debugging on application codes of 51 soft core |
| CN102831042A (en) * | 2012-06-26 | 2012-12-19 | 珠海市杰理科技有限公司 | System for on-line debugging single chip microcomputer and method of system |
| CN104331350A (en) * | 2014-09-29 | 2015-02-04 | 福建联迪商用设备有限公司 | Method and device for debugging serial port of IC (Integrated Circuit) card electronic equipment |
| CN104391770A (en) * | 2014-10-23 | 2015-03-04 | 山东维固信息科技股份有限公司 | Online debugging and upper computer communication module of SOC (system-on-chip) chip for embedded data security system |
| CN104598417A (en) * | 2015-01-04 | 2015-05-06 | 硅谷数模半导体（北京）有限公司 | Serial port transmitting method and device based on on-chip system |
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| CN106776433A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of debugging unit in microcontroller chip |
| CN107608923A (en) * | 2017-09-20 | 2018-01-19 | 广东欧珀移动通信有限公司 | The processing method and Related product of test |
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| CN102306137A (en) * | 2011-08-16 | 2012-01-04 | 苏州瀚瑞微电子有限公司 | Method for simulating on-chip system bus by utilizing serial communication |
| CN102662811A (en) * | 2012-03-31 | 2012-09-12 | 电子科技大学 | Method for realizing online debugging on application codes of 51 soft core |
| CN102662811B (en) * | 2012-03-31 | 2014-08-13 | 电子科技大学 | Method for realizing online debugging on application codes of 51 soft core |
| CN102831042A (en) * | 2012-06-26 | 2012-12-19 | 珠海市杰理科技有限公司 | System for on-line debugging single chip microcomputer and method of system |
| CN104331350B (en) * | 2014-09-29 | 2017-12-08 | 福建联迪商用设备有限公司 | A kind of method and device of IC-card electronic equipment AccessPort |
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| CN104391770A (en) * | 2014-10-23 | 2015-03-04 | 山东维固信息科技股份有限公司 | Online debugging and upper computer communication module of SOC (system-on-chip) chip for embedded data security system |
| CN104598417B (en) * | 2015-01-04 | 2018-03-23 | 硅谷数模半导体（北京）有限公司 | Serial ports sending method and device based on on-chip system |
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| CN104898546B (en) * | 2015-05-06 | 2017-07-14 | 浙江中控研究院有限公司 | A kind of PLC on-line debugging system and method based on SOC |
| CN104898546A (en) * | 2015-05-06 | 2015-09-09 | 浙江中控研究院有限公司 | PLC (Programmable Logic Controller) on-line debugging system and method based on SOC (System On Chip) |
| CN106776433A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of debugging unit in microcontroller chip |
| CN107608923A (en) * | 2017-09-20 | 2018-01-19 | 广东欧珀移动通信有限公司 | The processing method and Related product of test |
| CN107894936A (en) * | 2017-11-13 | 2018-04-10 | 重庆首亨软件有限公司 | A kind of single-chip microcomputer test software |
| CN115454881A (en) * | 2022-11-10 | 2022-12-09 | 北京红山微电子技术有限公司 | Debugging system and debugging method of RISC-V architecture |
| CN115454881B (en) * | 2022-11-10 | 2023-03-03 | 北京红山微电子技术有限公司 | Debugging system and debugging method of RISC-V architecture |
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