CN113609807B - IP core for replacing logic device to realize JTAG bridge exchange function - Google Patents

Abstract

The invention discloses an IP core for replacing a logic device to realize JTAG bridge conversion function, which can reduce hardware resource overhead and improve resource utilization rate. The invention is realized by the following technical scheme: firstly, defining three working states of IP core software and functions realized in each working state; then, an internal component block diagram of the IP core software and a connection relation and a function description of each component are given. In the state of waiting for the address, JBIP software follows the state change of the boundary scanning signal on the boundary scanning test bus and processes the addressing instruction, after the address is matched, the JBIP software enters an address selection state, and in the address selection state, the JBIP software responds to and processes various test instructions; the control of the JTAG bus is converted into the control of a local scanning port LSP in the tested module, the SCANSTA112 chip is replaced to realize the JTAG bridge function, and the hardware resource expense brought by a special chip is reduced.

Description

IP core for replacing logic device to realize JTAG bridge exchange function

Technical Field

The invention relates to an IP core for replacing a logic device to realize a JTAG bridge exchange function, in particular to an IP core for replacing a SCANSTA112 chip to realize the JTAG bridge function.

Background

Today, microelectronics have entered the Very Large Scale Integration (VLSI) era. With the miniaturization of chip circuits and the development of Surface Mount Technology (SMT) and circuit board assembly technology, conventional testing techniques face significant challenges. Under such circumstances, in order to improve testability of circuits and systems, the Joint Test Action Group (JTAG) proposed a new board test method, boundary scan test, in 1987 and accepted by IEEE in 1990, forming the IEEE1149.1 standard, also known as the JTAG standard [1]. This technique replaces the traditional "physical probes" with completely new "virtual probes" to improve the testability of circuits and systems. Due to the rapid development of new technology and new technology in the fields of microelectronics and computers, digital chips of DSP, PPC and FPGA are widely applied to an avionics comprehensive modular digital operation platform. The traditional physical probe type detection method cannot completely meet the requirements of board card integrity test and fault positioning during module acceptance, delivery and maintenance. In addition, the avionics system digital operation platform adopts a highly integrated and universal modular design, modules are interconnected and communicated through an RIO high-speed bus, a CAN bus and LVCOMS discrete lines of a rack backboard, and the system is difficult to locate a fault to a single module node through a BIT means after the inter-module interconnection communication fault occurs in an external field. The 'virtual electronic probe function' peculiar to the boundary scan test technology provides an effective solution for solving the problems, and the detection and the accurate positioning of chip open circuit, short circuit and cold solder joint faults can be realized by adding a scanning unit between the internal logic of the digital chip and a peripheral pin. Because of the good versatility of the JTAG standard, many IC companies now provide IC chips supporting boundary scan mechanism, and even some FPGA and CPLD chips use this technology. At present, the boundary scan test has formed a complete IEEE1149 series standard, and very large scale integrated circuits newly developed by global large-scale semiconductor manufacturers, such as CPUs, DSPs and FPGAs, all support the boundary scan test mechanism. The boundary scan test technology is widely applied to foreign aviation and aerospace equipment.

JTAG is an abbreviation of Joint Test Action Group (Joint Test Action Group) and is a common name in standard 1149.1 of IEEE entitled standard Test access port and boundary scan architecture. This standard is used to verify the functionality of the printed circuit board as designed and tested. JTAG was formally standardized by IEEE documents 1149.1-1990, and supplementary documents were added to describe the Boundary Scan Description Language (BSDL) in 1994. Since then, this standard has been widely adopted by electronic enterprises worldwide. Boundary scan is almost synonymous with JTAG. The JTAG standard is the IEEE1149.1 standard. Chips supporting the JTAG standard are attached with a specific BSDL (Boundary Scan Description Language) Description file. The BSDL language is a subset of the hardware description language (VHDL). The device describes the boundary scanning characteristics of the chip, is used for communicating the relationship between manufacturers, users and test tools, and provides related information for an automatic test pattern generation tool and a specific circuit board detection; test logic defined by the JYAG standard may be generated with the support of BSDL files. The BSDL file may be combined with software tools for test generation, result analysis, and fault diagnosis.

The Joint Test Action Group JTAG (Joint Test Action Group) drafts the Boundary Scan Test BST (Boundary Scan Testing) specification, which specifies a Test Access Port (TAP) and a Boundary Scan structure for digital integrated circuits, solving some Test problems due to high integration of digital circuits. It also provides a method of accessing and controlling an on-chip internal emulation (ICE) module, which typically includes functionality for internal scanning and self-testing, which may well support the development of integrated circuits. In the JTAG standard, registers are classified into two major categories, a Data Register (DR-Data Register) and an Instruction Register (IR-Instruction Register), and a boundary scan chain Register is an important Data Register, and the boundary scan chain can be used to observe and control the input and output of a chip. The instruction register is used to implement control of the data register. The basic idea of the boundary scan technique is to add a shift register cell near the input and output pins of the chip. By the boundary scanning register units, observation and control of chip input and output signals can be realized. In addition, the Boundary Scan (shift) register units near the input/output pins of the chip can be connected to each other to form a Boundary Scan Chain (Boundary-Scan Chain) around the chip. A typical chip will provide several independent boundary scan chains to implement the complete test function. Composing similar technologies into smaller local scan links can reduce complexity and improve debug and fault isolation. SCANSTA111/112 provides a simple, straightforward and highly flexible method-an isolated scan link to simplify programming. The standard JTAG interface defines some of the following signal pins: TMS: test mode select signal, input, IEEE1149.1 standard mandate requirements. TCK: test clock signal, input, IEEE1149.1 standard mandates. TDI: test data input signal, input, IEEE1149.1 standard mandates requirements. TDO: and outputting a test data output signal, and performing the mandatory requirement of the IEEE1149.1 standard. TRST: the internal TAP state machine reset signal, input, IEEE1149.1 standard does not mandate that the TAP Controller may also be reset by the TMS. STCK: the clock return signal is not mandatory by the IEEE1149.1 standard. DBGRQ: the IEEE1149.1 standard does not mandate control signals for operating conditions on the target board. The TAP state machine has 16 synchronous states, and the TMS signal is effective in sampling at the rising edge of TCK. Regardless of the state of the TAP state machine, the TAP will enter the Test-Logic-Reset state as long as the TMS signal is kept high on the rising edges of 5 consecutive TCK signals, and if the TMS signal is always high, the TAP will be kept in the Test-Logic-Reset state, otherwise the TRST signal can also force the TAP to enter the Test-Logic-Reset state. The TAP in the Test-Logic-Reset state is switched to the Run-Test-Idle state if the TMS signal is at a low level at the rising edge of the next TCK. Run-Test-Idle running Test Idle state Run-Test-Idle is the TAP state machine scan operation Idle state, and if the TMS signal is always low, the TAP will remain in the TRun-Test-Idle state. When the TMS signal is high on the rising TCK edge, the TAP state machine will enter the Select-DR-Scan state. Select-DR-Scan Select data register Scan state Select-DR-Scan is a temporary state of the TAP state machine, and the boundary Scan register BSR maintains their previous state. When the TMS signal is at low level at the next rising edge of TCK, the TAP state machine enters the Capture-DR state, and the scanning operation of a boundary scanning register is initialized at the same time. If the TMS signal is high on the next TCK rising edge, the TAP state machine will enter the Select-IR-Scan state. Capture-DR captures data register state. If the TAP state machine is in the Capture-DR state and the current instruction is a SAMPLE/PRELOAD instruction, the boundary Scan register BSR captures data at the input pin on the rising edge of the TCK signal. If it is not a SAMPLE/PRELOAD instruction at this time, then the BSRs keep their previous values and the value of the BSR is placed in a shift register connected between the TDI and TDO pins. In the Capture-DR state, the instruction is not changed. If the TMS signal is high on the next TCK rising edge, TAP enters the Exit1-DR state. If the TMS signal is low on the next TCK rising edge, the TAP enters the Shift-DR state. In the Shift-DR Shift data register state, at the rising edge of each TCK, the TDI-Shift register-TDO serial channel shifts one bit to the right, the data of TDI is shifted into the Shift register, and the Shift register shifts to the TDO pin closest to TDO. In the Shift-DR state, the instruction is not changed. If the TMS signal is high on the next TCK rising edge, TAP enters the Exit1-DR state. The TAP is always on the shift operation if the TMS signal is low. Exit1 from Exit1-DR out of data register state 1.Exit1-DR is a temporary state of the TAP state machine, if the TMS signal is at high level at the next TCK rising edge, the TAP enters into Update-DR state; if the TMS signal is low on the next TCK rising edge, the TAP enters the Pause-DR state. In the Exit1-DR state, the instruction is not altered. The Pause-DR data register state Pause-DR state allows the TAP state machine to temporarily halt the shift operation of the TDI-shift register-TDO serial channel. In the Pause-DR state, the instruction is not changed. If the TMS signal is at high level at the next TCK rising edge, the TAP enters an Exit2-DR state; the TAP remains in the suspend state if the TMS signal is low. Exit2-DR exits the data register state 2Exit2-DR is also a temporary state of the TAP state machine, if the TMS signal is at a high level at the next TCK rising edge, the TAP enters an Update-DR state, and the scanning operation is finished; if the TMS signal is low on the next TCK rising edge, the TAP re-enters the Shift-DR state. In the Exit2-D state, the instruction is not changed. Under normal conditions, the value of the boundary scan register BSR is latched in the parallel output pins to avoid changing the value of the BSR when a shift operation is performed under the EXTEST or SAMPLE/PRELOAD commands. When the BSR register is selected when in the Update-DR state, the value in the shift register will be latched into the BSR register's parallel output pin on the falling edge of TCK. In the Update-DR state, the instruction is not changed. If the TMS signal is at high level at the next rising edge of the TCK, the TAP enters a Select-DR-Scan state; if the TMS signal is low on the next TCK rising edge, the TAP enters the Run-Test-Idle state. Select-IR-Scan Select instruction register Scan state Select-IR-Scan is a temporary state of the TAP state machine. If the TMS signal is low on the next rising TCK edge, the TAP state machine enters the Capture-IR state and a scan operation to the instruction register is simultaneously initiated. If the TMS signal is high on the next TCK rising edge, the TAP state machine will enter the Test-Logic-Reset state. In Select-IR-Scan state, the instruction is not changed. When the Capture-IR Capture instruction register state is in the Capture-IR state, the value in the instruction register is fixedly set to 0b0000001 and placed in a shift register connected between TDI and TDO. In the Capture-DR state, the instruction is not changed. If the TMS signal is at high level at the next rising edge of TCK, the TAP enters an Exit1-IR state; if the TMS signal is low on the next TCK rising edge, the TAP enters the Shift-IR state. Shift-IR Shift instruction register State in the Shift-IR state, at each rising edge of TCK, the TDI-Shift register-TDO serial channel is shifted one bit to the right, JTAG instructions are shifted bit by bit from the TDI pin into the Shift register, and 0b0000001 in the Shift register is shifted bit by bit from the TDO pin. In the Shift-IR state, the instruction is not changed. If the TMS signal is at high level at the next rising edge of TCK, the TAP enters an Exit1-IR state; the TAP is always on the shift operation if the TMS signal is low. Exit1-IR Exit instruction register State 1Exit1-IR is a temporary state of the TAP state machine, if the TMS signal is at high level at the next TCK rising edge, the TAP enters into Update-IR state; if the TMS signal is low on the next TCK rising edge, the TAP enters the Pause-IR state. In the Exit1-IR state, the instruction is not altered. The Pause-IR instruction register state Pause-IR state allows the TAP state machine to temporarily halt the shift operation of the TDI-shift register-TDO serial channel. In the Pause-IR state, the instruction is not changed. If the TMS signal is at high level at the next TCK rising edge, TAP enters an Exit2-IR state; if the TMS signal is low, the TAP is always in a suspended state. Exit2-IR exits the state of the instruction register 2Exit2-IR is also the temporary state of the TAP state machine, if the TMS signal is at high level at the next rising edge of TCK, the TAP enters the Update-IR state, and the scanning operation is finished; if the TMS signal is low on the next TCK rising edge, the TAP re-enters the Shift-IR state. In the Exit2-D state, the instruction is not changed. When the Update-IR Update instruction register state is in the Update-IR state, the value in the shift register will be latched into the instruction register at the falling edge of TCK, and once latching succeeds, the new instruction will become the current instruction. If the TMS signal is at high level at the next rising edge of the TCK, the TAP enters a Select-DR-Scan state; if the TMS signal is at level on the next TCK rising edge, the TAP enters the Run-Test-Idle state.

At present, the boundary scan testing technology is mainly applied to the single board off-line testing process in the module acceptance, delivery and troubleshooting processes in China. The SCANSTA112 chip is a chip developed by TI corporation for implementing JTAG bridge functionality. The SCANSTA112 chip has 7 LSP access capabilities, converts control of the JTAG bus to control of the local scan port LSP in the module under test, and provides very rich test functionality. However, there are 2 limitations to using the SCANSTA112 chip: 1) The SCANSTA112 chip is an imported chip, and the risks of stopping production and banning of the chip exist; 2) The use of the SCANSTA112 chip may additionally increase the hardware resource overhead of the circuit module. Based on the above reasons, how to replace the imported SCANSTA112 chip to implement the JTAG bridge function, so as to achieve the purpose of autonomous controllability and reducing the hardware resource overhead of the circuit module is a difficult problem faced by the prior art.

The invention aims to provide IP core software for a PL part of an operation board card-level management FPGA chip or a ZYNQ chip to replace an imported SCANSTA112 chip to realize the JTAG bridge function.

Disclosure of Invention

The invention aims to solve the problems in the prior art, and aims to provide IP core software capable of running on a programmable logic device (an FPGA chip or a ZYNQ chip PL part), an IP core capable of reducing hardware resource expenditure and improving resource utilization rate and realizing a JTAG bridge conversion function by using a substitute logic device to substitute an imported logic device, particularly an IP core capable of avoiding possible shutdown or forbidden operation risks of an imported SCANSTA112 chip and reducing hardware resource expenditure brought by adopting a special chip.

The above object of the present invention can be achieved by an IP core for implementing a JTAG bridge switching function instead of a logic device, comprising: JBIP software (JTAG Bridge IP, JBIP for short) capable of running on a management programmable logic device of a module or a board card to be tested, wherein the JBIP software has three working states of waiting for an address state, an address selecting state and a parking state, and is characterized in that: in the state of waiting for the address, JBIP software follows the state change of the boundary scanning signal on the boundary scanning test bus and processes the addressing instruction, the JBIP software enters the state of address selection after the address is matched, and in the state of address selection, the JBIP software responds and processes various test instructions; in the parking state, JBIP parks the LSP state machine at one of 4 stable states of Test Logic Reset state, run Test/Idle, pause-IR and Pause-DR of the boundary scan Test state machine; JBIP software is based on JTAG oriented to reusable IP core test, on the basis of JTAG industrial standard, the control of JTAG bus supporting functions of register checking and setting, IP core program flow tracking, code coverage rate checking, code analysis, IP core scanning test and the like is converted into the control of local scanning port LSP in a tested module, a SCANSTA112 chip is replaced to realize JTAG bridge exchange function, a bus conversion bridge structure is realized by using FPGA to realize the scanning test and data conversion control of a JTAG chain in the tested module by a test system main control module through the JTAG bus, and finally the JTAG bus conversion bridge IP core is packaged.

The invention has the following beneficial effects:

the invention adopts JBIP software which can run on a management programmable logic device of a module or a board card to be tested, and the JBIP software has three working states of waiting for an address state, an address selecting state and a parking state, and is characterized in that: in the state of waiting for the address, JBIP software follows the state change of the boundary scanning signal on the boundary scanning test bus and processes the addressing instruction, after the address is matched, the JBIP software enters an address selection state, and in the address selection state, the JBIP software responds to and processes various test instructions; in a parking state, JBIP parks the LSP state machine at one of 4 stable states of Test Logic Reset, run Test/Idle, pause-IR and Pause-DR of a boundary scan Test state machine; on the management programmable logic device (FPGA chip or ZYNQ chip PL part) capable of running the tested module, the hardware resource overhead caused by additionally increasing SCANSTA112 chips is reduced, and the resource utilization rate is improved.

The invention adopts JBIP software with 7 LSP access capability, based on JTAG oriented to reusable IP core test, on the basis of JTAG industrial standard, the control of JTAG bus supporting functions of register checking and setting, IP core program flow tracking, code coverage rate checking, code analysis, IP core scanning test and the like is converted into the control of local scanning port LSP in the tested module, thereby replacing SCANSTA112 chip to realize JTAG bridge exchange function, realizing the scanning test and JTAG data conversion control of the JTAG chain in the tested module by the test system main control module through JTAG bus by utilizing FPGA to realize bus conversion bridge structure, and finally packaging into the bus conversion bridge IP core. By running JBIP software on a management programmable logic device (FPGA chip or ZYNQ chip PL part) of a tested module or board card, the JBIP software can replace a SCANSTA112 chip to realize a JTAG bridge exchange function, the control of a JTAG bus is converted into the control of a local scanning port LSP in the tested module, and the scanning test and control of 7 JTAG chains in the tested module by a main control module of a test system through 1 JTAG bus are realized. The replacement of the JTAG bridge function of the SCANSTA112 chip is realized, and the risk of shutdown or forbidden operation of an imported chip is avoided; BIP software can run on a programmable logic device (an FPGA chip or a ZYNQ chip PL part), and control of a JTAG bus is converted into control of a local scanning port LSP in a tested module to replace a SCANSTA112 chip to realize a JTAG bridge function. The IP core software running in the PL part of the FPGA chip or the ZYNQ chip of the module to be tested is used for realizing the JTAG bridge function, replaces an imported SCANSTA112 chip, solves the data exchange of each system through a bus conversion bridge architecture, avoids the possible production halt or forbidden operation risks of the imported chip, and simultaneously reduces the hardware resource overhead brought by adopting a special chip. The result shows that the design can well complete the data exchange among the system modules and realize the high-efficiency and stable multi-bus exchange function.

The invention utilizes the boundary scanning technology to control the IC chip to be in a high-impedance mode, and the testing mechanism based on the boundary scanning technology can be shared at different stages of the whole life cycle of the product, so that the circuit system can be conveniently debugged and tested by utilizing the boundary scanning technology, and the development cycle and the cost of the product are obviously reduced. The expected target is achieved through experiments.

The IP core which replaces the SCANSTA112 chip to realize the JTAG bridge exchange function is mainly applied to the development of a system-level and embedded online boundary scan test system which is highly fused with equipment design. The method can be applied to avionics systems adopting comprehensive modular architectures and is used for developing embedded online boundary scan test systems.

Drawings

The invention is further described below with reference to the drawings and the embodiments.

FIG. 1 is a block diagram of the internal components of the JBIP software of the present invention;

FIG. 2 is a schematic diagram of a TAP state machine in JBIP software;

FIG. 3 is a process flow diagram of JBIP software address matching;

the following detailed description of embodiments of the invention is intended to be illustrative, and is not to be construed as limiting the invention.

Detailed Description

See fig. 1. In a preferred embodiment described below, an IP core implementing JTAG bridge translation functionality in place of a logic device includes: JBIP software (JTAG Bridge IP, JBIP for short) capable of running on a management programmable logic device of a module or a board card to be tested, wherein the JBIP software has three working states of waiting for an address state, an address selecting state and a parking state, and is characterized in that: in the state of waiting for the address, JBIP software follows the state change of the boundary scanning signal on the boundary scanning test bus and processes the addressing instruction, the JBIP software enters the state of selecting the address after the address is matched, and in the state of selecting the address, the JBIP software responds and processes various test instructions; in a parking state, the JBIP parks the LSP state machine at one of four stable states of a Reset state Test Logic Reset state, a maintainable state Run-Test-Idle, a Pause-IR and a latch state Pause-DR of a boundary scanning Logic of a boundary scanning Test state machine; JBIP software is based on JTAG oriented to reusable IP core test, on the basis of JTAG industrial standard, the control of JTAG bus supporting functions of register checking and setting, IP core program flow tracking, code coverage rate checking, code analysis, IP core scanning test and the like is converted into the control of local scanning port LSP in a tested module, a SCANSTA112 chip is replaced to realize JTAG bridge exchange function, a bus conversion bridge structure is realized by using FPGA to realize the scanning test and data conversion control of a JTAG chain in the tested module by a test system main control module through the JTAG bus, and finally the JTAG bus conversion bridge IP core is packaged.

The JBIP software comprises: the JBIP software comprises: the system comprises a TAP state machine, an address matching address comparator, an instruction Register, mode selection registers Mode Register0 and Mode Register1, a multicast address configuration Register, a BYPASS Register, an IDCODE Register, a 32-bit TCK counter, an LSP serial connection and LSP stop state processing module, a TDO output selector and a data Register output selector, wherein the instruction Register comprises: BYPASS register, IDCODE register, multicast address configuration register, realize BYPASS BYPASS, node code IDCODE, mijiel MCGRSEL, mo Daisi special MODESELEL/model MODESELEL 1, untie mark UNPARK, PARKTLR, parkerr PARKRTI, pause PARKPAUSE, GOTOWAIT, process control CNTRSEL, CNTRON, CNTROFF instruction; the TAP state machine detects TMS, TCK, TRST and other signals of the boundary scan test bus, follows the control state of a TBC (peripheral component test) of the boundary scan test bus controller, and provides core working state indication for the interior of the system according to the boundary scan 16-bit TAP state machine; the address comparator with matched address matches the input of the matched slot position address according to the address matching input on the boundary scanning test bus, and converts the working state of the JBIP according to the matching result; the Mode selection registers Mode Register0 and Mode Register1 are configured with an LSP0-6 hanging Mode; the multicast address configuration register performs multicast address configuration; the BYPASS register provides a 1-bit boundary scan BYPASS register; the IDCODE register provides a 32-bit boundary scan IDCODE register; the 32-bit TCK counter provides a 32-bit TCK counter to support LSP BIST test by matching with a CNTRON/CNTROFF instruction; the LSP concatenation is carried out according to the mode selection register, and a PAD is provided for each LSP after concatenation; the LSP parking state processing module carries out related processing on TMS of LSP0-6 under the corresponding parking state according to the parking related instruction (including UNPARK, PARKTLR, PARKRTI and PARKPAUSE).

Providing a TAP (Test Access Port) state machine and an address matching function in a JBIP waiting address state; providing an instruction Register (BYPASS, IDCODE, MCGRSEL, MODESEL/MODESEL1, UNPARK, PARKTLR, PARKRTI, PARKPAUSE, GOTOWAIT, CNTRSEL, CNTRON, CNTROFF and other instructions) in an address selection state, mode selection registers of a Mode Register0 and a Mode Register1, a multicast address configuration Register, a BYPASS Register, a 32-bit IDCODE Register, a 32-bit TCK counter Register and an LSP concatenation function; and carrying out LSP (label switched path) parking state processing in the parking state.

The Data Register output selector selects a decoding result Data Register Select depending on the instruction Register; instruction: the instruction register processes various JTAG bridge control instructions, outputs a data selection register selection signal, and simultaneously sends an instruction value of the instruction register to the Address Comparator for Address matching comparison; the Address Comparator supports Address comparison mechanisms such as unicast, multicast and broadcast, and the Address Comparator gives a unicast Address selected signal Single Matched to control the output selection of the TDO Mux; the IR/DR Mux instruction/data selector selects DR Out in the Shift-DR State and IR Out in the Shift-IR State, the selection signal is from TAP State Machine, and the output of IR/DR Mux can be used as the input of Local Scan Port Mux or directly output to TDO Mux; local Scan Port Mux: the LSP serial connection processing and LSP stopping processing module is a core module of a JTAG bridge, and is used for performing serial connection processing on each LSP link according to a serial connection mode and simultaneously performing stopping management on the LSP according to a stopping state; TDO Mux: the TDO output selector selects according to the LSP state selection configuration, address matching state, or the like, and can output a Bridge TDO, LSP TDO, or High Z state.

See fig. 2. The TAP state machine is a core state machine of JBIP, and consists of a test access channel consisting of a test clock input line (TCK), a test mode selection input line (TMS), a test data input line (TDI), a test data output line (TDO) 4-wire serial test lines, and all operations defined by the JTAG standard are controlled by these four test lines. All the working mode switching, instruction analysis, register reading and writing and the like depend on the state machine. The TAP state machine is the same as the boundary scan 16-bit TAP state machine. The TAP state machine is the core controller for boundary scan testing and has a 16-state finite state machine operating in synchronization with the TCK signal and responsive to the TMS signal. Under control of the TCK and TMS signals, the TAP state machine can select whether to use instruction register scanning or data register scanning, as well as select the various states used to control the boundary scan test. Regardless of the current state, as long as the TMS keeps 5 TCK clocks high, the TAP state machine will return to the Test _ Logic _ Reset state, so that the Test circuit does not affect the normal Logic of the IC chip itself, and when testing is required, the TAP state machine jumps out of this state, selects the data register Scan (Select _ DR _ Scan) or selects the instruction register Scan (Select _ IR _ Scan) to enter the respective states of fig. 2. A

The TAP state machine captures instruction information in a Capture _ IR state, a new instruction is moved into the CAPTURE state through a Shift _ IR state, and the new instruction becomes a current instruction through an Update _ IR state; next, the current instruction selects a corresponding test data register in the Select _ DR _ Scan state, captures a response vector of a previous test vector in the Capture _ DR state, shifts out the response vector in the Shift _ DR state while shifting in a next test vector, and loads a new test quantity in parallel to a corresponding serial data channel in the Update _ DR state until shifting in a test vector, wherein the Pause _ DR state and the Pause _ IR state suspend the data Shift state; while the four Exit states are unstable states, they provide flexibility for state transitions.

The IR is an instruction register which sends various operation codes to each data register and determines the working mode of the data register, the IR unit is composed of a trigger Q1 and a latch Q2, a CAPTURE DATE signal controls an IR loading instruction, and a SHIRFT IR signal controls the shift of the instruction in the IR; the CLK IR signal provides a clock signal derived from TCK for the BSR capture operation, shift operation, and the UPDATE IR signal loads the current instruction into latch Q2 to determine the mode of operation to be performed and the type of test data register to be used.

The controller enters a reset state to enable a TMS end to receive a low level signal, after the TAP state machine is controlled to complete reset operation, the TAP state machine enters a Shift _ IR state, when 5 TCK periods continue for 5 TCK rising edges to enable the TMS end to receive 01100, the TAP state machine enters the Shift _ IR state, on the 5 th TCK rising edge of the Shift _ IR state, TMS =1 enters an Exit1_ IR state, then a high-resistance state instruction code 11111100 is written into an instruction register through TDI, and at the moment, the TMS keeps 4 periods of low level; after entering the Exit1_ IR state, TMS =1 is entered into the Update _ IR state. At this point the chip enters a high impedance state.

The TAP state machine comprises 16 operation states controlled by TMS and TCK2 JTAG signals, the 16 states are divided into three types, namely an Idle type, a data scanning type and an instruction scanning type, wherein the Idle type comprises two states of a Reset state Test-Logic-Reset and a Run-Test-Idle of a boundary scanning Logic, in the Reset state Test-Logic-Reset state of the boundary scanning Logic, a current instruction is automatically set to be an IDCODE, if an IDCODE register is not provided, the current instruction is set to be a BYPASS instruction, the internal Logic of the device is not influenced, the boundary scanning circuit is in an inactive state

As can be seen from the state transition diagram, in any case, the state must return to the Reset state Test-Logic-Reset of the boundary scan Logic as long as the TMS maintains the high level for five TCK periods, and furthermore, if the TMS has an undesired short low level due to an accidental factor, the state leaves the Reset state Test-Logic-Reset of the boundary scan Logic, and as long as the TMS returns to the high level, the state returns to the Reset state Test-Logic-Reset of the boundary scan Logic after three TCK periods. The three states Run-Test-Idle, select-DR-Scan and Select-IR-Scan which pass through the period do not activate the scanning operation, thereby ensuring that the boundary scanning circuit does not affect the working stability of the chip. In addition, if the TRST signal is low, the state is forced back to the Reset state Test-Logic-Reset of the boundary scan Logic. The Reset state Test-Logic-Reset of the boundary scan Logic is a holdable state that continues to be held when TMS is high on the rising TCK edge and leaves only when TMS is low on the rising TCK edge. The holdable state Run-Test-Idle state is the 1 st state after coming out of the Reset state Test-Logic-Reset state of the boundary scan Logic, a state between the scan operation and Reset, which will be held when TMS is low on the rising edge of TCK. The Run-Test-Idle only has a few instructions to execute operations in the state, such as self-Test, and most of the time, the operation cannot be executed in the state, and the register selected by the instruction does not act. Wherein Register refers to the data Register selected by JBIP according to instruction decoding.

And processing an LSP (label switched path) parking state. The LSP can only stop at the steady state of the 4 boundary scan state machines of Test Logic Reset, run Test/Idle, pause-DR and Pause-IR, and the handling of stopping and mounting of each state is slightly different, which is described separately below.

And mounting and docking the Test Logic Reset state. After the LSP is Reset, the state of the Test Logic Reset is kept at 1, TMS signals of the LSP are kept at 1 until a certain LSP is selected through the configuration of a mode selection register and executes a UNPARK instruction, after the UNPARK instruction takes effect, when the state machine is shifted to a Run Test/Idle state, the TMS of the LSP is changed into 0 and is synchronized with TMSB, so that the mounting of the state of the Test Logic Reset is finished, correspondingly, when JBIP inputs a PARKTLR instruction and takes effect, and after the state machine is shifted to the Test Logic Reset, the TMS of the LSP keeps at 1, so that the LSP is stopped at the state of the Test Logic Reset.

And mounting and docking of the Run Test/Idle state. After the LSP is mounted, if the instruction register of the JBIP inputs a PARKRTI instruction and takes effect, when the state machine is transferred to a Run Test/Idle state, the TMS of the LSP keeps 0 and is disconnected from the TMSB, so that the LSP is stopped at the Run Test/Idle state, correspondingly, the LSP stopped at the Run Test/Idle state is configured and selected by the mode register of the JBIP, when the state machine is transferred to the Run Test/Idle state after the UNPARK instruction is input and takes effect, the TMS of the LSP is synchronized with the TMSB, and therefore the LSP is not stopped from the Run Test/Idle state and is mounted on the JBIP.

And (4) mounting and docking the Pause-DR/Pause-IR states. After the LSP is mounted, if a PARKPAUSE instruction is input into an instruction register of JBIP and is effective, when the state machine is migrated to an Exit1-DR/Exit1-IR state, if the next TMS is 1, namely the state of the next state machine is Update-DR/Update-IR, the TMS of the LSP keeps 0 and is disconnected from TMSB, so that the LSP is docked in a Pause-DR/Pause-IR state; and if the next TMS in the Exit1-DR/Exit1-IR state is 0, namely the state of the next state machine is Pause-DR/Pause-IR, the TMS of the LSP still keeps synchronous with the TMSB, namely no docking is carried out. When the LSP is docked in a Pause-DR/Pause-IR state, if a PARKPAUSE instruction is input into an instruction register of JBIP and is effective, and when a state machine is migrated to an Exit1-DR/Exit1-IR state, if the next TMS is 0, namely the state of the next state machine is Pause-DR/Pause-IR, connecting the TMS of the parked LSP with the TMSB, so that the LSP is changed from the parking state to a mounting state; similarly, if the next state machine state is Update-DR/Update-IR while in the Exit1-DR/Exit1-IR state, the LSP still remains docked. PARKPAUSE is a dual function instruction that can both park and mount an LSP from the Pause-DR/Pause-IR state.

The data scanning states include 7 states, which are respectively: select-DR-Scan, capture-DR, shift-DR, exit1-DR, pause-DR, exit2-DR, and Update-DR, when in these states, a data register is selected for operation by the current instruction. The Select-DR-Scan, the Exit1-DR and the Exit2-DR are temporary states, and the main function is to buffer in the state transition process, so that the content of the selected register cannot be changed. The Capture-DR state is a parallel load state, in which if the selected data register has a parallel load capability and the current instruction requires a parallel load, the contents of the selected register will change immediately, and if the currently selected data register does not have a parallel load capability or the instruction does not require the same, the contents of the register will remain unchanged. The Shift-DR state is a serial Shift state in which the register selected by an instruction is connected to TDI and TDO to form a serial Shift chain, when the rising edge of TCK arrives, the value of TDI is sampled and shifted into the register, the other bits of the register are shifted by one bit in sequence, and the bit closest to TDO is shifted out to TDO for external reception. The Shift-DR state is a holdable state that persists when TMS is low on the rising edge of TCK, thus enabling continuous data movement in. The Pause-DR state is a suspended state whose purpose is to allow the move-in and move-out process of data to be temporarily stopped as needed, and to be quickly restored to the Shift-DR state. In this state, the register contents selected to be connected between TDO and TDI are unchanged and the external level change is ignored. The latch state Pause-DR can realize pauses of different time lengths. The Update-DR state is a latch state, which is intended to prevent the required data from being destroyed during the shifting process, and the latch contents can only be changed in the state under no special condition, i.e. after the data is shifted in, it needs to be shifted to the state, the data is saved, and then the next shifting or other operations are performed.

The instruction Scan state also includes 7 states, respectively Select-IR-Scan, capture-IR, shift-IR, exit1-IR, pause-IR, exit2-IR and Update-IR, which are all associated with the instruction Scan, and when in these states, the instruction register is selected for operation, which is simpler with respect to the data register since there is only one instruction register. The operation of the instruction register is completely determined by the states, the instruction scanning type states correspond to the data scanning type states one by one, the meanings and the effects of the instruction scanning type states and the data scanning type states are similar to the operation executed in the corresponding states, and only the operation objects are different.

See fig. 3. And the JBIP processes the addressing request of the JTAG main control according to the addressing instruction on the JTAG bus in the waiting address state, matches the addressing address of the JTAG main control according to the slot address input and the multicast address setting of the JBIP, and finally determines whether the JBIP enters the address selection state or returns to the waiting address state according to the matching result. The addressing request of the JTAG main control is carried out in the Shift-IR state of the boundary scan state machine, and in the state, all JBIPs in the waiting address state on the JTAG bus need to carry out matching processing on the address sent by the JTAG main control. The address matching length of JBIP is 8 bits, and is compatible with SCANSTA 112.

JBIP provides 250 single selection addresses, one broadcast address and four multicast addresses, and the values of the addresses are according to the 16-system address single selection addresses 00-39,40-FF, the broadcast addresses 3B,3C multicast addresses 0,3D multicast addresses 1,3E multicast addresses 2,3F multicast addresses 3.

After JBIP enters the address selection state, the Shift-IR operation of JTAG main control decodes the instruction register entering JBIP. The instruction register of JBIP is 8 bits in length and is compatible with SCANSTA 112. JBIP provides BYPASS, IDCODE, MCGRSEL, MODESEL/MODESEL1, UNPARK, PARKTLR, PARKRTI, PARKPAUSE, GOTOWAIT, CNTRSEL, CNTRON, CNTROFF instructions, etc., the instruction code is compatible with SCANSTA112, UNPARK is compatible with IEEE1149.1 standard IDCODE register, the LSP which is in the parking state and selected by the mode selection register exits the parking state and is hooked into the complete scan link. The timing of exiting the parked state depends on the particular parked state. An IDCODE register compatible with the PARKTLR and the IEEE1149.1 standard stops the LSP at the state when the boundary scan Test state machine enters the Test Logic Reset state; the IDCODE register compatible with PARKRTI and IEEE1149.1 standard stops LSP at the state when the boundary scan Test state machine enters the Run Test/Idle state; an IDCODE register compatible with PARKPAUSE and IEEE1149.1 standard stops LSP at the state when the boundary scan test state machine enters the Pause-DR or Pause-IR state; GOTOWAIT and IEEE1149.1 standard compliant IDCODE register. Controlling JBIP to wait for address state; the 32-bit TCK counter register of CNTRSEL sets a 32-bit TCK counter that supports BIST mode; the IDCODE register compatible with the IEEE1149.1 standard of the CNTRON controls the LSP to enter a BIST mode, and the BIST is executed according to the TCK counter; the IDCODE register compliant with CNTROFF IEEE1149.1 standard exits BIST mode.

The instruction code, corresponding data register and meaning of each instruction are as follows:

the Mode select registers include Mode Register0 and Mode Register1, both of which are 8 bits long.

The multicast address configuration register provides multicast address configuration and has a length of 2.

The BYPASS register is compatible with the IEEE1149.1 standard, and a 1-bit BYPASS register is added to the scan chain in series so as to shorten the length of the scan chain. When a chip is selected as a bypass chip, the bypass register is gated between the TDI and TDO pins, and the data path contains only one bit.

The IDCODE register is compatible with the IEEE1149.1 standard, has the length of 32 bits, has the value compatible with the SCANSTA112 and is 0x0FC2501F.

A32-bit TCK counter is used to support the BIST test, which is selected by the CNTRSEL instruction, and has a default value of 0x00000000. After the 32-bit TCK counter is configured, the counter can be started through a CNTRON instruction, and after the state machine enters a Run Test/Idle state, if the LSP is in a PARKRTI state, the 32-bit TCK counter is decremented on each rising edge of the TCK until the TCK is decremented to 0, and the TCK of the corresponding LSP is kept to 0.

The LSPs are concatenated. JBIP carries out LSP series connection according to the configuration of the mode selection register, and a 1-bit PAD is connected in series behind each LSP. There are various combinations of concatenation modes.

Claims (10)

1. An IP core that implements a JTAG bridge translation function in place of a logic device, comprising: JBIP software capable of running on the management programmable logic device of a module or a board card to be tested and having three working states of waiting for an address state, an address selecting state and a docking state, and is characterized in that: in the state of waiting for the address, JBIP software follows the state change of the boundary scanning signal on the boundary scanning test bus and processes the addressing instruction, the JBIP software enters the state of address selection after the address is matched, and in the state of address selection, the JBIP software responds and processes various test instructions; in the parking state, JBIP parks the LSP state machine at one of a Test Logic Reset state, a Run Test/Idle running Test Idle state, a Pause-IR instruction register state, a Pause-DR data register state and 4 stable states of a boundary scan Test state machine; JBIP software is based on JTAG oriented to reusable IP core test, on the basis of JTAG industrial standard, the control of JTAG bus supporting register checking and setting, IP core program flow tracking, code coverage rate checking, code analysis and IP core scanning test function is converted into the control of local scan port LSP in a tested module, SCANSTA112 chip is replaced to realize JTAG bridge exchange function, FPGA is used for realizing bus conversion bridge structure to realize the scan test and data conversion control of a JTAG chain in the tested module by a test system main control module through the JTAG bus, and finally the JTAG bus conversion bridge IP core is packaged.

2. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: the TAP state machine comprises 16 operation states controlled by TMS and TCK2 JTAG signals, wherein the 16 states are divided into three types, namely an Idle type, a data scanning type and an instruction scanning type, wherein the Idle type comprises two states of a Reset state Test-Logic-Reset and a Run-Test-Idle of a boundary scanning Logic, the current instruction is automatically set to be an IDCODE in the Reset state Test-Logic-Reset state of the boundary scanning Logic, if an IDCODE register is not provided, the instruction is set to be a BYPASS instruction, the internal Logic of the device is not influenced, and a boundary scanning circuit is in an inactive state.

3. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: after being Reset, the LSP is in a Test Logic Reset state, TMS signals of the LSP are kept at 1 until a certain LSP is selected through mode selection register configuration and executes a UNPARK instruction, after the UNPARK instruction takes effect, when the state machine is shifted to a Run Test/Idle state, the TMS of the LSP is changed into 0 and is synchronous with TMSB, the mounting of the Test Logic Reset state is completed, correspondingly, when JBIP inputs a PARKTLR instruction and takes effect, and after the state machine is shifted to the Test Logic Reset, the TMS of the LSP is kept at 1, so that the LSP is stopped at the Test Logic Reset state.

4. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: after the LSP is mounted, if a PARKPAUSE instruction is input into an instruction register of JBIP and is effective, when the state machine is migrated to an Exit1-DR/Exit1-IR state, if the next TMS is 1, namely the state of the next state machine is Update-DR/Update-IR, the TMS of the LSP keeps 0 and is disconnected from TMSB, and the LSP is stopped at a Pause-DR/Pause-IR state; and if the next TMS in the Exit1-DR/Exit1-IR state is 0, namely the state of the next state machine is Pause-DR/Pause-IR, the TMS of the LSP still keeps synchronous with the TMSB, namely no docking is carried out.

5. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: when the LSP is docked in a Pause-DR/Pause-IR state, if a PARKPAUSE instruction is input into an instruction register of JBIP and is effective, and when a state machine is migrated to an Exit1-DR/Exit1-IR state, if the next TMS is 0, namely the state of the next state machine is Pause-DR/Pause-IR, connecting the TMS of the docked LSP with the TMSB, and changing the LSP from the park state to a mount state; similarly, if the next state machine state is Update-DR/Update-IR while in the Exit1-DR/Exit1-IR state, the LSP still remains docked.

6. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: and when the JBIP is in the address waiting state, processing an addressing request of the JTAG main control according to an addressing instruction on the JTAG bus, matching the addressing request with an addressing address of the JTAG main control according to the slot address input and the multicast address setting of the JBIP, and finally determining whether the JBIP enters an address selecting state or returns to the address waiting state according to a matching result.

7. The IP core of claim 1, wherein the replacement logic device implements a JTAG bridge translation function, and wherein: the addressing request of the JTAG main control is carried out in the Shift-IR state of the boundary scan state machine, in the state, all JBIPs in the address waiting state on the JTAG bus carry out matching processing on the address sent by the JTAG main control; the address matching length of JBIP is 8 bits, and is compatible with SCANSTA 112.

8. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: after JBIP enters an address selection state, the Shift-IR operation of JTAG master control decodes an instruction register entering JBIP, exits the parking state of the LSP which is in the parking state and selected by the mode selection register, is hooked into a complete scanning link, and stops the LSP at the state when a boundary scanning Test state machine enters a Test Logic Reset state; the IDCODE register compatible with PARKRTI and IEEE1149.1 standard stops the LSP at the state when the boundary scan Test state machine enters the Run Test/Idle state; when the boundary scan test state machine enters a Pause-DR or Pause-IR state, the LSP is stopped at the state; controlling JBIP to wait for address state; the IDCODE register compatible with the IEEE1149.1 standard of the CNTRON controls the LSP to enter a BIST mode, and the BIST is executed according to the TCK counter; the IDCODE register compliant with CNTROFF IEEE1149.1 standard exits BIST mode.

9. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: LSP concatenates, JBIP carries on LSP concatenates according to the configuration of the mode selection register, join a 1bit PAD behind each LSP; the serial connection mode has various combinations; the BYPASS register is compatible with the IEEE1149.1 standard, a 1-bit BYPASS register is connected in series with a scan chain, when a chip is selected as a BYPASS chip, the BYPASS register is gated and connected between pins TDI and TDO, and a data path only comprises one bit.

10. The alternative logic device of claim 1, wherein the IP core implements a JTAG bridge translation function, and wherein: the counter is selected by a CNTRSEL instruction, the default value is 0x00000000, after the 32-bit TCK counter is configured, the counter is started by the CNTRON instruction, after the state machine enters a Run Test/Idle state, if the LSP is in a PARKRTI state, the 32-bit TCK counter is decreased at each TCK rising edge until the TCK is decreased to 0, and the corresponding TCK of the LSP is kept to be 0.

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