CN109491686A

CN109491686A - FPGA program on-line upgrading method based on xilinx company k7 series

Info

Publication number: CN109491686A
Application number: CN201811301657.6A
Authority: CN
Inventors: 李世良; 张迪飞
Original assignee: Tianjin Jinhang Institute of Technical Physics
Current assignee: Tianjin Jinhang Institute of Technical Physics
Priority date: 2018-11-02
Filing date: 2018-11-02
Publication date: 2019-03-19

Abstract

The present invention relates to a kind of FPGA program on-line upgrading methods based on xilinx company k7 series, belong to FPGA program on-line upgrading technical field.Two configuration image files are stored when the design of firmware program of the present invention in FPGA, make online upgrading FPGA program reliable and stable by the way of restarting, it is ensured that online upgrading function.That is 2 bit files are stored in FPGA, first is monitoring programme (preventing online upgrading from failing), and second is primary control program, i.e. battle order.Therefore, the present invention is realized through RS422 serial ports, if occurring mistake when online upgrading primary control program in escalation process leads to primary control program upgrading failure, system, which is again powered up, restarts, and will start monitoring programme, moreover it is possible to continue to upgrade primary control program.

Description

FPGA program on-line upgrading method based on xilinx company k7 series

Technical field

The invention belongs to FPGA program on-line upgrading technical fields, and in particular to it is a kind of based on xilinx company k7 series FPGA program on-line upgrading method.

Background technique

FPGA program carries out programming usually using USB artificial mains network, needs to carry out being dismounted for multiple times to equipment, seriously affects and be System working efficiency needs to develop new method realization to the online change of FPGA program, and setting FPGA is main SPI mode, is used for FPGA autonomous load configuration data after powering on is deposited using the Flash storage configuration data of standard SPI interface by changing Flash Data are stored up, the online upgrading of FPGA firmware program can be completed.In escalation process, to complete to write the erasing of Flash chip Enter operation, if making to wipe write operation failure due to power supply, cable etc., upgrading is unable to complete, again updating operation Becoming can not.

Summary of the invention

(1) technical problems to be solved

The technical problem to be solved by the present invention is how to make online upgrading FPGA program reliable and stable, it is ensured that online upgrading Function.

(2) technical solution

In order to solve the above-mentioned technical problems, the present invention provides a kind of FPGA programs based on xilinx company k7 series to exist Line upgrade method, comprising the following steps:

Host computer is sent to FPGA first starts equipment to code instruction, and FPGA online upgrading stream is successfully indicated entry into code Journey, upgrading data are entered in the twoport of FPGA by mother daughter board connector, and DSP will upgrade data buffer storage by EMIF interface, FPGA is communicated by read-write FIFO and FLASH therein, and carries out erasing operation to FLASH first, will after wiping successfully The upgrading data of caching upload in FLASH, and after the completion of upload, DSP sends reading order to FPGA, and FPGA controls FLASH and reads The upgrading data in FLASH are returned, upgrading data are transmitted to DSP by FIFO by FPGA, and DSP carries out full frame verification, and DSP judges to be written Enter FLASH data accumulation and with the data accumulation to read back from FLASH and whether consistent, if unanimously, controlling FPGA write-in and burning Write Success Flag, so that the monitoring programme of FPGA starts, inquire this mark, monitoring programme be responsible for judging last time programming whether at Function, decide whether to jump in primary control program start execute battle order terminate if inconsistent；If programming fails, do not jump Turn, FPGA rests on monitoring programme, if programming success, jumps to the primary control program of FPGA, i.e. battle order.

Preferably, the FPGA uses xilinx preferably, and matching inside k7 is utilized when jumping to the primary control program of FPGA It sets module I CAPE2 and starts more bit file skip command PROGRAM_B, and status word 27'h364C093 is set.

Preferably, the primitive module in the operating process be written and read to FLASH in FPGA, wiped, inside all calling k7 STARTUPE2 realizes the clock control to SPI FLASH chip.

Preferably, when the FPGA uploads to the upgrading data of caching in FLASH, divided stator frame.

Preferably, when the FPGA uploads to the upgrading data of caching in FLASH, 256 byte datas of every packet.

Preferably, the primary control program is battle order.

(3) beneficial effect

Two configuration image files are stored when the design of firmware program of the present invention in FPGA, by the way of restarting Keep online upgrading FPGA program reliable and stable, it is ensured that online upgrading function.That is 2 bit files are stored in FPGA, first is prison It controls program (preventing online upgrading from failing), second is primary control program, i.e. battle order.Therefore, the present invention, which realizes, passes through RS422 serial ports, if occurring mistake when online upgrading primary control program in escalation process leads to primary control program upgrading failure, system is again Secondary power-up is restarted, and monitoring programme will be started, moreover it is possible to continue to upgrade primary control program.

Detailed description of the invention

Fig. 1 is upgrade method flow chart of the invention；

Fig. 2 is system structure diagram of the invention.

Specific embodiment

To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention Specific embodiment is described in further detail.

As shown in Figure 1, a kind of FPGA program on-line upgrading method based on xilinx company k7 series provided by the invention, The following steps are included:

Host computer is sent first starts equipment to code instruction, and FPGA online upgrading process is successfully indicated entry into code, is upgraded Data are entered in the twoport of FPGA by mother daughter board connector, and DSP will upgrade data buffer storage by EMIF interface, and FPGA passes through it In read-write FIFO and FLASH (SPI FLASH) communicated (as shown in Figure 2), and first to FLASH progress erasing operation, After wiping successfully, the upgrading data of caching are uploaded in FLASH, divided stator frame, 256 byte datas of every packet, uploads and complete Afterwards, DSP gives FPGA to send reading order, and FPGA control FLASH reads back the upgrading data in FLASH, and FPGA leads to upgrading data Cross FIFO and be transmitted to DSP, DSP carries out full frame verification, DSP judge FLASH to be written data accumulation and with the number that reads back from FLASH According to cumulative and whether consistent, if unanimously, controlling FPGA and programming Success Flag being written, so as to the monitoring programme starting of FPGA, look into This mark is ask, monitoring programme is responsible for judging whether last time programming succeeds, and decides whether to jump to and starts to execute work in primary control program War program terminates if inconsistent.If programming fails, do not jump, FPGA rests on monitoring programme, to guarantee next energy Enough continue online upgrading, if programming success, jumps to the primary control program of FPGA, i.e. battle order.

In the present embodiment, FPGA is realized using xilinx company k7 family chip, benefit when jumping to the primary control program of FPGA Start more bit file skip command PROGRAM_B with the configuration module ICAPE2 inside k7, and status word 27' is set h364C093.Primitive module in the operating process be written and read to FLASH in FPGA, wiped, inside all calling k7 The existing clock control to SPI FLASH chip of STARTUPE2.

The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations Also it should be regarded as protection scope of the present invention.

Claims

1. a kind of FPGA program on-line upgrading method based on xilinx company k7 series, which comprises the following steps:

Host computer is sent to FPGA first starts equipment to code instruction, and FPGA online upgrading process is successfully indicated entry into code, is risen Grade data are entered in the twoport of FPGA by mother daughter board connector, and DSP will upgrade data buffer storage by EMIF interface, and FPGA passes through Read-write FIFO and FLASH therein is communicated, and carries out erasing operation to FLASH first, after wiping successfully, by the liter of caching Grade data upload in FLASH, and after the completion of upload, DSP sends reading order to FPGA, and FPGA control FLASH reads back in FLASH Upgrading data, upgrading data are transmitted to DSP by FIFO by FPGA, and DSP carries out full frame verification, and DSP judges FLASH's to be written Data accumulation and with the data accumulation to read back from FLASH and whether consistent, if unanimously, controlling FPGA write-in programming and successfully marking Will inquires this mark, monitoring programme is responsible for judging whether last time programming succeeds, and decision is so that the monitoring programme of FPGA starts It is no jump in primary control program start execute battle order terminate if inconsistent；If programming fails, do not jump, FPGA stops Monitoring programme is stayed in, if programming success, jumps to the primary control program of FPGA, i.e. battle order.

2. the method as described in claim 1, which is characterized in that the FPGA is realized using xilinx company k7 family chip.

3. method according to claim 2, which is characterized in that utilize the configuration inside k7 when jumping to the primary control program of FPGA Module I CAPE2 starts more bit file skip command PROGRAM_B, and status word 27'h364C093 is arranged.

4. method according to claim 2, which is characterized in that in the operating process that FPGA is written and read FLASH, wipes In, the primitive module STARTUPE2 inside calling k7 realizes the clock control to SPI FLASH chip.

5. the method as described in claim 1, which is characterized in that the FPGA uploads to the upgrading data of caching in FLASH When, divided stator frame.

6. method as claimed in claim 5, which is characterized in that the FPGA uploads to the upgrading data of caching in FLASH When, 256 byte datas of every packet.

7. such as method described in any one of claims 1 to 6, which is characterized in that the primary control program is battle order.