CN112732635A - FPGA (field programmable Gate array) reconstruction system and method based on-line update of SPI FLASH - Google Patents

Abstract

The invention relates to an FPGA reconstruction system and method based on-line update of SPI FLASH, which is technically characterized in that: an FPGA reconfiguration system based on-line updating of the SPI FLASH is constructed based on an external serial port, the FPGA and the SPI FLASH, meanwhile, an FPGA reconfiguration technical process of on-line programming of the SPI FLASH is designed for the system, and the FPGA in various devices can be updated by controlling the external serial port, the SPI FLASH and an FPGA internal module. The invention can not only update the FPGA program through the serial port, but also can update the program on line through the network interface, and meanwhile, the invention has higher performance and reliability and has important significance for the reconstruction of the FPGA.

Description

FPGA (field programmable Gate array) reconstruction system and method based on-line update of SPI FLASH

Technical Field

The invention belongs to the technical field of human-computer interaction, and particularly relates to an FPGA (field programmable gate array) reconstruction system and an FPGA reconstruction method based on-line update of an SPI FLASH.

Background

At present, most programs of the FPGA are stored in an external FLASH, the FPGA is used as a main controller to read data in the external FLASH to an internal RAM when being electrified, and then the programs are operated. The FPGA needs special software and a downloader for operating the external FLASH, and the downloading interface forms are different. Therefore, when the device needs to debug or upgrade the FPGA program in an external field, different downloaders are often required to be carried and the device is detached, so that the simulator can be connected with the FPGA for debugging or upgrading, and the device is reinstalled after debugging. Therefore, a large amount of manpower, material resources and debugging time are consumed, and sometimes installation calibration parameters of the system are damaged in the process of disassembly and assembly, so that the uncertainty of the system is increased.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, provides an FPGA reconstruction system and an FPGA reconstruction method based on-line updating of SPI FLASH, and can realize the updating of FPGA in various devices.

The technical problem to be solved by the invention is realized by adopting the following technical scheme:

the utility model provides a FPGA reconfiguration system based on to online update of SPI FLASH, includes outside serial ports, FPGA and SPI FLASH, outside serial ports, FPGA and SPI FLASH connect gradually, FPGA writes control logic module, SPI reads control logic module and SPI reading and writing module including receiving buffering FIFO module, information processing module, data check module, SPI, receives buffering FIFO module and connects outside serial ports respectively, SPI writes control logic module and data check module, SPI writes control logic module and connects information processing module and SPI reading and writing module respectively, SPI reads and writing module and connects SPI FLASH and SPI reading and writing control logic module respectively, SPI reads and writes control logic module and connects information processing module and data check module respectively.

And the SPI read-write module generates a gating signal CS, a clock signal CLK, a data sending signal MOSI and a data receiving signal MISO through a 4-wire SPI interface and a protocol of the FLASH to carry out data communication with the SPI FLASH.

And the information processing module detects the states generated by the SPI read control logic module and the SPI write control logic module in real time, generates corresponding information according to different states and sends the corresponding information to the upper computer for processing.

A FPGA reconstruction system method based on-line update of SPI FLASH is characterized in that: the method comprises the following steps:

step 1, sending an FPGA program to be updated to a receiving buffer FIFO module through an external serial port, sending received data to an SPI read-write module by an SPI write control logic module according to a certain time sequence, and writing the data into an SPI FLASH by the SPI read-write module through an SPI interface;

step 2, the data in the receiving buffer FIFO module is sent to a data check module, and a written data check value is calculated;

and 3, reading the data written into the SPI FLASH one by the SPI read-write control logic through the SPI read-write module until the number of the read data is the same as that of the written data, simultaneously sending the read data to the data check module by the SPI read control logic module so as to calculate a read data check value, judging whether the written data check value is the same as that of the read data, if so, successfully updating the program on line and finishing updating, and otherwise, giving error information.

Moreover, the FPGA program needing to be updated is a bin file generated by software.

The invention has the advantages and positive effects that:

the invention constructs an FPGA reconstruction system based on-line update of the SPI FLASH based on an external serial port, the FPGA and the SPI FLASH, designs an FPGA reconstruction technical process of on-line programming of the SPI FLASH aiming at the system, and can realize the update of the FPGA in various devices by controlling the external serial port, the SPI FLASH and an FPGA internal module. The invention can not only update the FPGA program through the serial port, but also can update the program on line through the network interface, and meanwhile, the invention has higher performance and reliability and has important significance for the reconstruction of the FPGA.

Drawings

FIG. 1 is a block diagram of the system architecture of the present invention;

fig. 2 is a flow chart of the reconstruction method of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

An FPGA reconfiguration system based on-line update of SPI FLASH is shown in figure 1 and comprises an external serial port, an FPGA and an SPI FLASH, wherein the external serial port, the FPGA and the SPI FLASH are connected in sequence. The FPGA comprises a receiving buffer FIFO module, an information processing module, a data verification module, an SPI writing control logic module, an SPI reading control logic module and an SPI reading and writing module, the receiving buffer FIFO module is respectively connected with an external serial port, the SPI writing control logic module and the data verification module, the SPI writing control logic module is respectively connected with the information processing module and the SPI reading and writing module, the SPI reading and writing module is respectively connected with an SPI FLASH and an SPI reading control logic module, and the SPI reading control logic module is respectively connected with the information processing module and the data verification module.

The SPI read-write module directly interacts with the SPI FLASH, and the SPI read-write module generates a gating signal CS, a clock signal CLK, a data sending signal MOSI and a data receiving signal MISO through a 4-wire SPI interface and a FLASH protocol to carry out data communication with the SPI FLASH.

A method for reconstructing a system based on an FPGA for on-line updating of an SPI FLASH comprises the following specific implementation methods: the FPGA program needing to be updated is sent to the receiving buffer FIFO module through an external serial port, wherein the SPI writing control logic module sends the received data to the SPI reading and writing module according to a certain time sequence, and the SPI reading and writing module writes the data into the SPI FLASH through the SPI interface; meanwhile, the data in the receiving buffer FIFO module is sent to a data check module, and a written data check value is calculated; after the whole updating program is written, the SPI read control logic reads the data written into the SPI FLASH one by one through the SPI read-write module until the number of the read data is the same as that of the written data, meanwhile, the SPI read control logic module sends the read data to the data check module, so that a read data check value is calculated, whether the written data check value is the same as that of the read data check value is judged, if the written data check value is communicated with the read data check value, the online updating program is successful and the updating is finished, and if not, error information is given.

The FPGA program needing to be updated is a bin file generated by software.

As shown in fig. 2, the specific implementation steps of the present invention are:

step 1, controlling gating;

step 2, the SPI write control logic module generates a read signal of the receiving buffer FIFO module and reads a program updating command from the FIFO;

step 3, the SPI writing control logic module sends an integral erasing command to the SPI FLASH through the SPI reading and writing module, and the SPI FLASH executes the integral erasing command;

step 4, as the whole-chip erasing time of the SPI FLASH is about 6s, waiting for 5 s after the whole-chip erasing is started;

step 5, the SPI writing control logic module reads the state register state of the SPI FLASH;

step 6, judging whether the whole erasing is finished, if the whole erasing is finished, performing step 7, and repeating the step 5;

step 7, the external serial port sends an update file to the receiving buffer FIFO module, the SPI writing control logic module reads data in the receiving buffer FIFO module, and the SPI reading and writing module generates a writing enabling command of the SPI FLASH;

step 8, writing the read data into the SPI FLASH through the SPI read-write module;

step 9, judging whether the page bytes are equal to 256, if the page bytes are equal to 256, performing step 10, otherwise, performing step 7;

step 10, reading the page writing state of the SPI FLASH by the SPI reading and writing module;

step 11, judging whether page writing is finished, if so, performing step 12, otherwise, performing step 10;

step 12, judging whether the written data is larger than an expected value, if so, performing step 13, otherwise, performing step 7;

step 13, judging whether the FIFO empty waiting time is more than 3 seconds, if the FIFO empty waiting time is more than 3 seconds, performing step 14, otherwise, performing step 7;

step 14, the SPI read-write module finishes writing data to the SPI FLASH;

step 15, the SPI read control logic module generates a read command of the SPI FLASH and reads the data in the SPI FLASH one by one through the SPI read-write module;

step 16, judging whether the number of the read data is equal to the number of the write data, if so, performing step 17, otherwise, performing step 15;

step 17, finishing reading data by the SPI FLASH;

step 18, judging whether the read data verification is equal to the write data verification, if the read data verification is equal to the write data verification, performing step 19, otherwise, performing step 20;

step 19, ending the updating;

step 20, giving error information.

The SPI reading control logic is as follows: after the SPI reading control logic generates a reading command, the SPI FLASH reading state information is generated and sent to the information processing module. The SPI read control logic sends a byte to the verification module for processing each time it reads out the byte.

The data checking module comprises the following processing procedures: data needs to be checked in order to ensure reliability and immunity to online updates of programs. When the data is received, the data in the FIFO buffer is sent to the check module for CRC8 check until the data reception is completed to generate a CRC8 check value of one byte. The SPI read control logic then reads back the data written into the SPI FLASH and sends the read-back data to the check module for CRC8 check, which also ultimately results in a one-byte CRC8 check value. If the CRC8 check values generated twice are equal, the updating is valid, and if the CRC8 check values are not equal, the rewriting is needed.

The information processing module comprises the following processing processes: the information processing module can detect the states generated by the SPI read-write control logic in real time, generates corresponding information according to different states and sends the corresponding information to the upper computer for processing.

According to the FPGA reconfiguration system and the method thereof based on the on-line update of the SPI FLASH, the accuracy and the reliability of the FPGA reconfiguration technology of the on-line update of the SPI FLASH are realized, the FPGA program needing to be updated is sent to system equipment in a laboratory and a high-low temperature environment warm box through serial ports, and after the update is completed and restarted, the equipment can run the updated program as required.

After the experiment platform reaches each index through examination, the method is applied to the intelligent marine comprehensive ultra-short baseline positioning system and the frogman positioning terminal, through proper software design, FPGA program updating can be carried out through a serial port, program online upgrading can be carried out through a network interface, and the performance and reliability of the method are strictly examined and verified.

It should be emphasized that the embodiments described herein are illustrative rather than restrictive, and thus the present invention is not limited to the embodiments described in the detailed description, but also includes other embodiments that can be derived from the technical solutions of the present invention by those skilled in the art.

Claims (5)

1. An FPGA reconfiguration system based on to SPI FLASH online update which characterized in that: including outside serial ports, FPGA and SPI FLASH, outside serial ports, FPGA and SPI FLASH connect gradually, FPGA is including receiving buffering FIFO module, information processing module, data check module, SPI writes control logic module, SPI reads control logic module and SPI reading and writing module, receive buffering FIFO module and connect outside serial ports respectively, SPI writes control logic module and data check module, SPI writes control logic module and connects information processing module and SPI reading and writing module respectively, SPI FLASH and SPI reading and writing control logic module are connected respectively to SPI reading and writing module, SPI reads control logic module and connects information processing module and data check module respectively.

2. The FPGA reconfiguration system based on the on-line update of the SPI FLASH according to the claim 1 is characterized in that: the SPI read-write module generates a gating signal CS, a clock signal CLK, a data sending signal MOSI and a data receiving signal MISO through a 4-wire SPI interface and a FLASH protocol to carry out data communication with the SPI FLASH.

3. The method for reconstructing the system of the FPGA based on the on-line update of the SPI FLASH according to claim 1, characterized in that: the information processing module detects states generated by the SPI read control logic module and the SPI write control logic module in real time, generates corresponding information according to different states and sends the corresponding information to the upper computer for processing.

4. A method of FPGA reconfiguration system based on-line update of SPI FLASH according to claim 1, 2 or 3, characterized by: the method comprises the following steps:

step 1, sending an FPGA program to be updated to a receiving buffer FIFO module through an external serial port, sending received data to an SPI read-write module by an SPI write control logic module according to a certain time sequence, and writing the data into an SPI FLASH by the SPI read-write module through an SPI interface;

step 2, the data in the receiving buffer FIFO module is sent to a data check module, and a written data check value is calculated;

and 3, reading the data written into the SPI FLASH one by the SPI read-write control logic through the SPI read-write module until the number of the read data is the same as that of the written data, simultaneously sending the read data to the data check module by the SPI read control logic module so as to calculate a read data check value, judging whether the written data check value is the same as that of the read data, if so, successfully updating the program on line and finishing updating, and otherwise, giving error information.

5. The method for reconstructing the system based on the FPGA for updating the SPI FLASH online according to claim 3, characterized in that: the FPGA program needing to be updated is a bin file generated by software.

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