CN110113275A - A kind of intelligence multichannel wideband interferer signal generation device - Google Patents
A kind of intelligence multichannel wideband interferer signal generation device Download PDFInfo
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- CN110113275A CN110113275A CN201910393725.4A CN201910393725A CN110113275A CN 110113275 A CN110113275 A CN 110113275A CN 201910393725 A CN201910393725 A CN 201910393725A CN 110113275 A CN110113275 A CN 110113275A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
Abstract
The invention discloses a kind of intelligent multichannel wideband interferer signal generation devices, use intelligentized design, easy to operate；Using multi-passage design, interference source module is reduced, reduces jamming equipment volume, weight, and reduce cost；Its conflicting mode is with strong points, generates corresponding interference signal for different target, interference effect reaches best；In addition, being alternatively arranged as instrument use, it to be used for lab signal generating device.
Description
Technical field
The present invention relates to interference signal technical fields more particularly to a kind of intelligent multichannel wideband interferer signal to generate dress
It sets.
Background technique
As electromagnetic environment increasingly complicates, the technology interfered radio signal is also required to constantly upgrade and change
Generation, it is desirable that the interference signal of jamming equipment want can the more flexible variation for electromagnetic environment be adjusted correspondingly, do
It disturbs signal pattern to need to change anywhere or anytime, to the generation technologies of radio-interference signals, more stringent requirements are proposed.If
Every time as the variation of interference signal requires artificially to carry out recalculating and adjusting for interference signal by computer and control software
It is whole, then in the interference signal data write to jamming equipment of generation, the whole operation time is greatly increased, when emergency event occurs
When be difficult satisfaction scene and timely use, be also faced at any time because operator it is horizontal it is irregular caused by scene interference effect
Fruit is bad, and this patent calculates automatically and generate interference signal using special technology and algorithm, realizes live interference signal intelligence
It calculates and signal exports, the operating time can be saved, simplify the operation of jamming equipment.
With the development of wireless communication technique, device for wireless communications are more and more, bring very to perturbation technique
Big difficulty, conventional conflicting mode cause equipment volume, weight increasing, and cost is higher and higher, and it is special that this patent utilizes
Technology and algorithm realize that multiple channel wideband interference signals generate in real time, can save equipment manufacturing cost, while can less equipment weight
Amount and volume.
Existing jamming equipment is mainly based on the conflicting modes such as white noise, multitone, frequency sweep, and equipment volume is huge, operation is multiple
It is miscellaneous, interference effect is bad；The currently used three kinds of jamming programs of brief description:
1) noise or Sweeping nonlinearity signal are generated with analog circuit: has certain interference effect to normal signal, but to having
The broadband target signal interference effect of modulation is not added, and can not modify frequency or frequency range, and modulation letter can not be added in interference signal
Number, and there are blindness for interference, it is difficult to reach optimum jamming effect.
2) interference signal is generated with DDS chip；Each DDS chip only can produce an interference signal, multiple if you need to generate
Signal then needs respective numbers DDS chip to need DDS number of chips more broadband target signal, and bulky, weight
Weight, needs power high, cost is high, but its overall interference effect is undesirable.
3) the modes interference signals such as multitone are generated with digit chips such as simple FPGA；Its interference signal can add related tune
System, but operating platform (notebook and control software) configuration-related data is needed, it is complicated for operation, and number of channels is up to 2,
Signal bandwidth is relatively narrow.
However, above-mentioned side's jamming program is complicated for operation, equipment volume is huge, weight is heavy, cost is high, and interferes effect
Fruit is undesirable.
Summary of the invention
The object of the present invention is to provide a kind of intelligent multichannel wideband interferer signal generation devices, and operation is intelligent,
Equipment volume is small and at low cost, and interference effect can be improved.
The purpose of the present invention is what is be achieved through the following technical solutions:
A kind of intelligence multichannel wideband interferer signal generation device, comprising: FPGA and DSP unit, the DSP unit
Inside is equipped with ARM and DSP；
The ARM for receiving the transmission power parameter of host computer transmission, and generates corresponding control instruction to described
DSP, and the running parameter of device and working condition are fed back into host computer；It is also used to control FPGA and carries out DDS mode, storage
The switching of mode and mixed mode；
The DSP, for completing the calculating of interference waveform according to parsing control instruction, then by corresponding interference waveform number
According to being transmitted to FPGA；
The FPGA is as coprocessor, in storage mode, the interference waveform data that storage DSP is calculated；In DDS mode
The lower corresponding modulation system of generation debugs interference waveform data, and passes through its internal DAC and complete digital-to-analogue conversion, generates
The interference waveform signal of simulation.
As seen from the above technical solution provided by the invention, 1) intelligentized design, it is easy to operate；2) multichannel is set
Meter reduces interference source module, reduces jamming equipment volume, weight, and reduce cost；3) conflicting mode is with strong points, for not
Corresponding interference signal is generated with target, interference effect reaches best；4) it can be used as instrument use, filled for lab signal
It sets.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of schematic diagram of intelligent multichannel wideband interferer signal generation device provided in an embodiment of the present invention；
Fig. 2 is FPGA internal dual port RAM provided in an embodiment of the present invention and DAC transmission channel schematic diagram；
Fig. 3 is DAC structure schematic diagram provided in an embodiment of the present invention；
Fig. 4 is DSP unit structural schematic diagram provided in an embodiment of the present invention；
Fig. 5 is UART chip structural schematic diagram provided in an embodiment of the present invention；
Fig. 6 is the clock topology figure of DSP unit provided in an embodiment of the present invention；
Fig. 7 is the clock scheme schematic diagram of device provided in an embodiment of the present invention；
Fig. 8 is the detailed protocol schematic diagram of power supply provided in an embodiment of the present invention；
Fig. 9 is the software program block schematic illustration of device provided in an embodiment of the present invention；
Figure 10 is program of device flow chart provided in an embodiment of the present invention.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, belongs to protection scope of the present invention.
The embodiment of the present invention provides a kind of intelligent multichannel wideband interferer signal generation device, dry using multi-channel wide band
Signal generation technology is disturbed, each channel works independently, and uses disturbance signal for different target, realizes by DSP unit
Interference signal intelligent processing is equipped with inside the DSP unit as shown in Figure 1, it specifically includes that FPGA and DSP unit
ARM and DSP；
The ARM for receiving the transmission power parameter of host computer transmission, and generates corresponding control instruction to described
DSP, and the running parameter of device and working condition are fed back into host computer；It is also used to control FPGA and carries out DDS mode, storage
The switching of mode and mixed mode；
The DSP, for completing the calculating of interference waveform according to parsing control instruction, then by corresponding interference waveform number
According to being transmitted to FPGA；
The FPGA is as coprocessor, in storage mode, the interference waveform data that storage DSP is calculated；In DDS mode
The lower corresponding modulation system of generation debugs interference waveform data, and passes through its internal DAC and complete digital-to-analogue conversion, generates
The interference waveform signal of simulation.
The device further include: display screen and key, the two are connect with the GPIO port in FPGA；
The display screen, for the running parameter of display device, working condition and calculated interference waveform data；
The key calculates interference waveform for generating key scheme driving DSP under manual operation mode.
The device further include: external memory NVRAM and Norflash, the NVRAM is for storing interference signal data；
The Norflash is for storing DPS unit program and FPGA program.
The device further include: network interface, the network interface include: sequentially connected MAC (medium access control sublayer agreement),
PHY, network transformer；Wherein, MAC is integrated in inside DPS unit, and PHY is port physical layer, network transformer realize interface every
From.
In order to make it easy to understand, doing detailed introduction below for above-mentioned apparatus.
One, FPGA.
The FPGA mainly completes the storage of interference signal, the generation of interference signal, data parallel-serial conversion.Memory is used to
Stored waveform data, DAC complete analog conversion function, digital waveform are converted into analog waveform, are mainly used for viscous and logic, mention
For the logic interfacing conversion function of peripheral components.
Referring to Figure 1, the FPGA specifically includes that GPIO port (general purpose input/output end port), interface logic mould
Block, sequential logic module, control logic module, dual port RAM, multiple DAC and multiple data parallel-to-serial converters；
Interface logic biock: the interface logic of the main communication for realizing FPGA and DSP unit (OMAP-L138), such as EMIF
The interfaces such as bus SPI UPP are realized；
Sequential logic module: main to generate logical timer and interface clock；
Control logic module: the instruction from DSP unit (OMAP-L138) is received by interface logic biock to control
GPIO DAC resets serial ports, and in addition it also controls the information such as the transmission power of RF power amplification, reading temperature current decaying and sends back
DSP unit (OMAP-L138) etc..
Described GPIO port one end connects DSP unit, and the other end connects dual port RAM by interface logic biock；Timing is patrolled
It collects module, control logic module and dual port RAM to be sequentially connected, and control logic module is also connect with interface logic biock；It is described
Dual port RAM is connect with each data parallel-to-serial converter respectively, data parallel-to-serial converter and the one-to-one connection of DAC.
Illustratively, FPGA is used as coprocessor type selecting mainly to consider in a device:
1) LVDS (oserdes) rate needs to reach 1200Mb/s；
2) IO (input/output port): assuming that being equipped with 4 DAC in FPGA, then needing 156 IO, EMIFA to need 44,
UPP bus interface 50, serial ports 12, (EMIFA UPP bus is connected to OMAP-L138 by FPGA IO to IO 50, by FPGA
Internal interface logic realizes communication), so the IO number in design should be not less than 312；
3) data storage method refers to Fig. 2, and which show FPGA internal dual port RAM and DAC transmission channel.Such as Fig. 2 institute
Show, if DAC maximum speed is 1.2GSPS, bandwidth 1.2G*14=16.8GHZ, this also requires memory read data
Speed will also reach 16.8G bandwidth, be provided by the dual port RAM inside FPGA, need in frequency resolution 5K 1.2GSPS
240K point is stored, each point 14bit, 4 DAC need the memory space of 14M, thus can choose XC7K410T.
In the embodiment of the present invention, DAC can choose AD9736, and structure is as shown in Figure 3；Its sampling with 1200MSPS
Rate, 1 tunnel output, can produce the multicarrier of up to respective nyquist frequency, 14 resolution ratio, and output electric current can be
It is programmed in 8.66mA to 31.66mA range, the total power consumption under 1.8V and 3.3V power supply power supply bypass mode is 380mW.
Two, DSP unit.
Referring to Figure 1, ARM and DSP and a series of peripheral interfaces are integrated in the DSP unit；It is described a series of outer
Enclosing interface at least includes: the GPIO port connecting with the GPIO port in FPGA, is mainly used as interruption generation and the interface of FPGA
It is reserved；The port UART, is connected to FPGA serial ports and some instructions relevant to DAC are deposited as the data under memory module download to
In reservoir；The port EMIFA, DSP program storage NORFLASH read-write, the command communication with FPGA；The port UPP, with FPGA's
Data transmission, the biggish data of data volume, it is fast that this interface ratio EMIFA transmits data；The port EMIFB being connect with mDDR, fortune
Row memory interface, data power down are lost.
DSP unit be used as in a device main control unit mainly realize aobvious control, signal modulation, FPGA Wave data load,
Communicated with host computer, radio communication control, power amplifier communication control function, function is more done by monokaryon if be likely to result in
System real-time response is poor, so being handled using dual core processor, ARM is advantageous to display, control, communication etc., and DSP is to letter
Number modulation is advantageous, and OMAP-L138 is at a ARM+DSP double-core based on ARM926EJ-S and C674x that TI company releases
Reason, two core dominant frequency can reach 456MHz, and C674x can reach 3648MIPS and 2746MFLOPS in performance, have rich
Rich peripheral interface such as network interface, serial ports, USB2.0, SATA, NANDFlash, Mddr/DDR2 controller, LCD show, upp,
EDMA3, SPI, IO abundant are able to satisfy the requirement of our projects, and there are also certain scalabilities, and system is facilitated to increase it
Its function, structure are as shown in Figure 4.
Three, memory.
As long as memory described in the embodiment of the present invention refers to: FPGA program load with memory (Norflash of Fig. 1),
DSP unit program load with memory (i.e. the Norflash of Fig. 1), waveform solidification memory (NVRAM), DSP unit RAM,
FPGA RAM。
1, memory is used in FPGA program load.
As shown in table 1, Master Serial, Master SelectMAP, Slave SelectMAP, Slave Serial
Mode is FPGA special purpose interface agreement, and use environment is restricted.Master BPI mode is stored using parallel port FLASH
Bitstream file can achieve maximum configured rate, but disadvantage is it is obvious that pin occupies too much.Master SPI mould
Formula uses the FLASH of SPI interface, and occupancy pin is few, and rate is very fast, but attainable maximum velocity ratio BPI mode wants small.If
FPGA is of less demanding to the program load time in meter, so the load of FPGA program uses SPI FLASH mode, 7 series of products journeys
Sequence is larger so the FLASH of the compatible 256Mb depth of the encapsulation of selection N25Q128A13ESF40F, SOP2-16 facilitates extension.Program
Code may include two versions, and two versions correspond respectively to DDS mode and memory module so there is two panels on hardware
Which program SPIFLASH, FPGA program specifically load by ARM control or logic to realize.
| Configuration Mode | M [2:0] | Bus Width | CCLK Direction |
| Master Serial | 000 | x1 | Output |
| Master SPI | 001 | X1, x2, x4 | Output |
| Master BPI | 010 | X8, x16 | Output |
| Master SelectMAP | 100 | X8, x16 | OutPut |
| JTAG | 101 | x1 | Not Applicable |
| Slave SelectMAP | 110 | X8, x16, x32(1) | Input |
| Slave Serial(2) | 111 | x1 | Input |
1 FPGA configuration mode of table
2, memory is used in DSP unit program load.
The DPS unit program includes: ARM program and DSP program；There are DSP and ARM two parts in ROM inside DPS unit
Start code, the BOOTLOADER of DSP is first run after DPS unit electrification reset, is loaded by PRU (may be programmed real-time unit)
ARM initial code, then DSP enables the power supply of ARM by PSC (power supply and sleeping controller), runs ARM's
DSP is placed in reset state by BOOTLOADER, ARM, and closes its clock, and ARM reads BOOT setting and user is selected Norflash
Code be transported in memory, and PC pointer is write into program entry address, completes ARM starting, reset shape ensuring that DSP is in
Under state, HOSTCFG1 register is written in the entry address of DSP code by ARM, and the entry address of DSP requires 1K byte-aligned, ARM
The clock (i.e. PSC0.MDCTL15 [NEXT]=3) of enabled DSP, enables DSP on piece memory to be accessed.ARM loads DSP generation
Code DSP for operating system of the ARM using tape file system can be used as the file storage of file system, if made
With DSP LINK, directly parsing .out file is driven to be loaded, for not file system scene usually by DSP code
Be converted into binary file, storage specified position on a flash, ARM code from designated position according to file organization format into
Row reads load.ARM discharges reset PSC0.MDCTL15 [LRST]=1, DSP of DSP from the entry address that HOSTCFG1 is arranged
It brings into operation, the code based on the above start-up course DSP and ARM can be put into same medium, and ARM is also possible to that file can be used
System and operating system occupied space are larger, and OMAP-L138 has ECC, in addition to software development speed is faster and development board
Selection is the same as a NANDFLASH K9F1G08U0A-Y, P.
3, waveform solidifies memory.
Waveform solidification memory is used to store cured Wave data, and DAC operation is fastly most 1.2GSPS, 14 bit resolutions,
System needs the frequency resolution of 5k, and if there is 4 road DAC, then the memory space needed is 4 × (1.2G/5K) × 16=
The space 15.36Mb.2 NVRAM CY14B116N are selected in design.Two panels DAC stored waveform is given per a piece of.
4, DSP unit RAM.
At runtime, internal RAM is smaller by DSP and ARM, DSP core (32KB L1P 32KB L1D 256KBL2) ARM core
(16KB instruction buffer 16KB data buffer storage) maps maximum support 256MB by handbook memory space so needing to add external RAM
Space memory, in the embodiment of the present invention can in select RAM of the K4T1G164QF-BCE7 as DSP unit.
Four, UART (universal asynchronous receiving-transmitting transmitter) port.
Signal source is by the way that serial ports controls two-way power amplifier respectively, two-way radio frequency (can connect one after each digital analog converter in Fig. 1
Radio frequency and a power amplifier), four serial ports are needed, the MAX3232ESE+ of magnesium letter may be selected, chip structure can be found in Fig. 5.
Five, network interface.
Network interface is mainly made of MAC, PHY (port physical layer), network transformer, and wherein MAC is in OMAP-L138 collection
At.
1) LAN8710A may be selected in PHY:PHY, it is a high-performance, small package, 10base-T/100BASE-TX
Microchip chip, it realizes the repertoire of MII/RMII sublayer, PCS, PMA, PMD, MDI.
2) network transformer: may be selected YT37-1107S, realize interface isolation.
Six, clock.
In the embodiment of the present invention, clock demand can be determined according to the specific type selecting of device each inside device, table 2 is exemplary
Give clock demand.
2 system clock demand of table
The clock topology of DSP unit is as shown in fig. 6, DSP unit needs two clocks: 1, System Clock Reference；2, when RTC
Clock.Specific targets are as shown in table 3, and CVDD is 1.25V or so.
The clock of 3 DSP unit of table inputs demand
DAC type selecting is if it is AD9736, since DAC AD9736 supports that highest 1.2GSPS speed, its clock maximum are
Its clock input requirements of 1.2GHz are as shown in table 4
The requirement of Fig. 4 DAC input clock
So clock selecting is preferably more than or equal to 1.2GHz, it can be ADF4350 that clock module, which exports master clock chip,
Its reference frequency output is: 137.5MHz to 4400MHz, may be programmed 1/2/4/8/16 clock output, and shake is less than 0.5ps
Rms (representative value).It output power -4dBm-+5dBm and is exported for AC coupled, its output characteristics is as shown in table 5.
The output characteristics of Fig. 5 DAC
Based on above-mentioned introduction, the clock scheme of whole device can be as shown in Figure 7: the clock that DAC clock module generates
(1.2GHz clock) generates the DAC inside multipath clock (4 road 1.2GHz) one-to-one supply FPGA by clock distributor, and
FPGA is returned to after DAC is distributed, sends back corresponding DAC after doing synchronization process by FPGA；It is certain by there is source crystal oscillator to generate
The clock of frequency (20MHz), and by (system clock of the frequency multiplication to 200MHz) as FPGA after FPGA frequency multiplication；
By have source crystal oscillator generate certain frequency (24MHz) clock, and by after DSP unit frequency multiplication with after frequency dividing (by it
Portion PLL generates 150MHz and other frequency-dividing clocks) for the logic inside ARM, DSP and FPGA；Inside DSP unit when RTC
The clock of PHY is generated by different crystal in clock and network interface, and specific as shown in table 2, crystal 32.768K clock is for RTC, crystal
25M clock is for PHY.
Seven, power supply designs
Power supply design is carried out below with reference to the specific type selecting of device each inside device, device internal components power consumption and power supply need
It asks respectively as shown in table 6, table 7.
6 device power consumption of table
| Serial number | Voltage network | Voltage (V) | Electric current (mA) |
| 1 | VCC_1V0 | 1 | 6528 |
| 2 | VCC_1V3 | 1.3 | 987.3 |
| 3 | VCC_1V8 | 1.8 | 1211 |
| 4 | FPGA_2V5 | 2.5 | 289 |
| 5 | VCC_3V3 | 3.3 | 530.25 |
| 6 | VCC_5V0 | 5 | 507 |
| 7 | VCC_3V3_DAC | 3.3 | 100 |
| 8 | VCC_1V8_DAC | 1.8 | 188 |
| Total power consumption | 15.844w |
7 system power supply demand of table
There are 8 tunnels according to power supply shown in table 7, installation's power source efficiency calculates total power consumption the largest of about 19805W by 80%.Power supply it is detailed
Thin scheme can be found in Fig. 8.
It is introduced above mainly for the hardware configuration of device, to guarantee hardware energy works fine, need to realize hardware
Software function is described in detail mainly for software below.
As shown in figure 9, being the software program frame of device.Entire software program is divided into DSP unit (that is, OMAP-L138)
With FPGA two parts, OMAP-L138 is divided to for two cores: ARM core is ARM926EJ-S, and DSP core is C674x.Program circuit is as schemed
Shown in 10, left part be generate interference signal generate process, right side be mainly system initialization, process of self-test, communication process,
The signal that instruction execution and information are shown.
1, ARM program major function includes:
1) has the communication function between main control computer, main control computer can realize reserved frequency, transmission power ginseng
Number setting, while the working condition of real-time monitoring jammer；
2) Keyboard Control working condition and setting parameter can be received by panel；
3) has remote code upgrading more new function, the code of ARM, FPGA, DSP can be realized remotely more by network interface
Newly；
4) there is module self-checking function (radio frequency, power amplifier voltage and current detecting, FLASH, DDR3, serial ports, SD card)；
5) have the function of that running parameter reports host computer；
6) there is control FPGA, carry out DDS mode, memory module, mixed mode handoff functionality；
7) the control management of radio frequency, power amplifier: the state reading and control of radio frequency, power amplifier
8) the starting guidance of ARM, DSP.
2, DSP program major function includes:
1) interference waveform (multitone, comb spectrum, linear frequency modulation, white noise, modulation etc.) computing function；
2) receive ARM order and parse；
3) it loads, solidify interference waveform, interference signal control；
4) modulation bandwidth: narrowband is 5kHz~200kHz；Broadband is 1MHz~20MHz.
3, FPGA program major function includes:
1) memory module: the Wave data that storage PC/DSP is calculated；
2) operating mode: receiving ARM control instruction, carries out DDS mode, memory module, mixed mode switching；
3) control of 4 road DAC
4) read-write of SPI FLASH
5) logical transition of serial ports
6) have the function of that running parameter is reported to ARM；
7) FM, CW, AM, ASK, 2FSK, 4FSK, 8PSK, BPSK, QPSK, 16QAM, 64QAM modulation methods DDS mode: are generated
Formula；
8) carrier frequency quantity: 8/channel；
9) guarantee output frequency accuracy: broadband signal ,≤bandwidth * 5%；Tone signal ,≤fo × 10-6Hz；
10) spectral resolution :≤100Hz (DDS mode)；≤ 5KHz (memory module).
Above scheme major advantage of the embodiment of the present invention is as follows:
1) intelligentized design, it is easy to operate；Only a cable is needed to be connected to PC, passes through an APP on PC
Control all operationss of equipment.
2) multi-passage design reduces interference source module, reduces jamming equipment volume, weight, and reduce cost.
Two times that prior-generation product channels number is original are compared using 4 channels TX in design, and control circuit area ratio
Originally equipment is also small, and cost reduces by 50%.
3) conflicting mode is with strong points, generates corresponding interference signal for different target, interference effect reaches best；Below
Illustratively provide for the conflicting mode under different frequency range:
4) it can be used as instrument use, be used for lab signal generating device.
Support FM, CW, AM, ASK, 2FSK, 4FSK, 8PSK, BPSK, QPSK, 16QAM modulation system, modulation bandwidth: narrow
Band: 5kHz~200kHz；Broadband: 1MHz~25MHz, carrier frequency quantity: at least four, with interior any single-tone, multitone or comb wave
Shape；With other user-defined random waveforms such as interior any frequency sweep, broadband noise.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Within the technical scope of the present disclosure, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Subject to enclosing.
Claims (8)
1. a kind of intelligence multichannel wideband interferer signal generation device characterized by comprising FPGA and DSP unit, it is described
DSP unit inside be equipped with ARM and DSP；
The ARM for receiving the transmission power parameter of host computer transmission, and generates corresponding control instruction to the DSP, with
And the running parameter of device and working condition are fed back into host computer；Be also used to control FPGA carry out DDS mode, memory module with
The switching of mixed mode；
The DSP is used to complete the calculating of interference waveform, then corresponding interference waveform data are passed according to parsing control instruction
Transport to FPGA；
The FPGA is as coprocessor, in storage mode, the interference waveform data that storage DSP is calculated；It is produced under DDS mode
Raw corresponding modulation system debugs interference waveform data, and completes digital-to-analogue conversion by its internal DAC, generates simulation
Interference waveform signal.
2. a kind of intelligent multichannel wideband interferer signal generation device according to claim 1, which is characterized in that described
FPGA include: GPIO port, interface logic biock, sequential logic module, control logic module, dual port RAM, multiple DAC and
Multiple data parallel-to-serial converters；
Described GPIO port one end connects DSP unit, and the other end connects dual port RAM by interface logic biock；Sequential logic mould
Block, control logic module and dual port RAM are sequentially connected, and control logic module is also connect with interface logic biock；The twoport
RAM is connect with each data parallel-to-serial converter respectively, data parallel-to-serial converter and the one-to-one connection of DAC；
The interface logic biock realizes the interface logic that FPGA is communicated with DSP unit；Sequential logic module, when generating logic
Clock and interface clock；Control logic module: the instruction from DSP unit is received by interface logic biock and is patrolled accordingly
Collect control.
3. a kind of intelligent multichannel wideband interferer signal generation device according to claim 1 or 2, which is characterized in that
The device further include: display screen and key, the two are connect with the GPIO port in FPGA；
The display screen, for the running parameter of display device, working condition and calculated interference waveform data；
The key calculates interference waveform for generating key scheme driving DSP under manual operation mode.
4. according to claim 1 or a kind of described intelligent multichannel wideband interferer signal generation device, which is characterized in that institute
It states and is integrated with ARM and DSP and a series of peripheral interfaces in DSP unit；A series of peripheral interfaces include at least: with
GPIO port, the port UART, the port EMIFA and the port UPP of GPIO port connection in FPGA, connect with external memory
The port EMIFA and the port EMIFB being connect with mDDR.
5. according to claim 4 or a kind of intelligent multichannel wideband interferer signal generation device, which is characterized in that institute
State external memory, comprising: NVRAM and Norflash, the NVRAM are for storing interference signal data；The Norflash
For storing DPS unit program and FPGA program.
6. according to claim 5 or a kind of intelligent multichannel wideband interferer signal generation device, which is characterized in that institute
Stating DPS unit program includes: ARM program and DSP program；
There are DSP and ARM two parts to start code in ROM inside DPS unit, the BOOTLOADER of DSP after DPS unit electrification reset
It first runs, ARM initial code is loaded by PRU, then DSP enables the power supply of ARM by PSC, runs ARM's
DSP is placed in reset state by BOOTLOADER, ARM, and closes its clock, and ARM reads BOOT setting and user is selected Norflash
In code be transported in memory, and PC pointer is write into program entry address, completes ARM starting, resetted ensuring that DSP is in
Under state, HOSTCFG1 register is written in the entry address of DSP code by ARM, and the entry address of DSP requires 1K byte-aligned,
ARM enables the clock of DSP, and DSP on piece memory is accessed.
7. a kind of intelligent multichannel wideband interferer signal generation device according to claim 1, which is characterized in that the dress
It sets further include: network interface, the network interface include: sequentially connected MAC, PHY, network transformer；Wherein, MAC is integrated in DPS unit
Inside, PHY are port physical layer, and network transformer realizes interface isolation.
8. a kind of intelligent multichannel wideband interferer signal generation device according to claim 1, which is characterized in that the dress
It is as follows to set internal clock scheme:
The clock that DAC clock module generates generates the DAC inside one-to-one supply FPGA of multipath clock by clock distributor,
And FPGA is returned to after DAC is distributed, corresponding DAC is sent back after doing synchronization process by FPGA；By there is source crystal oscillator to generate one
Determine the clock of frequency, and by the system clock after FPGA frequency multiplication as FPGA；
By have source crystal oscillator generate certain frequency clock, and by after DSP unit frequency multiplication with after frequency dividing for ARM, DSP and other outside
Portion's equipment uses；The clock of PHY is generated by different crystal in DSP unit inside RTC clock and network interface.
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