CN114116565B - Circuit compatible with PCI and PCIE buses, card board and computing equipment - Google Patents

Circuit compatible with PCI and PCIE buses, card board and computing equipment Download PDF

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Publication number
CN114116565B
CN114116565B CN202111421014.7A CN202111421014A CN114116565B CN 114116565 B CN114116565 B CN 114116565B CN 202111421014 A CN202111421014 A CN 202111421014A CN 114116565 B CN114116565 B CN 114116565B
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China
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circuit
bus
pci
pcie
information
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CN202111421014.7A
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CN114116565A (en
Inventor
霍炳秀
刘炳坤
刘海玲
朱恒飞
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Tianjin Embedtec Co Ltd
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Tianjin Embedtec Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application provides a circuit, cardboard and equipment compatible PCI and PCIE bus, and this circuit includes: using a PCIE connection circuit, a switching circuit receives first bus information and first clock information of the PCIE circuit, sends the first clock information to a clock synchronization circuit to be output as a reference clock, and outputs the first bus information as bus output information; the PCI connection circuit is used, the clock synchronous control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronous control circuit through the selection of the switching circuit to be output by referring to the clock most, the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, second bus information is generated, and the second bus information is selected as bus output information through the switching circuit to be output. According to the PCI bus connection circuit and the PCI E bus connection circuit, the PCI bus connection circuit and the PCI E bus connection circuit are designed into one circuit, so that one circuit can be connected with a PCI bus or a PCI bus, and the card board compatibility is improved.

Description

Circuit compatible with PCI and PCIE buses, card board and computing equipment
Technical Field
The present application relates to a bus connection circuit, and more particularly to a circuit compatible with PCI and PCIE buses. The application also relates to a card board compatible with PCI and PCIE buses, a method compatible with PCI and PCIE buses and a computing device.
Background
The PCI bus specification was proposed in the 90 s of the 20 th century to quickly unify various types of local buses that coexist at that time, to which most peripheral devices of the processor system are directly or indirectly connected. One milestone in the history of the development of computing device architecture on the PCI bus, and PCIE is a new generation of I/O local bus standard, a revolutionary bus architecture that replaces the PCI bus. Even if the PCI bus gradually replaces the PCI bus, the importance of the PCI bus in the field of computing devices cannot be masked.
In the hardware circuit, the PCIE bus inherits the design thought of the PCI bus, and is different from the shared parallel architecture of the PCI bus, and the PCIE bus can support higher frequency by using a high-speed serial transmission mode, so that connected devices do not share bus bandwidth like the PCI bus. From the software level, the PCIE bus is basically compatible with the PCI bus in the system software, the difficulty of the system software from the original PCI bus system architecture system to the PCIE system architecture is reduced to the greatest extent, and the development of the driver is ensured to be consistent.
The PCI bus is completely different from the PCIE bus equipment in terms of parallel bus and serial bus respectively on the hardware circuit connection with the computing equipment, so that the golden finger connectors of the PCI bus and the PCIE bus are completely different. The transition from the PCI bus device to the PCIE bus device completely requires a new device to be designed, and in the complete PCI system computing device and the complete PCIE system device, the PCI or PCIE device interface cards cannot be replaced with each other, and the interfaces with the same function cannot adapt to the complete PCIE bus device and the complete PCIE bus device, so that the PCI bus and the PCIE bus device hardware cannot be compatible.
Disclosure of Invention
In order to solve the problem that the PCI bus and the PCIE bus cannot be compatible in the current technical scheme, the application provides a circuit compatible with the PCI bus and the PCIE bus, a card board compatible with the PCI bus and the PCIE bus, a method compatible with the PCI bus and the PCIE bus and a computing device.
The application provides a circuit compatible with PCI and PCIE buses, comprising: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit;
when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information;
when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit through the selection of the switching circuit to be output by referring to the clock most, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit.
Optionally, the power supply circuit is connected with an external complete machine through a PCI connection circuit or a PCIE connection circuit, and obtains a power supply from the external complete machine.
Optionally, the switching circuit includes: and switching light for switching channels of the first bus information and the second bus information.
Optionally, the PCI connection circuit and the PCIE connection circuit are connected with an external whole machine through a golden finger.
Optionally, the PCI connection circuit and the PCIE connection circuit respectively correspond to golden fingers that are disposed on different sides of the card board.
The application also provides a card board compatible with PCI and PCIE buses, comprising: and the PCI connecting circuit and the golden fingers of the PCIE connecting circuit are respectively arranged on two sides of the clamping plate.
The application also provides a method for compatible PCI and PCIE buses, comprising the following steps:
setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data, and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting PCIE bus format data acquired by the PCIE bus interface.
The application also provides a computing device, which adopts a circuit compatible with PCI and PCIE buses, wherein the circuit compatible with PCI and PCIE buses comprises: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit;
when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information;
when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit through the selection of the switching circuit to be output by referring to the clock most, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit.
Optionally, the power supply circuit is connected with an external complete machine through a PCI connection circuit or a PCIE connection circuit, and obtains a power supply from the external complete machine.
Optionally, the switching circuit includes: and switching light for switching channels of the first bus information and the second bus information.
Compared with the prior art, the application has the advantages that:
the application provides a circuit compatible with PCI and PCIE buses, comprising: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit; when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information; when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit through the selection of the switching circuit to be output by referring to the clock most, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit. The PCI bus connection circuit and the PCIE bus connection circuit are designed into one circuit, data format conversion is carried out, and then the data format conversion is output, so that the PCI bus can be connected with one circuit, the PCIE bus can be connected with the other circuit, and the compatibility of the PCI bus and the PCIE bus is realized.
Drawings
Fig. 1 is a schematic diagram of a circuit compatible with PCI and PCIE buses in the present application.
Fig. 2 is a schematic diagram of a card board compatible with PCI and PCIE buses in the present application.
Detailed Description
The following are examples of specific implementation provided for the purpose of illustrating the technical solutions to be protected in this application in detail, but this application may also be implemented in other ways than described herein, and one skilled in the art may implement this application by using different technical means under the guidance of the conception of this application, so this application is not limited by the following specific embodiments.
The application provides a circuit compatible with PCI and PCIE buses, comprising: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit; when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information; when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit through the selection of the switching circuit to be output by referring to the clock most, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit. The PCI bus connection circuit and the PCIE bus connection circuit are designed into one circuit, data format conversion is carried out, and then the data format conversion is output, so that the PCI bus can be connected with one circuit, the PCIE bus can be connected with the other circuit, and the compatibility of the PCI bus and the PCIE bus is realized.
Fig. 1 is a schematic diagram of a circuit compatible with PCI and PCIE buses in the present application.
Referring to fig. 1, the circuit described in the present application includes: the PCI bus interface circuit comprises a PCI connection circuit 101 and a PCIE connection circuit 102, wherein the PCI connection circuit 101 is used for connecting a PCI bus interface of an external complete machine, and the PCIE connection circuit 102 is used for connecting a PCIE bus interface of the external complete machine.
The PCIE connection circuit 102 and the PCI connection circuit 101 are connected with a power supply circuit 105, the power supply circuit 105 obtains power from an external host through the PCI connection circuit 101 and the PCIE connection circuit 102, and the power supply is processed in the power supply circuit 105 to supply power to the conversion circuit 103, the switching circuit 106, and the clock synchronization control circuit 104, respectively.
In this application, the power supply circuit 105 is connected to an external whole machine through the PCI connection circuit 101 or the PCIE connection circuit 102, and obtains power from the external whole machine. The PCI link circuit 101 and the PCIE link circuit 102 actually use only one, and therefore the power supply circuit 105 directly transmits the=3.3v auxiliary power supply of the PCI link circuit 101 or the PCIE link circuit 102 to the subsequent stage. The PCIE connection circuit 102 provides a main power supply of +12v, and the power supply circuit 105 converts the +12v main power supply into a +5v power supply, and connects the +12v power supply to the first relay, and then to the ground. The main power supplied by the PCI connection circuit 101 is +5v power, and the +5v power is connected to the second relay and then to the ground.
The PCIE connection circuit 102 and the PCI connection circuit 101 actually use only one end, and thus, depending on the PCIE connection circuit 102 or the PCI connection circuit 101 used, the corresponding main power supply is used to transmit to the subsequent circuit.
The auxiliary power supply described herein will be converted to 1.8V power for use by the switching circuit 106, and the main power supply will be provided for use by other circuits than the switching circuit 106.
In this application, when the PCIE connection circuit 102 is used, the switching circuit 106 receives the first bus information and the first clock information of the PCIE circuit by the power supply of the power supply circuit 105, sends the first clock information to the clock synchronization circuit as a reference clock output, and outputs the first bus information as bus output information.
Specifically, the clock synchronization control circuit 104 includes a clock synchronization chip, and the chip processes the first clock signal transmitted by the PCIE connection circuit 102 to implement clock synchronization of all PCIE interface chips. The clock synchronization control circuit 104 further comprises a crystal oscillator for outputting a second clock signal, which is also transmitted to the switching circuit 106. The switching circuit 106 includes: and switching light for switching channels of the first bus information and the second bus information. The switching circuit 106 is configured to switch the first clock signal and the second clock signal, and switch to the first clock signal when the PCIE connection circuit 102 is used.
The first clock signal is processed by the switching circuit 106 and is referred to herein as a third clock signal, which is returned to the clock synchronization controller and processed by the clock synchronization controller to generate a fourth clock signal and a fifth clock signal.
The fourth clock signal will be sent to the next stage functional circuit and the fifth clock signal will be sent to the conversion circuit 103.
The PCIE connection circuit 102 sends the first bus information to the switching circuit 106, and sends the first bus information to the next functional circuit after passing through the switching circuit 106.
When the PCI connection circuit 101 is used, the clock synchronization control circuit 104 generates a second clock signal by supplying power from the power supply circuit 105, the second clock signal is returned to the clock synchronization control circuit 104 by selecting the switching circuit 106, and is sent to the conversion circuit 103, the conversion circuit 103 receives the second clock signal and the second input information of the PCI connection circuit 101, and generates second bus information, and the second bus information is selected as bus output information by selecting the switching circuit 106.
Specifically, when the PCI connection circuit 101 is used, the second clock information is switched to third clock information, and fifth clock information generated from the third clock information is input to the conversion circuit 103.
The conversion circuit 103 receives the input information of the PCI connection circuit 101 and generates second service information according to the fifth clock information. The conversion circuit 103 further receives the first reset information transmitted by the PCIE connection circuit 102, and the second reset information and the first reset information are processed by and logic to generate third reset information.
The input information of the PCI link circuit 101 is converted into information in PCIE bus format through serial-parallel conversion, and the information is transmitted to the switching circuit 106 together with the third reset information through the second bus, which is referred to herein as second bus information.
The second bus information is passed through the switching circuit 106 and then passed to the next stage of functional circuits.
Preferably, the PCI connection circuit 101 and the PCIE connection circuit 102 are connected to an external whole machine through a golden finger. The golden fingers respectively corresponding to the PCI connection circuit 101 and the PCIE connection circuit 102 are arranged on different sides of the card board.
The application also provides a card board compatible with PCI and PCIE buses, wherein the card board is provided with the circuit compatible with PCI and PCIE buses, and the PCI connecting circuit 101 and the golden fingers of the PCIE connecting circuit 102 are respectively arranged on two sides of the card board.
Fig. 2 is a schematic diagram of a card board compatible with PCI and PCIE buses in the present application.
Referring to fig. 2, the card board is provided with two groups of golden fingers respectively located at different sides of the card board, preferably, the two groups of golden fingers are respectively located at opposite sides of the card board.
The application also provides a method for compatible PCI and PCIE buses, which is realized by adopting the circuit compatible with PCI and PCIE buses.
Specifically, the method comprises the following steps: setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data, and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting PCIE bus format data acquired by the PCIE bus interface.
The specific data transfer and conversion flow of the method compatible with the PCI and PCIE buses is consistent with the circuit description of the compatible PCI and PCIE buses, and is not described herein again.
The application also provides a computing device, the computing device adopts the circuit compatible with the PCI and PCIE buses to realize a bus interface, and the circuit compatible with the PCI and PCIE buses includes: the PCI interface circuit 101 and the PCIE interface circuit 102 are alternatively used.
When the PCIE connection circuit 102 is used, the switching circuit 106 receives the first bus information and the first clock information of the PCIE circuit through power supply of the power supply circuit 105, sends the first clock information to the clock synchronization circuit to be output as a reference clock, and outputs the first bus information as bus output information;
when the PCI connection circuit 101 is used, the clock synchronization control circuit 104 generates a second clock signal by supplying power from the power supply circuit 105, the second clock signal is returned to the clock synchronization control circuit 104 by selecting the switching circuit 106, and is sent to the conversion circuit 103, the conversion circuit 103 receives the second clock signal and the second input information of the PCI connection circuit 101, and generates second bus information, and the second bus information is selected as bus output information by selecting the switching circuit 106.
Preferably, the power supply circuit 105 is connected to an external whole machine through the PCI connection circuit 101 or the PCIE connection circuit 102, and obtains power from the external whole machine.
Preferably, the switching circuit 106 includes: and switching light for switching channels of the first bus information and the second bus information.

Claims (10)

1. A circuit compatible with PCI and PCIE buses, comprising: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit;
when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information;
when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit to be output most by referring to a clock through the selection of the switching circuit and is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit;
the PCI connection circuit is used for connecting a PCI bus interface of the external whole machine, and the PCI connection circuit is used for connecting a PCI bus interface of the external whole machine.
2. The PCI and PCIE bus compatible circuit according to claim 1 wherein said power supply circuit is connected to an external complete machine through a PCI connection circuit or a PCIE connection circuit and obtains power from said external complete machine.
3. The PCI and PCIE bus compatible circuit as defined in claim 1 wherein said switching circuit comprises: and switching light for switching channels of the first bus information and the second bus information.
4. The PCI and PCIE bus compatible circuit as defined in claim 1 wherein said PCI connection circuit and said PCIE connection circuit are connected to an external device by a gold finger.
5. The circuit compatible with PCI and PCIE buses of claim 4 wherein said PCI connection circuit and said PCIE connection circuit are respectively arranged on different sides of said card board.
6. A card board compatible with PCI and PCIE buses, wherein any one of the PCI and PCIE bus compatible circuits of claims 1 to 5 is arranged on the card board, and golden fingers of the PCI connection circuit and the PCIE connection circuit are respectively arranged on two sides of the card board.
7. A method for compatible PCI and PCIE buses, comprising:
setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data, and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting PCIE bus format data acquired by the PCIE bus interface.
8. A computing device, wherein the circuitry for using the PCI and PCIE bus compatible as defined in any one of claims 1 to 5, the circuitry for using the PCI and PCIE bus compatible comprises: the switching circuit is used for switching the switching circuit to the switching circuit, and switching the switching circuit to the switching circuit;
when a PCIE connection circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to be used as reference clock output, and outputs the first bus information as bus output information;
when the PCI connection circuit is used, through the power supply of the power supply circuit, the clock synchronization control circuit sends out a second clock signal, the second clock signal is returned to the clock synchronization control circuit through the selection of the switching circuit to be output by referring to the clock most, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and the second input information of the PCI connection circuit, generates second bus information, and the second bus information is selected to be output as bus output information through the switching circuit.
9. The computing device of claim 8, wherein the power circuit is connected to an external overall machine through a PCI connection circuit or a PCIE connection circuit and obtains power from the external overall machine.
10. The computing device of claim 8, wherein the switching circuit comprises: and switching light for switching channels of the first bus information and the second bus information.
CN202111421014.7A 2021-11-26 2021-11-26 Circuit compatible with PCI and PCIE buses, card board and computing equipment Active CN114116565B (en)

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CN111934859A (en) * 2020-07-22 2020-11-13 北京三未信安科技发展有限公司 Cipher card communication method, cipher card and computer equipment

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