CN114116565A - Circuit, cardboard and computing equipment of compatible PCI and PCIE bus - Google Patents

Circuit, cardboard and computing equipment of compatible PCI and PCIE bus Download PDF

Info

Publication number
CN114116565A
CN114116565A CN202111421014.7A CN202111421014A CN114116565A CN 114116565 A CN114116565 A CN 114116565A CN 202111421014 A CN202111421014 A CN 202111421014A CN 114116565 A CN114116565 A CN 114116565A
Authority
CN
China
Prior art keywords
circuit
bus
pci
pcie
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202111421014.7A
Other languages
Chinese (zh)
Other versions
CN114116565B (en
Inventor
霍炳秀
刘炳坤
刘海玲
朱恒飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin Embedtec Co Ltd
Original Assignee
Tianjin Embedtec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin Embedtec Co Ltd filed Critical Tianjin Embedtec Co Ltd
Priority to CN202111421014.7A priority Critical patent/CN114116565B/en
Publication of CN114116565A publication Critical patent/CN114116565A/en
Application granted granted Critical
Publication of CN114116565B publication Critical patent/CN114116565B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application provides circuit, cardboard and equipment of compatible PCI and PCIE bus, this circuit includes: the PCIE circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit, the first clock information is sent to the clock synchronization circuit to be output as a reference clock, and the first bus information is output as bus output information; and the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information. According to the application, the PCI bus connecting circuit and the PCIE bus connecting circuit are designed into one circuit, so that one circuit can be connected with both the PCI bus and the PCIE bus, and the compatibility of the clamping plates is improved.

Description

Circuit, cardboard and computing equipment of compatible PCI and PCIE bus
Technical Field
The present application relates to a bus connection circuit, and more particularly, to a circuit compatible with PCI and PCIE buses. The application also relates to a card board compatible with the PCI and PCIE buses, a method compatible with the PCI and PCIE buses and a computing device.
Background
The PCI bus specification was introduced in the 90's of the 20 th century to quickly unify various local buses that existed at the time, so far, most of the peripheral devices of the processor system were directly or indirectly connected to the PCI bus. While PCI has been a milestone in the development of computing device architectures on the PCI bus, PCIE is a new generation of I/O local bus standard, a revolutionary bus architecture that replaces the PCI bus. Even though the PCI express bus gradually replaces the PCI bus, the importance of the PCI bus in the field of computing devices cannot be covered.
On a hardware circuit, a PCIE bus inherits the design idea of a PCI bus, and is different from a shared parallel architecture of the PCI bus, the PCIE bus uses a high-speed serial transmission mode and can support higher frequency, and connected devices do not share bus bandwidth like the PCI bus. From the software aspect, the PCIE bus maintains basic compatibility between the system software and the PCI bus, which reduces the difficulty of the system software from the original PCI bus architecture system to the structure of the PCIE system to the maximum extent, and ensures consistency in the development of the driver.
On the hardware circuit connection with the computing device, the PCI bus is completely different from the PCIE bus device, and is respectively in the form of a parallel bus and a serial bus, so that the two golden finger connectors are completely different. The transition from the PCI bus device to the PCIE bus device completely requires designing a new device, and in the PCI architecture computing device complete machine and the PCIE architecture complete machine, the PCI or PCIE device interface cards cannot be replaced with each other, and the interfaces with the same function cannot adapt to the two computing device complete machines, so that the device hardware of the PCI bus and the PCIE bus cannot be compatible.
Disclosure of Invention
In order to solve the problem that a PCI bus and a PCIE bus cannot be compatible in the current technical scheme, the present application provides a circuit compatible with the PCI and PCIE bus, a card board compatible with the PCI and PCIE bus, a method compatible with the PCI and PCIE bus, and a computing device.
The application provides a circuit of compatible PCI and PCIE bus, includes: the device comprises a clock synchronization control circuit, a switching circuit, a conversion circuit, a power supply circuit, a PCI (peripheral component interconnect) connecting circuit and a PCIE (peripheral component interconnect express) connecting circuit, wherein the PCI connecting circuit and the PCIE connecting circuit are selected for use;
when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information;
when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information.
Optionally, the power supply circuit is connected to an external complete machine through a PCI connection circuit or a PCIE connection circuit, and obtains a power supply from the external complete machine.
Optionally, the switching circuit includes: and switching on the light for switching the channels of the first bus information and the second bus information.
Optionally, the PCI connecting circuit and the PCIE connecting circuit are connected to an external whole device through a gold finger.
Optionally, the gold fingers corresponding to the PCI connecting circuit and the PCIE connecting circuit are disposed on different sides of the card board.
The application also provides a cardboard of compatible PCI and PCIE bus, includes: the card board is provided with the circuit compatible with the PCI and PCIE buses of any one of claims 1-5, and the golden fingers of the PCI connecting circuit and the PCIE connecting circuit are respectively arranged on two side edges of the card board.
The application also provides a method for compatible PCI and PCIE buses, which comprises the following steps:
setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting the PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting the data in the PCIE bus format acquired by the PCIE bus interface.
The present application further provides a computing device, which employs the circuit compatible with the PCI and PCIE buses of the claims above, where the circuit compatible with the PCI and PCIE buses includes: the clock synchronization control circuit, the switching circuit, the conversion circuit, the power supply circuit, the PCI connecting circuit and the PCIE connecting circuit are selected for use;
when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information;
when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information.
Optionally, the power supply circuit is connected to an external complete machine through a PCI connection circuit or a PCIE connection circuit, and obtains a power supply from the external complete machine.
Optionally, the switching circuit includes: and switching on the light for switching the channels of the first bus information and the second bus information.
Compared with the prior art, the application has the advantages that:
the application provides a circuit of compatible PCI and PCIE bus, includes: the device comprises a clock synchronization control circuit, a switching circuit, a conversion circuit, a power supply circuit, a PCI (peripheral component interconnect) connecting circuit and a PCIE (peripheral component interconnect express) connecting circuit, wherein the PCI connecting circuit and the PCIE connecting circuit are selected for use; when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information; when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information. According to the application, the PCI bus connecting circuit and the PCIE bus connecting circuit are designed into one circuit, and output is performed after data format conversion, so that one circuit can be connected with the PCI bus and also can be connected with the PCIE bus, and compatibility of the PCI bus and the PCIE bus is realized.
Drawings
Fig. 1 is a schematic diagram of a circuit compatible with PCI and PCIE buses in the present application.
Fig. 2 is a diagram of a card compatible with PCI and PCIE buses in the present application.
Detailed Description
The following is an example of a specific implementation process provided for explaining the technical solutions to be protected in the present application in detail, but the present application may also be implemented in other ways than those described herein, and a person skilled in the art may implement the present application by using different technical means under the guidance of the idea of the present application, so that the present application is not limited by the following specific embodiments.
The application provides a circuit of compatible PCI and PCIE bus, includes: the device comprises a clock synchronization control circuit, a switching circuit, a conversion circuit, a power supply circuit, a PCI (peripheral component interconnect) connecting circuit and a PCIE (peripheral component interconnect express) connecting circuit, wherein the PCI connecting circuit and the PCIE connecting circuit are selected for use; when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information; when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information. According to the application, the PCI bus connecting circuit and the PCIE bus connecting circuit are designed into one circuit, and output is performed after data format conversion, so that one circuit can be connected with the PCI bus and also can be connected with the PCIE bus, and compatibility of the PCI bus and the PCIE bus is realized.
Fig. 1 is a schematic diagram of a circuit compatible with PCI and PCIE buses in the present application.
Referring to fig. 1, the circuit of the present application includes: the PCI bus interface circuit comprises a PCI connecting circuit 101 and a PCIE connecting circuit 102, wherein the PCI connecting circuit 101 is used for connecting a PCI bus interface of an external complete machine, and the PCIE connecting circuit 102 is used for connecting a PCIE bus interface of the external complete machine.
The PCIE connection circuit 102 and the PCI connection circuit 101 are connected to a power supply circuit 105, the power supply circuit 105 obtains a power supply from an external host through the PCI connection circuit 101 and the PCIE connection circuit 102, and the power supply is processed in the power supply circuit 105 to respectively supply power to the conversion circuit 103, the switching circuit 106, and the clock synchronization control circuit 104.
In this application, the power circuit 105 is connected to an external whole device through the PCI connection circuit 101 or the PCIE connection circuit 102, and obtains a power supply from the external whole device. The PCI link circuit 101 and the PCIE link circuit 102 actually use only one, and therefore the power supply circuit 105 directly transmits the 3.3V auxiliary power supply of the PCI link circuit 101 or the PCIE link circuit 102 to the subsequent stage. The main power supply provided by the PCIE connection circuit 102 is +12V, and the power supply circuit 105 converts the +12V main power supply into a +5V power supply to be connected to the first relay and then to the ground. The main power supply provided by the PCI link 101 is +5V power, which is connected to the second relay and then to ground.
The PCIE link circuit 102 and the PCI link circuit 101 actually use only one end, and therefore, according to the used PCIE link circuit 102 or PCI link circuit 101, the corresponding main power source is respectively used to be transmitted to the subsequent stage circuit.
The auxiliary power supply described herein will be converted to 1.8V power for use by the switching circuit 106, and the main power supply will be provided for use by circuits other than the switching circuit 106.
In this application, when the PCIE connection circuit 102 is used, the switching circuit 106 receives the first bus information and the first clock information of the PCIE circuit by supplying power to the power supply circuit 105, and sends the first clock information to the clock synchronization circuit as the reference clock, and outputs the first bus information as the bus output information.
Specifically, the clock synchronization control circuit 104 includes a clock synchronization chip, and the clock synchronization chip processes the first clock signal transmitted by the PCIE connection circuit 102 to implement clock synchronization of all PCIE interface chips. The clock synchronization control circuit 104 further comprises a crystal oscillator for outputting a second clock signal, which is also transmitted to the switching circuit 106. The switching circuit 106 includes: and switching on the light for switching the channels of the first bus information and the second bus information. The switching circuit 106 is configured to switch the first clock signal and the second clock signal, and when the PCIE connection circuit 102 is used, the first clock signal is switched to.
The first clock signal is referred to as a third clock signal in this application after being processed by the switching circuit 106, and the third clock signal is returned to the clock synchronization controller and processed by the clock synchronization controller to generate a fourth clock signal and a fifth clock signal.
The fourth clock signal will be sent to the next stage functional circuit and the fifth clock signal will be sent to the conversion circuit 103.
The PCIE connection circuit 102 sends the first bus information to the switching circuit 106, and sends the first bus information to the next stage of function circuit after passing through the switching circuit 106.
When the PCI connection circuit 101 is used, the clock synchronization control circuit 104 sends out a second clock signal by the power supply of the power supply circuit 105, the second clock signal is returned to the clock synchronization control circuit 104 as the reference clock output by the selection of the switching circuit 106 and sent to the conversion circuit 103, the conversion circuit 103 receives the second clock information and the second input information of the PCI connection circuit 101 to generate second bus information, and the second bus information is selected by the switching circuit 106 to be output as bus output information.
Specifically, when the PCI connection circuit 101 is used, the second clock information is switched to the third clock information, and the fifth clock information generated from the third clock information is input to the conversion circuit 103.
The conversion circuit 103 receives input information of the PCI connection circuit 101, and generates second service information according to the fifth clock information. The conversion circuit 103 further receives first reset information transmitted by the PCIE connection circuit 102, and the second reset information and the first reset information are processed by and gate logic to generate third reset information.
The input information of the PCI connecting circuit 101 is converted into information in the PCIE bus format through serial-to-parallel conversion, and is transmitted to the switching circuit 106 through the second bus together with the third reset information, which is referred to as second bus information in this application.
The second bus information passes through the switching circuit 106 and then is transmitted to the next stage functional circuit.
Preferably, the PCI connecting circuit 101 and the PCIE connecting circuit 102 are connected to an external whole device through a gold finger. The gold fingers corresponding to the PCI connecting circuit 101 and the PCIE connecting circuit 102 are disposed on different sides of the card board.
The application also provides a cardboard of compatible PCI and PCIE bus, set up the above-mentioned circuit of compatible PCI and PCIE bus on the cardboard, PCI connecting circuit 101 with the golden finger of PCIE connecting circuit 102 sets up respectively at two sides of cardboard.
Fig. 2 is a diagram of a card compatible with PCI and PCIE buses in the present application.
Referring to fig. 2, the card board is provided with two sets of golden fingers respectively located at different sides of the card board, and preferably, the two sets of golden fingers are respectively located at opposite sides of the card board.
The application also provides a method for the compatibility of the PCI and the PCIE buses, and the method is realized by adopting the circuit for the compatibility of the PCI and the PCIE buses.
Specifically, the method comprises the following steps: setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting the PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting the data in the PCIE bus format acquired by the PCIE bus interface.
The specific data transmission and conversion flow of the method for compatible PCI and PCIE buses is consistent with the circuit description of the compatible PCI and PCIE buses, and is not described herein again.
The present application further provides a computing device, where the above-mentioned circuit compatible with the PCI and PCIE buses is adopted by the computing device to implement a bus interface, and the circuit compatible with the PCI and PCIE buses includes: the device comprises a clock synchronization control circuit, a switching circuit 106, a conversion circuit 103, a power supply circuit 105, a PCI connecting circuit 101 and a PCIE connecting circuit 102, wherein the PCI connecting circuit 101 and the PCIE connecting circuit 102 are selected for use.
When the PCIE connection circuit 102 is used, the switching circuit 106 receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit 105, sends the first clock information to the clock synchronization circuit as a reference clock to be output, and outputs the first bus information as bus output information;
when the PCI connection circuit 101 is used, the clock synchronization control circuit 104 sends out a second clock signal by the power supply of the power supply circuit 105, the second clock signal is returned to the clock synchronization control circuit 104 as the reference clock output by the selection of the switching circuit 106 and sent to the conversion circuit 103, the conversion circuit 103 receives the second clock information and the second input information of the PCI connection circuit 101 to generate second bus information, and the second bus information is selected by the switching circuit 106 to be output as bus output information.
Preferably, the power circuit 105 is connected to an external whole device through the PCI connection circuit 101 or the PCIE connection circuit 102, and obtains power from the external whole device.
Preferably, the switching circuit 106 includes: and switching on the light for switching the channels of the first bus information and the second bus information.

Claims (10)

1. A PCI and PCIE bus compatible circuit, comprising: the device comprises a clock synchronization control circuit, a switching circuit, a conversion circuit, a power supply circuit, a PCI (peripheral component interconnect) connecting circuit and a PCIE (peripheral component interconnect express) connecting circuit, wherein the PCI connecting circuit and the PCIE connecting circuit are selected for use;
when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information;
when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information.
2. The circuit of claim 1, wherein the power circuit is connected to an external device via a PCI link circuit or a PCIE link circuit, and obtains power from the external device.
3. The PCI and PCIE bus compatible circuit of claim 1, wherein the switching circuit comprises: and switching on the light for switching the channels of the first bus information and the second bus information.
4. The circuit of claim 1, wherein the PCI link circuit and the PCIE link circuit are connected to an external device through a gold finger.
5. The circuit of claim 4, wherein the gold fingers of the PCI link circuit and the PCIE link circuit respectively correspond to are disposed on different sides of the card board.
6. A card board compatible with PCI and PCIE buses, characterized in that the card board is provided with any one of the PCI and PCIE bus compatible circuits of claims 1-5, and the golden fingers of the PCI connecting circuit and the PCIE connecting circuit are respectively arranged at two side edges of the card board.
7. A method for compatible PCI and PCIE buses is characterized by comprising the following steps:
setting a PCI bus connection interface to be connected with a PCI bus complete machine, or setting a PCIE bus interface to be connected with a PCIE bus complete machine;
if the PCI bus interface is used, converting the PCI bus format data acquired from the PCI bus interface to generate PCIE bus format data and outputting the PCIE bus format data;
and if the PCIE bus interface is used, outputting the data in the PCIE bus format acquired by the PCIE bus interface.
8. A computing device using the PCI and PCIE bus compatible circuit of any one of claims 1-5, wherein the PCI and PCIE bus compatible circuit comprises: the clock synchronization control circuit, the switching circuit, the conversion circuit, the power supply circuit, the PCI connecting circuit and the PCIE connecting circuit are selected for use;
when a PCIE (peripheral component interface express) connecting circuit is used, the switching circuit receives first bus information and first clock information of the PCIE circuit through power supply of the power supply circuit, sends the first clock information to the clock synchronization circuit to serve as a reference clock to be output, and outputs the first bus information serving as bus output information;
when the PCI connecting circuit is used, the clock synchronization control circuit sends out a second clock signal through the power supply of the power supply circuit, the second clock signal is selected by the switching circuit to return to the clock synchronization control circuit for outputting as the reference clock, and the second clock signal is sent to the conversion circuit, the conversion circuit receives the second clock information and second input information of the PCI connecting circuit to generate second bus information, and the second bus information is selected by the switching circuit to be output as bus output information.
9. The computing device of claim 8, wherein the power circuit is coupled to an external overall device via a PCI link circuit or a PCIE link circuit and obtains power from the external overall device.
10. The computing device of claim 8, wherein the switching circuit comprises: and switching on the light for switching the channels of the first bus information and the second bus information.
CN202111421014.7A 2021-11-26 2021-11-26 Circuit compatible with PCI and PCIE buses, card board and computing equipment Active CN114116565B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111421014.7A CN114116565B (en) 2021-11-26 2021-11-26 Circuit compatible with PCI and PCIE buses, card board and computing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111421014.7A CN114116565B (en) 2021-11-26 2021-11-26 Circuit compatible with PCI and PCIE buses, card board and computing equipment

Publications (2)

Publication Number Publication Date
CN114116565A true CN114116565A (en) 2022-03-01
CN114116565B CN114116565B (en) 2024-01-30

Family

ID=80369929

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111421014.7A Active CN114116565B (en) 2021-11-26 2021-11-26 Circuit compatible with PCI and PCIE buses, card board and computing equipment

Country Status (1)

Country Link
CN (1) CN114116565B (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1855213A (en) * 2005-04-29 2006-11-01 鸿富锦精密工业（深圳）有限公司 Interface switching system and method
CN1928803A (en) * 2005-09-09 2007-03-14 北京富瑞菲格电力科技有限公司 Multiple passages selection AD interface card with PCI, PCI-X PCI-E interfaces
CN202267962U (en) * 2011-10-11 2012-06-06 联想(北京)有限公司 Bus interface circuit and electronic device
CN202421950U (en) * 2011-12-16 2012-09-05 北京航天测控技术有限公司 External expanding unit for PCI (Peripheral Component Interconnect) bus board cards
CN105045740A (en) * 2015-05-27 2015-11-11 北京立华莱康平台科技有限公司 Conversion method and circuit for communication interfaces
CN107015928A (en) * 2016-01-27 2017-08-04 广达电脑股份有限公司 To switch the system and method for multiple interfaces and system to switch bus
CN208999998U (en) * 2018-11-22 2019-06-18 北京比特大陆科技有限公司 Data processing equipment
CN209168084U (en) * 2018-10-22 2019-07-26 大族激光科技产业集团股份有限公司 A kind of pinboard and adapting system of multiplex roles
CN209572087U (en) * 2019-04-02 2019-11-01 海能电子(深圳)有限公司 A kind of signal switching apparatus
CN111694779A (en) * 2020-06-18 2020-09-22 京东方科技集团股份有限公司 Interface switching device, communication equipment and interface switching method
CN111934859A (en) * 2020-07-22 2020-11-13 北京三未信安科技发展有限公司 Cipher card communication method, cipher card and computer equipment
CN211981999U (en) * 2020-01-19 2020-11-20 南京优维视光电科技有限公司 Multi-signal format conversion switching device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1855213A (en) * 2005-04-29 2006-11-01 鸿富锦精密工业（深圳）有限公司 Interface switching system and method
CN1928803A (en) * 2005-09-09 2007-03-14 北京富瑞菲格电力科技有限公司 Multiple passages selection AD interface card with PCI, PCI-X PCI-E interfaces
CN202267962U (en) * 2011-10-11 2012-06-06 联想(北京)有限公司 Bus interface circuit and electronic device
CN202421950U (en) * 2011-12-16 2012-09-05 北京航天测控技术有限公司 External expanding unit for PCI (Peripheral Component Interconnect) bus board cards
CN105045740A (en) * 2015-05-27 2015-11-11 北京立华莱康平台科技有限公司 Conversion method and circuit for communication interfaces
CN107015928A (en) * 2016-01-27 2017-08-04 广达电脑股份有限公司 To switch the system and method for multiple interfaces and system to switch bus
CN209168084U (en) * 2018-10-22 2019-07-26 大族激光科技产业集团股份有限公司 A kind of pinboard and adapting system of multiplex roles
CN208999998U (en) * 2018-11-22 2019-06-18 北京比特大陆科技有限公司 Data processing equipment
CN209572087U (en) * 2019-04-02 2019-11-01 海能电子(深圳)有限公司 A kind of signal switching apparatus
CN211981999U (en) * 2020-01-19 2020-11-20 南京优维视光电科技有限公司 Multi-signal format conversion switching device
CN111694779A (en) * 2020-06-18 2020-09-22 京东方科技集团股份有限公司 Interface switching device, communication equipment and interface switching method
CN111934859A (en) * 2020-07-22 2020-11-13 北京三未信安科技发展有限公司 Cipher card communication method, cipher card and computer equipment

Also Published As

Publication number Publication date
CN114116565B (en) 2024-01-30

Similar Documents

Publication Publication Date Title
CN100468378C (en) SPI apparatus telecommunication circuit
CN108255755B (en) PCIE general multifunctional communication interface module based on FPGA
US20070067539A1 (en) Enhanced CCID circuits and systems utilizing USB and PCI functions
CN110968352B (en) Reset system and server system of PCIE equipment
CN112597097B (en) Communication system based on ADC data acquisition card, application method and medium thereof
CN212135411U (en) IO module and OCP keysets
CN112269123A (en) Universal configurable chip test circuit
US7590146B2 (en) Information processing unit
US9665526B2 (en) Implementing IO expansion cards
CN110399328B (en) Control method and device for board-mounted graphics processor
CN110362058A (en) The system tested for multiple interfaces
US5644734A (en) Method and apparatus for multiplexing bus connector signals with sideband signals
CN114116565B (en) Circuit compatible with PCI and PCIE buses, card board and computing equipment
CN117097614A (en) Storage system and plug-in card working mode switching device thereof
CN114020669A (en) I2C link system and server based on CPLD
CN110362433A (en) The system for being able to carry out multiplex roles test
US20040205283A1 (en) Interface module
US20060095645A1 (en) Multi-function chipset and related method
US8819324B2 (en) Computer system with bridge
CN104978294A (en) Compatible device of serial peripheral interface, serial peripheral interface and host device
CN106844113B (en) Server fault recovery system and method adopting redundant PCH
CN105224497A (en) The extendible treating apparatus of serial line interface and method
CN216351887U (en) Multichannel data acquisition system
CN216310777U (en) Depth computation processor board card and interconnection system for depth computation processor board cards
CN115202257B (en) LPC bus protocol conversion and equipment parallel control device and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant