CN210129219U

CN210129219U - Multi-functional USB Type-C interface circuit of FPGA accelerator card

Info

Publication number: CN210129219U
Application number: CN201921288953.7U
Authority: CN
Inventors: 张晶威; 韩大峰; 刘丹
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-08-09
Filing date: 2019-08-09
Publication date: 2020-03-06
Anticipated expiration: 2029-08-09

Abstract

The embodiment of the utility model discloses multi-functional USBType-C interface circuit of FPGA accelerator card is based on USB2.0PHY chips and the multi-functional interface conversion chip of USB to, including USBType-C interface, USBMUX switch module and power module, the USB2.0 signal and the USB3.0 signal input of USBType-C interface extremely USB MUX switch module input, USB MUX switch module output is connected USB2.0PHY chips with the multi-functional interface conversion chip of USB to, power module connects USB MUX switch module with the multi-functional interface conversion chip of USBto. The utility model discloses maintain USB communication interface and USB with the heterogeneous calculation accelerator card of FPGA and maintain the interface and merge into a USBType-C interface, draw forth the front panel with Type-C interface on to calculate accelerator card 5V power domain and outside HOST and supply with 5V power domain and cut apart, not only solved the limited problem that can not maintain USB communication interface and USB with USB in front panel space and all draw forth, still solved the incompatible problem in the unified back power domain of two kinds of interfaces.

Description

Multi-functional USB Type-C interface circuit of FPGA accelerator card

Technical Field

The utility model relates to a server technical field, concretely relates to multi-functional USBType-C interface circuit of FPGA accelerator card.

Background

The FPGA heterogeneous computing accelerator card is used as a computing unit of a server and is realized in a PCIe standard card insertion mode, and a front panel of a card mainly has two specifications of full height (4.376inch, namely 111.15mm) and half height (2.731inch, namely 68.9 mm). In a limited board card panel size, the spatial position of the front panel is mostly occupied by the network communication interface, for example: and optical module interfaces such as RJ45 (standard ethernet interface), SFP, QSFP28 and the like.

Generally, a front panel of an FPGA heterogeneous computing accelerator card includes a USB interface besides a network communication interface, and the USB interface has two application scenarios.

The USB universal communication function interface is applied, the application scene is the application of a common USB interface or a USB OTG (On the go) interface, and the OTG interface, namely a heterogeneous computing accelerator card of the FPGA, can be used as a Host computer and can also be used as a slave device. If the computing accelerator card is applied to edge computing, the importance of USB applications is higher.

And the other is USB maintenance function interface application, wherein the application scene is a debugging application interface aiming at the FPGA and/or other embedded microcontrollers on the calculation accelerator card and is also a firmware downloading interface. The heterogeneous computing accelerator card comprises programmable devices such as an FPGA and/or an embedded microcontroller, and meanwhile, during debugging, printing information of firmware and software in the running process of the programmable devices may need to be checked.

As shown in fig. 1, USB interfaces in different application scenarios mostly adopt interface forms with separate functions, the interface types are not uniform, and the USB interfaces are in two forms, namely on-board interfaces and external interfaces, and the functions are relatively independent. The front panel of the accelerator card adopts a USBType-B type interface for the maintenance function of the accelerator card, for example, a JTAG interface signal path from a USB interface on the accelerator card to the FPGA is used for programming firmware, a UART interface signal path from the USB interface on the accelerator card to the FPGA is used as a debugging printing interface, and the debugging printing interface outputs printing information of system operation. However, in general, since the space of the front panel of the board card is limited, the interface for the UART debugging and printing is not arranged on the front panel of the board card but arranged on the board card, so that the case needs to be opened during debugging, a USB to UART conversion circuit debugging tool needs to be externally connected, and the debugging tool needs to prepare for driving software before the calculation acceleration card is powered on. If the front panel of the board card has no redundant space, the JTAG interface for programming the firmware is also arranged on the board card, and an external USB to JTAG conversion circuit debugging tool is also required when the firmware is programmed.

If USB communication requirements exist, a USB Type-A interface is independently added on a front panel of the accelerator card for the communication function of the accelerator card; if the USB communication interface is disposed inside the board, it cannot be used as an external communication interface, and is inconvenient to apply.

In the current application, most USB interfaces adopt an interface form with discrete functions, the interface types are not uniform and are limited by the space limitation of a front panel of a PCIe standard card, most interfaces cannot be led out from the front panel, and inconvenience is brought to system debugging and/or system upgrading in centralized deployment.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides an embodiment provides a multi-functional USBType-C interface circuit of FPGA accelerating card, USB communication interface and USB maintain the interface and merge into a USBType-C interface on the accelerating card with the heterogeneous calculation of FPGA, and draw forth USBType-C interface on the front panel, and supply with 5V power domain to cut apart with outside HOST to calculating accelerating card 5V power domain, the limited problem that can not maintain USB communication interface and USB and draw forth all has not only been solved in the front panel space, the incompatible problem in back power domain has still been solved to two kinds of interfaces unification.

The embodiment of the utility model discloses following technical scheme:

the utility model provides a multi-functional USBType-C interface circuit of FPGA accelerator card, based on USB2.0PHY chips and the multi-functional interface conversion chip of USB to, including USBType-C interface, USB MUX switch module and power module, the USB2.0 signal and the USB3.0 signal input of USBType-C interface extremely USB MUX switch module input, USB MUX switch module output is connected the USB2.0PHY chips with the multi-functional interface conversion chip of USB to, FPGA's USB2.0 signal pin is connected to the USB2.0PHY chip, power module connects USB MUX switch module with the multi-functional interface conversion chip of USB to.

Further, USB MUX switch module includes USB MUX switch and function selection switch, function selection switch connects the USB MUX switch, the USB2.0 signal connection of USB MUX switch output the USB2.0PHY chip with USB to multi-functional interface conversion chip, the USB3.0 signal of USB MUX switch module output is direct to be connected FPGA's USB3.0 signal pin through Serdes.

Furthermore, the USB to multifunctional interface conversion chip converts the USB interface into a plurality of JTAG interfaces and a plurality of UART debugging serial ports, the JTAG interfaces are connected with JTAG signals of the FPGA, and the UART debugging serial ports are connected with UART signals of the FPGA.

Furthermore, the JTAG interface is connected with a plurality of pieces of JTAG equipment through a standard JTAG chain.

Further, the power module comprises a power domain selection module and a plurality of power chips, and the power domain selection module is connected with the plurality of power chips.

Furthermore, the power domain selection module comprises a dial switch SW, a resistor R and an NMOS, one end of the dial switch SW is grounded, the other end of the dial switch SW is connected with a G pole of the NMOS and one end of the resistor R, the G pole of the NMOS is connected with an enabling end of the power chip, the other end of the resistor R and a D pole of the NMOS are connected with a 5V calculation accelerator card, and the S pole of the NMOS is connected with an external HOST to supply 5V and an input end of the power chip.

Further, the USB Type-C interface is arranged on a front panel of the board card.

The effects provided in the contents of the present invention are only the effects of the embodiments, not all the effects of the present invention, and one of the above technical solutions has the following advantages or advantageous effects:

the utility model discloses multi-functional USBType-C interface circuit of FPGA accelerator card combines USB communication interface and USB maintenance interface on the heterogeneous calculation accelerator card of FPGA into a USBType-C interface, arranges the interface in the front panel space, utilizes USBType-C interface small, supports the mechanical structure advantage of positive and negative plug-in operation, practices thrift limited PCIe standard card front panel space; the circuit integrates USB communication interface application and maintenance interface application in a signal circuit physical layer, realizes the unification of USB interface requirements on the FPGA heterogeneous computing accelerator card, and is convenient for a user to use the USB interface for maintenance or communication.

The utility model discloses the multi-functional USB Type-C interface circuit of FPGA accelerator card will calculate accelerator card 5V power domain and outside HOST and supply with 5V power domain and cut apart, when calculating accelerator card and being in USB communication interface application, provide USB power supply, USB power is output state this moment; when the calculation accelerator card is applied to the USB maintenance interface, an external Host (Host) supplies power to a local circuit through a USB cable, the local circuit completes initialization preparation before the calculation accelerator card is powered on, and the power domain division technology solves the problem that the two interfaces are unified and then power domains are incompatible.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a block diagram of a conventional circuit structure according to the present invention;

FIG. 2 is a block diagram of the multifunctional USB Type-C interface circuit according to the embodiment of the present invention;

FIG. 3 is a block diagram of a circuit structure of a standard JTAG chain connecting multiple JTAG devices according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a power module according to an embodiment of the present invention;

fig. 5 is a block diagram of a power domain structure applied to the USB communication interface according to an embodiment of the present invention;

fig. 6 is a block diagram of a power domain structure applied to a USB maintenance interface according to an embodiment of the present invention;

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is explained in detail by the following embodiments in combination with the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and processes are omitted so as to not unnecessarily limit the invention.

The embodiment of the utility model provides a circuit, maintain the interface with USB communication interface and USB on the heterogeneous calculation accelerator card of FPGA and merge into a USBType-C interface, draw forth the USBType-C interface on the front panel to supply with 5V power domain to cut apart with outside HOST to calculation accelerator card 5V power domain, realized that USB communication interface uses and USB maintains the unification that the interface was used.

As shown in FIG. 2, the circuit is based on an USB2.0PHY chip and a USB to multifunctional interface conversion chip, and comprises a USBType-C interface, a USBMUX switch module and a power supply module.

The USB Type-C interface (called Type-C for short) is one of USB hardware interface specifications, and has smaller volume (8.3 mm in length and 2.6mm in height) in terms of mechanical appearance and usability, compared with Type A and Type B, the volume of Type-C is about 1/4 of the two types, and the Type-C supports double-sided insertion (called 'positive and negative insertion' in common).

The USB MUX switch module comprises a USB MUX switch and a function selection switch, and the USB MUX switch is connected with the function selection switch.

USB2.0 and USB3.0 signal input to USB MUX switch input end that USB Type-C interface inserts, USB MUX switch module output divide into USB communication interface application signal flow direction and USB and maintain interface application signal flow direction.

The utility model discloses a USB MUX switch be American texas instrument TI product: the TUSB8041a, TUSB8042, and TUSB8044 chips all support 4 USB2.0+3.0 signals, and can all implement the functions of the present embodiment, and other USB MUX switches whose outputs include two or more sets of ports and support USB2.0+3.0 signals can also be used.

The function selection switch is connected with the USB communication interface application or the USB maintenance interface application in a mode of manually selecting a signal path, and the function selection switch selects a dial switch or other out-of-band control modes, so that the function selection switch is suitable for general field debugging, and if the batch and scale deployment is needed, a program is matched to control the USB MUX switch, and the signal path is automatically selected to be realized.

The USB communication interface application signal flow direction comprises an USB2.0PHY chip (USB2.0PHY chip, which is a fixed interface of FPGA toUSB2.0 and is a conversion chip from a protocol layer to a physical layer), the USB communication interface application signal flow direction of the USB MUX switch outputs a USB2.0 signal and a USB3.0 signal, the USB2.0 signal is connected with a USB2.0 signal pin of the FPGA through a USB2.0PHY chip, and the USB2.0 communication from USB Type-C to FPGA is realized through the path; USB3.0 signal directly connects FPGA's USB3.0 signal pin through Serdes, and USB Type-C is realized to FPGA's USB3.0 communication to this passageway, and USB communication interface application signal flow direction has realized the function that USB communication interface used.

The USB maintenance interface application signal flow direction comprises a USB to multifunctional interface conversion chip, the USB maintenance interface application signal flow direction of a USB MUX switch outputs a USB2.0 signal, the USB2.0 signal is connected with the USB to multifunctional interface conversion chip (FT 4232H chip of FTDIchip company), the USB to multifunctional interface conversion chip converts the USB interface into a plurality of JTAG interfaces and a plurality of UART debugging serial ports, the JTAG interfaces are connected with JTAG signals of the FPGA, the UART debugging serial ports are connected with UART signals of the FPGA, and the USB maintenance interface application signal flow direction realizes the function of the USB maintenance interface application.

The JTAG interface is connected with the FPGA and can also be connected with a plurality of pieces of JTAG equipment through a standard JTAG chain.

As shown in fig. 3, in this embodiment, the JTAG interface is connected to multiple FPGAs through a standard JTAG chain, and a JTAG link is planned according to 4 or 8 pieces, that is, a single board is used as a JTAG chain unit to manage individual links of devices in the system. The JTAG chain can also be connected with a plurality of FPGAs and a plurality of CPLDs, and the CPLDs need to be consistent with the FPGA manufacturers.

In the physical layer, a plurality of interfaces output by the USB to multifunctional interface conversion chip are time-division multiplexed; in the software driving interface, an upper computer (such as a debugging HOST, HOST and the like) is converted into a plurality of UART debugging serial ports through USB, the ports of the UART debugging serial ports are numbered and distinguished, and the port of the UART debugging serial port is selected through the upper computer interface, so that the communication from the USB to a certain UART debugging serial port device is realized (the embodiment can realize time division multiplexing, and the operations of debugging and printing state information do not need strong real-time performance, and even if two pieces of interconnected state are debugged, only some debugging marks and signs are printed, so that the USB type universal serial bus interface is a simple low-speed interface).

The circuit embodiment divides a 5V power domain of the calculation accelerator card and a 5V power domain supplied by an external HOST, and when the calculation accelerator card is applied to a USB communication interface, the calculation accelerator card provides a USB 5V power supply; when the calculation accelerator card is applied to the USB maintenance interface, an external Host (Host) supplies power to the USB MUX switch circuit and a local circuit of the USB to multifunctional interface conversion chip through a USB cable, and the local circuit completes initialization preparation before the calculation accelerator card is powered on.

The power module is used for supplying power to the USB MUX switch and the USB to multifunctional interface conversion chip, the power module comprises a power domain selection module and a plurality of power chips, and the power domain selection module is used for controlling the plurality of power chips.

As shown in fig. 4, the power domain selecting module includes a dial switch SW, a resistor R and an NMOS, one end of the dial switch SW is grounded, the other end of the dial switch SW is connected to the G pole of the NMOS and one end of the resistor R, the G pole of the NMOS is connected to the enabling end of the power chip, the other end of the resistor R and the D pole of the NMOS are connected to the computing accelerator card 5V, and the S pole of the NMOS is connected to the external HOST supply 5V and the input end of the power chip.

The power module uses NMOS transistor as switch between 5V power domain of accelerator card and 5V power domain of external HOST supply, and the logic of the power module is:

when the manual dial switch SW is in an off state, the 5V power supply of the calculation accelerator card is switched on, the NMOS is switched on, the external HOST obtains power supply from the 5V power supply domain of the calculation accelerator card, the board card supplies power to the external USB equipment, the high level of the enabling end of the power supply chip is invalid at the moment, and the output end of the power supply chip does not output power;

when the dial switch SW is manually adjusted to be in a closed state, the dial switch SW is closed and conducted to GND, the external HOST supplies 5V to be connected into the calculation accelerator card in advance, the NMOS is disconnected at the moment, the low level of the output end of the power supply chip is effective, the output end of the power supply chip outputs power, and the external HOST supplies 5V to supply power to the maintenance function local circuit for initialization.

The circuit needs a plurality of power chips to supply power to the USB MUX switch and the USB to multifunctional interface conversion chip for working, and each power chip outputs voltages with different amplitudes, such as 1.8V, 3.3V and the like.

The working principle of the circuit is as follows:

by utilizing a function selection switch of the calculation accelerator card, selecting a USB MUX switch to apply signal flow direction for a USB communication interface, when a dial switch SW is in an off state, the calculation accelerator card is in a USB communication interface application mode (at the moment, the calculation accelerator card is a Host, and the external device is a Slave), a power supply path of the calculation accelerator card to external USB equipment is opened, a power domain state of a board card is in a non-debugging state, the board card is taken over by a 5V power supply of the calculation accelerator card, and the board card supplies power to the external USB interface, so that the power domain of the whole board is unified, namely a circuit formed by a USB MUX switch module, a power domain selection module, an USB2.0PHY chip and a USB multifunctional interface conversion chip in a thick frame shown in FIG. 5 is a 5V power domain of the calculation accelerator card;

the method comprises the steps that a function selection switch of a calculation accelerator card is utilized to select a USB MUX switch to apply signal flow direction to a USB maintenance interface, when a dial switch SW is in a closed state, the calculation accelerator card is in a USB maintenance interface application mode (at the moment, the calculation accelerator card is a Slave, an external device is a Host), an external HOST supplies 5V to be connected to a power supply module, the power supply module outputs power to the USB MUX switch and a USB to multifunctional interface conversion chip for use, and power-on preparation is made before a board card works; the division of the partial power domain realizes the communication of a USB cable, namely the power supply of the USB maintenance interface application circuit, and also realizes the integration of hardware power supply and USB drive identification of the maintenance signal circuit, for example, a circuit formed by a USB MUX switch module, a power module and a USBto multifunctional interface conversion chip in an irregular thick frame shown in FIG. 6, namely, an external HOST supply 5V power domain.

The above description is only a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations are also considered as the protection scope of the present invention.

Claims

1. The utility model provides a multi-functional USB Type-C interface circuit of FPGA accelerator card, is based on USB2.0PHY chip and the multi-functional interface conversion chip of USB to, its characterized in that, including USB Type-C interface, USB MUX switch module and power module, USB2.0 signal and the USB3.0 signal input of USBType-C interface extremely USB MUX switch module input, USB MUX switch module output is connected USB2.0PHY chip with the multi-functional interface conversion chip of USB to, the USB2.0 signal pin of FPGA is connected to the USB2.0PHY chip, power module connects USB MUX switch module with the multi-functional interface conversion chip of USBto.

2. The multifunctional USB Type-C interface circuit of the FPGA accelerator card as claimed in claim 1, wherein the USB MUX switch module comprises a USB MUX switch and a function selection switch, the function selection switch is connected to the USB MUX switch, the USB2.0 signal at the output end of the USB MUX switch is connected to the USB2.0PHY chip and the USB to multifunctional interface conversion chip, and the USB3.0 signal at the output end of the USB MUX switch module is directly connected to the USB3.0 signal pin of the FPGA through Serdes.

3. The multifunctional USB Type-C interface circuit of the FPGA accelerator card according to claim 1, wherein the USB to multifunctional interface conversion chip converts the USB interface into a plurality of JTAG interfaces and a plurality of UART debugging serial ports, the JTAG interfaces are connected with JTAG signals of the FPGA, and the UART debugging serial ports are connected with UART signals of the FPGA.

4. The multifunctional USB Type-C interface circuit of the FPGA accelerator card of claim 3, wherein the JTAG interface is connected to a plurality of JTAG devices through a standard JTAG chain.

5. The multifunctional USB Type-C interface circuit of the FPGA accelerator card as recited in claim 1, wherein the power module comprises a power domain selection module and a plurality of power chips, and the power domain selection module is connected with the plurality of power chips.

6. The multifunctional USB Type-C interface circuit of the FPGA accelerator card as recited in claim 5, wherein the power domain selection module comprises a toggle switch SW, a resistor R and an NMOS, one end of the toggle switch SW is grounded, the other end of the toggle switch SW is connected with a G pole of the NMOS and one end of the resistor R, the G pole of the NMOS is connected with an enabling end of the power chip, the other end of the resistor R and a D pole of the NMOS are connected with a 5V computing accelerator card, and an S pole of the NMOS is connected with an external HOST supply 5V and an input end of the power chip.

7. The multifunctional USBType-C interface circuit of the FPGA accelerator card of claim 1, wherein the USBType-C interface is disposed on a front panel of the board card.