CN214480671U - One-to-many communication circuit based on SPI communication - Google Patents

One-to-many communication circuit based on SPI communication Download PDF

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Publication number
CN214480671U
CN214480671U CN202023338394.1U CN202023338394U CN214480671U CN 214480671 U CN214480671 U CN 214480671U CN 202023338394 U CN202023338394 U CN 202023338394U CN 214480671 U CN214480671 U CN 214480671U
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module
spi
slave
chip selection
chip
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CN202023338394.1U
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Inventor
何纯
韩国俭
张美生
梁栋
李怀新
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Qingdao Topscomm Communication Co Ltd
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Qingdao Topscomm Communication Co Ltd
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Abstract

The utility model discloses a one-to-many communication circuit based on SPI communication, including master control MCU, multichannel from module (or from chip), simulation electronic switch module, drive module, chip selection signal generation module. The master control MCU controls the chip selection signal generation module to generate a specific slave module chip selection signal so as to enable the corresponding slave module SPI to communicate; the master control MCU controls the analog electronic switch module to switch the communication link to the corresponding slave module; and the SPI master-slave communication function is realized. The driving capability is improved through the driving module, the multi-channel analog switch is switched, chip selection control of multiple slave modules on a single channel is achieved, occupation of resources of a master control chip is reduced, the communication speed is improved, and the number of the slave modules capable of being accessed is increased.

Description

One-to-many communication circuit based on SPI communication
Technical Field
The utility model relates to a SPI communication technical field, in particular to communication circuit of a pair of many of SPI communication.
Background
SPI, Serial peripheral Interface, is a communication Interface technology introduced by Motorola, inc. SPI is a high-speed, full-duplex, synchronous serial communication bus, a ring bus structure, and occupies only four wires (MISO, MOSI, CS, SCK) on the pins of the chip. The method is mainly applied to EEPROM, FLASH, real-time clock, AD converter, and also applied between digital signal processor and digital signal decoder.
The SPI is composed of a main device and one or more slave devices, the main device starts synchronous communication with the slave devices so as to complete data exchange, and the whole communication process is controlled by the SPI main device. The SPI interface is composed of four signals, i.e., MISO (serial data input), MOSI (serial data output), SCK (serial shift clock), and CS (slave enable signal). Where CS denotes a slave enable signal, controlled by the master. When there are multiple slave devices, each slave device has a chip select pin connected to the host device, and when the host device communicates with a certain slave device, the level of the chip select pin corresponding to the slave device needs to be pulled down or pulled up.
Currently, the number of slave devices that an SPI master device can usually mount is no more than eight due to the limitation of chip IO drive capability. In some complex multi-node systems, the SPI of the master chip cannot provide sufficient driving capability, which affects the number of slave nodes that are accessed, and meanwhile, high-speed communication cannot be realized under the condition of multiple slave devices, often indicating that the communication rate cannot be increased or communication fails.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a one-to-many communication circuit based on SPI communication. The circuit is simple and practical, the number of the SPI slave devices can be increased, the number of the IO interfaces occupied by the master control MCU is reduced, and the bus communication speed is increased.
The utility model provides a to many communication circuit based on SPI, including master control MCU, multichannel slave module or from the chip, simulation electronic switch module, drive module, chip selection signal generation module. The connection relationship is as follows: SCK, MOSI and MISO pins of the main control MCU chip are respectively connected with corresponding input ends of the driving module; the SCK, MOSI and MISO output ends of the driving module are respectively connected with the analog switch moduleAn input terminal of (1); SCK of analog switch0…m、MOSI0…mAnd MISO0…mThe pins are respectively connected to SCK, MOSI and MISO inputs of the slave modules; the control IO pins of the MCU chip are respectively connected to the chip selection generation module and the CS of the chip selection generation module0…nThe functional pins are respectively connected to the slave modules. Firstly, a chip selection signal generation module is controlled by a master control MCU (microprogrammed control unit) to generate a specific slave module chip selection signal so as to enable the corresponding slave module SPI (serial peripheral interface) to communicate; the master control MCU controls the analog electronic switch module to switch the communication link to the corresponding slave module; and then the master control MCU generates a communication signal of the SPI, and the SPI is driven by the driving module. And the SPI master-slave communication function is realized.
The driving module is used for providing the driving capability of the SPI communication port, and the driving module is a driving circuit built by a special chip or a triode. And the analog electronic switch module is used for switching and controlling the signal path according to the control instruction and selecting the SCK, the MOSI and the MISO of the SPI interface to the slave module to be accessed to communicate. The chip selection signal generation module can receive a master control MCU signal through a serial or parallel interface, generate a chip selection signal pointing to a specific slave module and enable the slave module to realize SPI communication; the chip selection signal generation module is a single decoder chip, or a combination of a plurality of decoder chips, or a plurality of channels of chip selection signals generated by the main control MCU, so as to drive the corresponding slave modules.
The utility model has the advantages of: the occupation of the main control chip resources is reduced, the communication speed is improved, and the number of the accessible slave modules is increased.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention without limiting the invention. In the drawings:
fig. 1 is a block diagram for implementing a one-to-many communication circuit based on SPI communication according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the specific forms herein described are to be considered as illustrative and not restrictive in character.
The utility model discloses a communication system and implementation method provide a circuit of a to many communications based on SPI, including main control MCU, multichannel slave module (or from the chip), analog electronic switch module, drive module, chip selection signal generation module. The MISO, MOSI and CSK three-way signals of the SPI module of the main control MCU are connected to the driving module, and I/O port current driving control is carried out on the three-way signals, so that the driving capability is improved. Then, the signals of the MISO, MOSI and CSK of the SPI module of the main control MCU after being driven are synchronously selected to be independent channels, namely MISOm, MOSIm and CSKm are simultaneously accessed, wherein m is the same channel or represents the same channel, and the SPI after being expanded is divided into each channel to be connected according to the figure 1.
The chip selection signal generation module can be a single decoder chip or a combination of a plurality of decoder chips, and can also be a simple auxiliary MCU to generate a plurality of channels of chip selection signals for driving the corresponding slave modules. The module generates a CS corresponding to a certain slave module on a corresponding certain channel after the switching of the multi-channel analog switch, namely, the CS is accessed to the channel connected by the MISOm, MOSIm and CSKm at the moment, and the corresponding CSn, n represents the serial number of the corresponding slave module. At this time, the master control MCU can perform SPI high-speed communication under the determined connection and chip selection conditions.

Claims (4)

1. A one-to-many communication circuit based on SPI communication, characterized by that includes:
the system comprises a main control MCU, a multi-channel slave module, an analog electronic switch module, a driving module and a chip selection signal generating module;
the connection relationship is as follows: SCK, MOSI and MISO pins of the main control MCU chip are respectively connected with corresponding input ends of the driving module; the SCK, MOSI and MISO output ends of the driving module are respectively connected with the input end of the analog switch module; SCK of analog switch0…m、MOSI0…mAnd MISO0…mThe pins are respectively connected toSCK, MOSI, and MISO inputs of the slave module; the control IO pins of the MCU chip are respectively connected to the chip selection generation module and the CS of the chip selection generation module0…nThe functional pins are respectively connected to the slave modules;
the control chip selection signal generation module generates a specific slave module chip selection signal and enables the corresponding slave module SPI to communicate; the master control MCU controls the analog electronic switch module to switch the communication link to the corresponding slave module, so that the SPI master-slave communication function is realized.
2. The SPI communication based one-to-many communication circuit according to claim 1, wherein:
the driving module is used for providing the driving capability of the SPI communication port, and the driving module is a driving circuit built by a special chip or a triode.
3. The SPI communication based one-to-many communication circuit according to claim 1, wherein:
and the analog electronic switch module is used for switching and controlling the signal path according to the control instruction and selecting the SCK, the MOSI and the MISO of the SPI interface to the slave module to be accessed to communicate.
4. The SPI communication based one-to-many communication circuit according to claim 1, wherein:
the chip selection signal generation module can receive a master control MCU signal through a serial or parallel interface, generate a chip selection signal pointing to a specific slave module and enable the slave module to realize SPI communication; the chip selection signal generation module is a single decoder chip, or a combination of a plurality of decoder chips, or a plurality of channels of chip selection signals generated by the main control MCU, so as to drive the corresponding slave modules.
CN202023338394.1U 2020-12-30 2020-12-30 One-to-many communication circuit based on SPI communication Active CN214480671U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202023338394.1U CN214480671U (en) 2020-12-30 2020-12-30 One-to-many communication circuit based on SPI communication

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Application Number Priority Date Filing Date Title
CN202023338394.1U CN214480671U (en) 2020-12-30 2020-12-30 One-to-many communication circuit based on SPI communication

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CN214480671U true CN214480671U (en) 2021-10-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114780476A (en) * 2022-04-15 2022-07-22 北京经纬恒润科技股份有限公司 SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114780476A (en) * 2022-04-15 2022-07-22 北京经纬恒润科技股份有限公司 SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves
CN114780476B (en) * 2022-04-15 2024-03-22 北京经纬恒润科技股份有限公司 SPI time-sharing multiplexing circuit supporting multiple masters and multiple slaves

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