CN108107409A - A kind of intermediate-freuqncy signal source and its signal generating method of MIMO radar target seeker - Google Patents
A kind of intermediate-freuqncy signal source and its signal generating method of MIMO radar target seeker Download PDFInfo
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- CN108107409A CN108107409A CN201711217470.3A CN201711217470A CN108107409A CN 108107409 A CN108107409 A CN 108107409A CN 201711217470 A CN201711217470 A CN 201711217470A CN 108107409 A CN108107409 A CN 108107409A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
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- Radar, Positioning & Navigation (AREA)
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- Radar Systems Or Details Thereof (AREA)
Abstract
A kind of intermediate-freuqncy signal source and its signal generating method of MIMO radar target seeker, FPGA control circuit, for generating timing control signal and noise parameter, and DDS groups circuit is controlled to generate orthogonal wideband mid-frequency noise signal, DDS groups circuit is electrically connected FPGA control circuit, for generating orthogonal wideband mid-frequency noise signal under the control of FPGA control circuit, clock distribution circuit is electrically connected FPGA control circuit and DDS group circuits, DDS group circuits are sent to for generating synchronizing clock signals under the control of FPGA control circuit, storage circuit is electrically connected FPGA control circuit, for storing the much noise parameter of FPGA control circuit generation.The present invention takes full advantage of fpga chip flexible in programming and special DDS chip frequencies feature with high accuracy, generated MIMO radar intermediate frequency quadrature signal frequency resolution ratio is 0.8149Hz, intermediate-frequency bandwidth reaches as high as 1350MHz, than being higher by an order of magnitude by the way of FPGA and high speed D/A structure.
Description
Technical field
The present invention relates to MIMO radar target seeker orthogonal waveforms to generate field more particularly to a kind of MIMO radar target seeker
Intermediate-freuqncy signal source and its signal generating method.
Background technology
Compared with conventional phased array target seeker, MIMO guidings neck major technique advantage is mainly reflected in following side
Face：Anti-stealth capability is strong, angle measurement accuracy is improved in aperture synthesis, strong etc. with wider irradiation wave beam, anti-clutter ability.Quadrature wave
Design, generation and the optimization of shape are the important research directions of MIMO radar target seeker, and China is carrying out MIMO radar skill at present
The theoretical research and test platform research that art is applied on target seeker, in order to realize the MIMO radar of the orthogonal agile of waveform transmitting letter
Number, the design that the intermediate frequency quadrature waveform of MIMO radar target seeker generates seems very necessary.
There are mainly two types of modes for the generation of present radar signal：Direct analog frequency synthesizes and uses FPGA and high speed
DA structures.
The principle of direct analog frequency synthesis be use one or more reference signals are carried out frequency multiplication, frequency dividing, mixing and
Analog switch operation generates required frequency.This mode there are the fast stability of frequency transformation speed it is high the advantages of, but because
The shortcomings that its debugging is not easy, spurious reduction is difficult, system complex is of high cost, present which seldom makes in radar engineering
With.
Principle by the way of FPGA and high speed D/A structure is one soft core of DDS of generation inside FPGA, by a high speed
DA generates analog signal output.It is flexible that this method has the characteristics that waveform generates, but this mode will also add mould after DA
It is all to be operated in analog portion to intend modulator and frequency mixer, this partial circuit, is had in terms of I/Q phase alignments and noise suppressed
Certain difficulty.In addition, this mode is due to being the generation soft cores of DDS inside FPGA, system clock and memory capacity all can be by
To the limitation of fpga chip, centre frequency is generally it is difficult to accomplish very high.
A kind of design for the intermediate-freuqncy signal source for being more suitable for MIMO radar target seeker is needed to meet its big bandwidth, orthogonal waveforms
Requirement.
The content of the invention
The present invention provides a kind of intermediate-freuqncy signal source and its signal generating method of MIMO radar target seeker, takes full advantage of
Fpga chip flexible in programming and special DDS chip frequencies feature with high accuracy, generated MIMO radar intermediate frequency quadrature signal frequency
Rate resolution ratio is 0.8149Hz, and intermediate-frequency bandwidth reaches as high as 1350MHz, than being higher by one by the way of FPGA and high speed D/A structure
A order of magnitude.
In order to achieve the above object, the present invention provides a kind of intermediate-freuqncy signal source of MIMO radar target seeker, comprising：
FPGA control circuit for generating timing control signal and noise parameter, and controls DDS groups circuit to generate orthogonal width
Band mid-frequency noise signal；
DDS group circuits are electrically connected FPGA control circuit, for generating orthogonal width under the control of FPGA control circuit
Band mid-frequency noise signal；
Clock distribution circuit is electrically connected FPGA control circuit and DDS group circuits, in the control of FPGA control circuit
The lower generation synchronizing clock signals of system are sent to DDS group circuits；
Storage circuit is electrically connected FPGA control circuit, for storing the much noise ginseng of FPGA control circuit generation
Number.
The DDS group circuits include：Multiple DDS modules, each DDS module connect FPGA control circuit and clock respectively
Distributor circuit, each DDS module generate the signal of a passage respectively.
The DDS module further includes：
DDS chips are electrically connected FPGA control circuit and clock distribution circuit, in the control of FPGA control circuit
Lower generation orthogonal wideband mid-frequency noise signal；
Transformer, is electrically connected DDS chips, and the intermediate-freuqncy signal for DDS chips to be generated is converted to electricity by current mode
Die mould signal；
Low-pass filter is electrically connected transformer, for filtering out high frequency harmonic components.
Control interface between the FPGA control circuit and DDS group circuits includes：Serial SPI interface and parallel data
Interface.
The model AD9914 of the DDS chips, the chip model of transformer is TC1-1-13M+, low-pass filter
Cutoff frequency is 1000MHz, system clock 2400MHz, and the chip model of clock distribution circuit is HMC7043, storage circuit
Using SDRAM DDR2 chips, chip model MT47H128M16.
The present invention also provides a kind of signal generating methods of the intermediate-freuqncy signal source of MIMO radar target seeker, include following step
Suddenly：
FPGA control circuit generates random sequence in real time, and noise parameter is obtained by being iterated computing to random sequence,
And noise parameter is converted into frequency control word, amplitude control words or phase control words；
Noise parameter is sequentially stored into storage circuit by FPGA control circuit, until the random sequence for completing a frame is deposited
Storage；
When intermediate-freuqncy signal source needs to generate noise signal, FPGA control circuit completes the register to DDS chips first
Basic configuration, and DDS chips is controlled to be transformed into direct read/write parameter mode；
According to the requirement for generating noise pulse signal, FPGA control circuit takes out noise parameter hair from storage circuit in real time
DDS chips are given, DDS chips generate orthogonal Wideband Intermediate Frequency noise signal by quick renewal frequency control word in real time.
The iterative formula of random sequence is：
X (n)=0.5-1.99 | x (n-1) |
Wherein, n=1,2,3 ..., x (0)=0.5.
The invention has the advantages that：
Take full advantage of fpga chip flexible in programming and special DDS chip frequencies feature with high accuracy, generated MIMO
Radar mean frequency orthogonal signalling frequency resolution is 0.8149Hz, and intermediate-frequency bandwidth reaches as high as 1350MHz, than using FPGA and high speed
The mode of DA structures is higher by an order of magnitude.Only need one group of DDS passage that can generate the MIMO radar intermediate frequency quadrature in big broadband
Signal is combined the present invention with upconverter, can complete the wideband orthogonal waveform transmitting letter of each frequency range MIMO radar target seeker
Number.
Description of the drawings
Fig. 1 is a kind of electrical block diagram of the intermediate-freuqncy signal source of MIMO radar target seeker provided by the invention.
Fig. 2 is that noise parameter generates schematic diagram.
Fig. 3 is the schematic diagram for generating orthogonal wideband noise.
Fig. 4 is that FPGA control DDS chips generate broadband noise schematic diagram.
Specific embodiment
Below according to Fig. 1~Fig. 4, presently preferred embodiments of the present invention is illustrated.
Fpga chip, which has the advantages that be easily programmed, controls flexible, dedicated Direct Digital Synthesizer (DDS) core
Piece has the features such as generation signal bandwidth is big, variable frequency range is wide, frequency step is small, amplitude and high frequency accuracy, system clock
It can generally accomplish more than 1GHz.It, will by the way of FPGA and dedicated Direct Digital Synthesizer (DDS) chip
The advantages of the advantages of fpga chip and special DDS chips, combines, and this mode is no matter in terms of signal generation or work
There is certain advantage in terms of Cheng Shixian.
As shown in Figure 1, the present invention provides a kind of intermediate-freuqncy signal source of MIMO radar target seeker, comprising：
FPGA control circuit 1, for generating timing control signal and noise parameter, and it is orthogonal that DDS groups circuit is controlled to generate
Wideband Intermediate Frequency noise signal；
DDS groups circuit 2 is electrically connected FPGA control circuit 1, for being generated just under the control of FPGA control circuit 1
Hand over Wideband Intermediate Frequency noise signal；
Clock distribution circuit 3 is electrically connected FPGA control circuit 1 and DDS groups circuit 2, in FPGA control circuit 1
Control under generate synchronizing clock signals be sent to DDS groups circuit 2；
Storage circuit 4 is electrically connected FPGA control circuit 1, for storing the much noise of the generation of FPGA control circuit 1
Parameter.
Further, the DDS groups circuit 2 includes：Multiple DDS modules, each DDS module connect FPGA control electricity respectively
Road 1 and clock distribution circuit 3, each DDS module generate the signal of a passage respectively.
The DDS module further includes：
DDS chips 201 are electrically connected FPGA control circuit 1 and clock distribution circuit 3, in FPGA control circuit 1
Control under generate orthogonal wideband mid-frequency noise signal；
Transformer 202 is electrically connected DDS chips 201, for the intermediate-freuqncy signal that generates DDS chips 201 by current mode
Be converted to voltage mode signals；
Low-pass filter 203 is electrically connected transformer 202, for filtering out high frequency harmonic components.
In the present embodiment, the model AD9914 of the DDS chips 201, the chip model of transformer 202 is TC1-
1-13M+, the cutoff frequency of low-pass filter 203 is 1000MHz；
The clock distribution circuit 3 is converted to the clock reference signal for receiving external clock reference signal
Differential clock signal is assigned on 2 channel DDSs, for the system clock between synchronous each DDS module, ensures each passage
The system clock of DDS is homologous clock, and system clock 2400MHz can generate centre frequency as 840MHz, bandwidth 100MHz
Orthogonal noise signal, the chip model of clock distribution circuit 3 is HMC7043；
The storage circuit 4 is for storing noise parameter, since each pulse of broadband noise radar signal is non-phase
Ginseng, it is therefore desirable to store substantial amounts of noise parameter, noise parameter can be frequency control word, amplitude control words or phase control
Word processed, storage circuit 4 use SDRAM DDR2 chips, and chip model is MT47H128M16, it is necessary to which two panels chip is made into 32
Storage circuit.
Control interface between the FPGA control circuit 1 and DDS groups circuit 2 includes：Serial SPI interface and and line number
According to interface, to meet the needs of different working modes.
The present invention also provides a kind of intermediate-freuqncy signal source signal generating methods of MIMO radar target seeker, comprise the steps of：
Step S1, after intermediate-freuqncy signal source powers on, random sequence is generated by FPGA control circuit in real time first, by with
Machine sequence is iterated computing and obtains noise parameter, and noise parameter is converted into frequency control word, amplitude control words or phase
Position control word；
Step S2, by controlling the write-in of storage circuit, noise parameter is sequentially stored into storage by FPGA control circuit
In circuit, the storage of the random sequence until completing a frame；
Step S3, when intermediate-freuqncy signal source needs to generate noise signal, FPGA control circuit is completed first to DDS chips
The basic configuration of register, and DDS chips is controlled to be transformed into direct read/write parameter mode；
Step S4, according to the requirement for generating noise pulse signal, FPGA control circuit takes out from storage circuit make an uproar in real time
Sound parameter, and pass through 32 position datawires between FPGA control circuit and DDS module and be sent to DDS chips, DDS chips pass through fast
Fast renewal frequency control word (being updated once per 10ns) generates orthogonal Wideband Intermediate Frequency noise signal in real time.
In the step S1, the precision of there are many generations of random sequence signal method, wherein physical noise generator
Be highest, but be unfavorable for Project Realization, said on the noise sequence stricti jurise that digit synthesis noise generator generates be it is pseudo- with
Machine noise, but as long as cycle long enough is with regard to that can meet requirement of engineering.
As shown in Fig. 2, generating random sequence using iterative formula in the present invention, the iterative formula of random sequence is：
X (n)=0.5-1.99 | x (n-1) |
Wherein, n=1,2,3 ..., x (0)=0.5.It is wanted since the parameter for generating orthogonal wideband noise signal quickly changes
It asks, and parameter is obtained by random sequence interative computation, the real-time speed that generates of FPGA control circuit is slow, can not meet
The Parameters variation requirement of high speed, it is therefore desirable to additional storage device, and storage device needs to have higher storage and reads speed
Degree.Since each pulse of broadband noise radar signal is non-coherent, it is therefore desirable to the chip of large storage capacity.Simple is outer
Non-volatile memory mode is hung since the capacity of monolithic is small, reading speed is slow, generally requires multi-plate chip and builds, and passes through complexity
Control can be only achieved the requirement of large storage capacity and high reading speed.For SDRAM DDR2 since memory capacity is big, reading speed is high,
But it is power down volatile memory.Therefore random sequence is generated in real time and changes into frequency control word using FPGA after the power is turned on, deposit
In the SDRAM DDR2 chips of large capacity, until needing with noise parameter, then taken out from SDRAM control DDS's in real time
Method is realized.
As shown in figure 3, after intermediate-freuqncy signal source powers on, noise parameter, FPGA controls are generated by FPGA control circuit first
Noise parameter is sequentially stored into storage circuit by circuit, the storage of the random sequence until completing a frame.Believe in pulse radar
In number disposal system, there are many working methods, are all that a frame data (bold and unconstrained second grade) obtain a handling result, if working method
Orthogonal wideband noise pattern is switched to, typically generates noise signal by a unit interval of a frame signal, if necessary
Multiframe signal, which is same group of noise sequence, to be cycled by DDS and generates, for example when 100ms is 1 frame data, FPGA control circuit is first
It calculates sufficiently long noise sequence and stores and ensure that DDS can generate the wideband orthogonal noise of 100ms under noise pattern.It makes an uproar
Ping is the enable signal that DDS chips generate noise FM signal, if noise pulse is 1, illustrates that intermediate-freuqncy signal source needs
Noise signal is generated, FPGA control circuit takes out noise parameter in real time from storage circuit and is sent to DDS chips, DDS chips
Orthogonal Wideband Intermediate Frequency noise signal is generated in real time.As shown in figure 4, the 32 parallel-by-bit pin ports of AD9914 are only with one group 4
Vertical functional pin F [3:0] cooperate, the state of 4 functional pins determines the configuration mode of 32 parallel-by-bit ports.Work as application
Logic level on functional pin is F [3:When 0]=0000, parallel schema is effective.Set AD9914's using the pattern
Function register.Wherein, function register is set to include enabled clock distribution circuit and exports SYNCCLK (during 1/24 system
Clock), parallel data stream is enabled, opens amplitude control switch OSK.When the logic level being applied on functional pin is F [3:0]=
When 0010 to 1101, parallel port is used as accessing 32 bit frequencies in DDS kernels, 16 phases and 12 range parameters
High-speed interface.User can directly control DDS parameters (or various combination of frequency, phase, amplitude these parameters), parallel port
It is run with the sampling rate for being equal to 1/24 system clock.Use the function that noise parameter is updated with the rate of 100M,
Meet the application demand of wide-band modulation well.
FPGA control circuit is as follows to the control flow of DDS chips：The reseting pin of DDS chips is resetted first,
Then basic configuration, such as enabled SYNCCLK are carried out to register again, opens amplitude control switch OSK etc..Register is matched somebody with somebody
It is F [3 to put the logic level on the functional pin of AD9914:0] configured in the state of=0000.During configuration AD9914 with
32 direct-connected DDS data pins are divided into the register control line of 8, and the register address line of 8 and 16 s' posts
Latch data line.After the completion of basic configuration, the logic level on functional pin is set to enter direct read/write parameter mode, it should
Lower 32 data pins of pattern only make data cable, for transmitting noise parameter.Logic level on the functional pin of AD9914
For F [3:When 0]=0101,32 data pins are used to transmit initial phase parameter and range parameter.When the function of AD9914 is drawn
Logic level on foot is F [3:When 0]=0010,32 data pins are used to transmit noise frequency parameter.
Intermediate-freuqncy signal source provided by the invention has following performance：
1st, rate-adaptive pacemaker scope：Frequency source generates signal using Direct frequency synthesizer (DDS) technology in orthogonal wideband noise, when
When inputting DDS working clock frequencies selection 2.4GHz, frequency source reference frequency output is DC~1GHz in orthogonal wideband noise.(when
When inputting DDS working clock frequencies selection 3.5GHz, chip highest output frequency is 1.4GHz)；
2nd, spurious reduction performance：According to DDS chips AD9914 at work clock position 2.4GHz when spurious-free dynamic range
Situation understand, in orthogonal wideband noise frequency source output frequency range 790M~890M signal spurious reduction can reach -60dBc with
On.
3rd, fast frequency-hopped ability：Frequency source is using state-of-the-art DDS chips in the industry in orthogonal wideband noise, when using parallel end
Mouthful when directly controlling pattern, system work clock is 2.4GHz, and DDS parameters are updated with the rate of highest 100M, i.e., frequency hopping when
Between most it is short be 10ns.(system work clock is 3.5GHz, and it is 7.2ns that the accessible most short Hopping time of chip is most short).
4th, storage resource：Frequency source configures 2 DDR2SDRAM in orthogonal wideband noise, and every SDRAM memory capacity is 256M
× 16bit, total capacity reach 1GB.
5th, communication capacity：When FPGA communicates with storage chip DDR2SDRAM inside frequency source in orthogonal wideband noise, working
In a state that frequency is 200MHz, DDR2SDRAM's writes bandwidth up to 1.431GB/S, and tape reading is wide to reach 1.448GB/S.
The invention has the advantages that：
Take full advantage of fpga chip flexible in programming and special DDS chip frequencies feature with high accuracy, generated MIMO
Radar mean frequency orthogonal signalling frequency resolution is 0.8149Hz, and intermediate-frequency bandwidth reaches as high as 1350MHz, than using FPGA and high speed
The mode of DA structures is higher by an order of magnitude.Only need one group of DDS passage that can generate the MIMO radar intermediate frequency quadrature in big broadband
Signal is combined the present invention with upconverter, can complete the wideband orthogonal waveform transmitting letter of each frequency range MIMO radar target seeker
Number.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. a kind of intermediate-freuqncy signal source of MIMO radar target seeker, which is characterized in that include：
FPGA control circuit (1) for generating timing control signal and noise parameter, and controls DDS groups circuit to generate orthogonal width
Band mid-frequency noise signal；
DDS groups circuit (2) is electrically connected FPGA control circuit (1), for being generated under the control of FPGA control circuit (1)
Orthogonal wideband mid-frequency noise signal；
Clock distribution circuit (3) is electrically connected FPGA control circuit (1) and DDS groups circuit (2), for controlling electricity in FPGA
Synchronizing clock signals are generated under the control on road (1) and are sent to DDS groups circuit (2)；
Storage circuit (4) is electrically connected FPGA control circuit (1), makes an uproar for storing a large amount of of FPGA control circuit (1) generation
Sound parameter.
2. the intermediate-freuqncy signal source of MIMO radar target seeker as described in claim 1, which is characterized in that the DDS group circuits
(2) include：Multiple DDS modules, each DDS module connect FPGA control circuit (1) and clock distribution circuit (3) respectively, each
DDS module generates the signal of a passage respectively.
3. the intermediate-freuqncy signal source of MIMO radar target seeker as claimed in claim 2, which is characterized in that the DDS module into
One step includes：
DDS chips (201) are electrically connected FPGA control circuit (1) and clock distribution circuit (3), for controlling electricity in FPGA
Orthogonal wideband mid-frequency noise signal is generated under the control on road (1)；
Transformer (202) is electrically connected DDS chips (201), for the intermediate-freuqncy signal that generates DDS chips (201) by electric current
Type is converted to voltage mode signals；
Low-pass filter (203) is electrically connected transformer (202), for filtering out high frequency harmonic components.
4. the intermediate-freuqncy signal source of MIMO radar target seeker as claimed in claim 3, which is characterized in that the FPGA control electricity
Control interface between road (1) and DDS groups circuit (2) includes：Serial SPI interface and parallel data grabbing card.
5. the intermediate-freuqncy signal source of MIMO radar target seeker as claimed in claim 4, which is characterized in that the DDS chips
(201) model AD9914, the chip model of transformer (202) are TC1-1-13M+, the cutoff frequency of low-pass filter (203)
Rate is 1000MHz, system clock 2400MHz, and the chip model of clock distribution circuit (3) is HMC7043, storage circuit (4)
Using SDRAM DDR2 chips, chip model MT47H128M16.
6. a kind of signal generation side of the intermediate-freuqncy signal source of the MIMO radar target seeker in 1-5 such as claim as described in any one
Method, which is characterized in that comprise the steps of：
FPGA control circuit generates random sequence in real time, and noise parameter is obtained by being iterated computing to random sequence, and will
Noise parameter is converted into frequency control word, amplitude control words or phase control words；
Noise parameter is sequentially stored into storage circuit by FPGA control circuit, the storage of the random sequence until completing a frame；
When intermediate-freuqncy signal source needs to generate noise signal, FPGA control circuit completes the base of the register to DDS chips first
This configuration, and DDS chips is controlled to be transformed into direct read/write parameter mode；
According to the requirement for generating noise pulse signal, FPGA control circuit takes out noise parameter in real time from storage circuit and is sent to
DDS chips, DDS chips generate orthogonal Wideband Intermediate Frequency noise signal by quick renewal frequency control word in real time.
7. the signal generating method of the intermediate-freuqncy signal source of MIMO radar target seeker as claimed in claim 6, which is characterized in that with
The iterative formula of machine sequence is：
X (n)=0.5-1.99 | x (n-1) |
Wherein, n=1,2,3 ..., x (0)=0.5.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107682011A (en) * | 2017-09-26 | 2018-02-09 | 天津光电通信技术有限公司 | A kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method |
| CN109507642A (en) * | 2018-12-29 | 2019-03-22 | 广西科技大学 | A kind of Nonlinear Parameter harmonic detecting method based on noise FM technology |
| CN109542815A (en) * | 2018-09-28 | 2019-03-29 | 天津市英贝特航天科技有限公司 | A kind of high-speed d/a system and working method based on USB3.0 interface |
| CN110995251A (en) * | 2019-12-04 | 2020-04-10 | 山东浪潮人工智能研究院有限公司 | Frequency hopping source for reducing frequency changing time and using method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080074311A1 (en) * | 2006-09-26 | 2008-03-27 | Lockheed Martin Corporation | System and Method for Coherent Frequency Switching in DDS Architectures |
| CN102724162A (en) * | 2012-06-25 | 2012-10-10 | 中国科学院武汉物理与数学研究所 | Multi-channel nuclear magnetic resonance radio frequency signal transmitter |
| CN103001898A (en) * | 2012-11-27 | 2013-03-27 | 重庆西南集成电路设计有限责任公司 | Quad-channel I/Q signal source |
| CN104090270A (en) * | 2014-07-22 | 2014-10-08 | 中国科学院空间科学与应用研究中心 | Signal generator used for generating chaos radar signals in real time |
| CN104683273A (en) * | 2013-11-27 | 2015-06-03 | 中国航空工业集团公司雷华电子技术研究所 | Direct digital synthesizer (DDS) chip based Gaussian filtered minimum shift keying (GMSK) signal generation method |
| CN104977569A (en) * | 2015-07-13 | 2015-10-14 | 重庆大学 | Universal micro-deformation intermediate-frequency beacon |
-
2017
- 2017-11-28 CN CN201711217470.3A patent/CN108107409A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080074311A1 (en) * | 2006-09-26 | 2008-03-27 | Lockheed Martin Corporation | System and Method for Coherent Frequency Switching in DDS Architectures |
| CN102724162A (en) * | 2012-06-25 | 2012-10-10 | 中国科学院武汉物理与数学研究所 | Multi-channel nuclear magnetic resonance radio frequency signal transmitter |
| CN103001898A (en) * | 2012-11-27 | 2013-03-27 | 重庆西南集成电路设计有限责任公司 | Quad-channel I/Q signal source |
| CN104683273A (en) * | 2013-11-27 | 2015-06-03 | 中国航空工业集团公司雷华电子技术研究所 | Direct digital synthesizer (DDS) chip based Gaussian filtered minimum shift keying (GMSK) signal generation method |
| CN104090270A (en) * | 2014-07-22 | 2014-10-08 | 中国科学院空间科学与应用研究中心 | Signal generator used for generating chaos radar signals in real time |
| CN104977569A (en) * | 2015-07-13 | 2015-10-14 | 重庆大学 | Universal micro-deformation intermediate-frequency beacon |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107682011A (en) * | 2017-09-26 | 2018-02-09 | 天津光电通信技术有限公司 | A kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method |
| CN109542815A (en) * | 2018-09-28 | 2019-03-29 | 天津市英贝特航天科技有限公司 | A kind of high-speed d/a system and working method based on USB3.0 interface |
| CN109507642A (en) * | 2018-12-29 | 2019-03-22 | 广西科技大学 | A kind of Nonlinear Parameter harmonic detecting method based on noise FM technology |
| CN110995251A (en) * | 2019-12-04 | 2020-04-10 | 山东浪潮人工智能研究院有限公司 | Frequency hopping source for reducing frequency changing time and using method thereof |
| CN110995251B (en) * | 2019-12-04 | 2023-12-08 | 山东浪潮科学研究院有限公司 | Frequency hopping source capable of reducing frequency changing time and application method thereof |
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Application publication date: 20180601 |