CN107682011A - A kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method - Google Patents
A kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method Download PDFInfo
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- CN107682011A CN107682011A CN201710884047.2A CN201710884047A CN107682011A CN 107682011 A CN107682011 A CN 107682011A CN 201710884047 A CN201710884047 A CN 201710884047A CN 107682011 A CN107682011 A CN 107682011A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
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Abstract
The invention provides a kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method, including fpga chip, configurable clock generator module in the fpga chip, the clock module connects digital frequency synthesizer；Also include M sequence generative circuit and M sequence sample circuit, the M sequence generative circuit connects clock module, the input of the output end connection M sequence sample circuit of the M sequence generative circuit, the output end of the connection M sequence sample circuit and the output end of digital frequency synthesizer all connect frequency mixer, the output end connection D/A converting circuit of the frequency mixer, intermediate-freuqncy signal is exported by D/A converting circuit.The adjustable signal generator of intermediate frequency of signal to noise ratio of the present invention and implementation method can realize that the mixing of intermediate-freuqncy signal and white noise exports in very big frequency band, the signal to noise ratio of output signal can be accurately controlled simultaneously, and strong support is provided to complete the functional test of communication system.
Description
Technical field
The invention belongs to signal processing technology field, more particularly, to a kind of adjustable signal generator of intermediate frequency of signal to noise ratio and
Implementation method.
Background technology
In a communications system, IF-FRE is generally tens of or up to a hundred megahertzs.In R＆D process, it is often necessary to test system
The service behaviour united under the conditions of different signal to noise ratio intermediate-freuqncy signals, so as to simulate real working condition.At present, price is relatively low
Ordinary signal generation typically without produce white noise function or can produce noise very bandwidth it is narrow.And there are similar functions
Signal generator often price is prohibitively expensive, this cause communication system research and development encounter great difficulty.
The content of the invention
In view of this, the present invention is directed to propose a kind of adjustable signal generator of intermediate frequency of signal to noise ratio and implementation method, with solution
Certainly existing signal generator of intermediate frequency can not produce the situation of white noise.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
A kind of adjustable signal generator of intermediate frequency of signal to noise ratio, including input module, control module, FPGA chips, digital-to-analogue turn
Change circuit, the signal input part of the signal output part link control module of the input module；
Configurable clock generator module, digital frequency synthesizer, frequency mixer in the fpga chip, the clock module connection numeral
Frequency synthesizer, the fpga chip also include M sequence generative circuit and M sequence sample circuit, and the M sequence generative circuit connects
Connect clock module, the input of the output end connection M sequence sample circuit of the M sequence generative circuit, the connection M sequence amount
Change the output end of circuit and the output end of digital frequency synthesizer all connects frequency mixer；
The output end connection D/A converting circuit of the frequency mixer, intermediate-freuqncy signal is exported by D/A converting circuit.
Further, the control module uses AT89S52 chips, and the control module is also connected with display module.
Further, the display module is dot character liquid crystal display, the number of the display module and AT89S52
According to transmission using the transmission of 8 parallel-by-bits or the transmission of 4 parallel-by-bits.
Further, the input module is determinant keyboard, and keyboard is provided with 16 keys altogether, including numerical key, list
Position key and function key, input control is carried out by keyboard to required signal-to-noise ratio and the frequency of signal.
Further, the clock module includes the crystal oscillating circuit that output frequency is 25MHz, and the crystal oscillating circuit connects number
Word phaselocked loop, the clock signal for realizing 100MHz by digital phase-locked loop export.
Further, the fpga chip connects D/A converting circuit by SPI interface；The D/A converting circuit uses
AD9117 type DAC chips.
A kind of implementation method of the adjustable signal generator of intermediate frequency of signal to noise ratio, comprises the following steps：
S1, control module to fpga chip send control signal, fpga chip using digital frequency synthesizer technology when
Mid-frequency sinusoidal signal is produced under clock module drive；
S2, fpga chip produce M sequence using clock module driving M sequence generative circuit, the letter according to needed for control module
Make an uproar than and the output digit of intermediate-freuqncy signal M sequence signal is quantified；
S3, the M sequence value after quantization and intermediate-freuqncy signal be mixed, by D/A converting circuit obtain needed for intermediate frequency letter
Number.
Further, in the step S1, the method for producing intermediate-freuqncy signal is：
S101, use output frequency to be inputted for 25MHz crystal oscillator as clock, realized using Digital Phase-Locked Loop Technology
100MHz clock signal is as system clock；
S102, using digital frequency synthesizer technology the clock signal of system driving under produce mid-frequency sinusoidal signal, letter
Number frequency is less than 50MHz according to Nyquist.
Further, in the step S2, the method for generation and the quantization of M sequence is specific as follows：
S201, M sequence generated using the primitive polynomial of 128 ranks, its expression formula is：
F (x)=x128+x29+x27+x2+1
Sequence initial value is arranged to any non-zero status；
S202, because intermediate-freuqncy signal is full width output, according to the output digit of required signal-to-noise ratio and intermediate-freuqncy signal to M sequences
Column signal is quantified；When system requirements signal to noise ratio is higher, using relatively low quantization digit, so as to reduce the width of noise signal
Degree；Conversely, when system requirements signal to noise ratio is relatively low, the higher quantization digit of use, so as to increase the amplitude of noise signal.
Relative to prior art, the adjustable signal generator of intermediate frequency of signal to noise ratio of the present invention and implementation method have with
Lower advantage：
The adjustable signal generator of intermediate frequency of signal to noise ratio of the present invention and implementation method with different quantization digits it is pseudo- with
Based on machine sequence, each function is realized by SCM＆FPGA；Realized by adjusting the quantization digit of pseudo-random sequence
The adjustable signal generator of intermediate frequency of signal to noise ratio；This is designed to realize that the mixing of intermediate-freuqncy signal and white noise is defeated in very big frequency band
Go out, while the signal to noise ratio of output signal can be controlled, strong support is provided to complete the functional test of communication system；In addition, this
The cost of design is relatively low, and peripheral circuit is simple, is easy to safeguard and changes, practicality is stronger.
Brief description of the drawings
The accompanying drawing for forming the part of the present invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the signal generator principle assumption diagram described in the embodiment of the present invention；
Fig. 2 is the adjustable signal generator of intermediate frequency principle schematic of signal to noise ratio described in the embodiment of the present invention；
Fig. 3 is the M sequence generative circuit schematic diagram described in the embodiment of the present invention；
Fig. 4 is that the control module described in the embodiment of the present invention is connected circuit diagram with display module；
Fig. 5 is the keyboard circuit figure described in the embodiment of the present invention.
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or dark
Show that the device of meaning or element there must be specific orientation, with specific azimuth configuration and operation, thus it is it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " etc. are only used for describing purpose, and it is not intended that instruction or hint phase
To importance or the implicit quantity for indicating indicated technical characteristic.Thus, the feature for defining " first ", " second " etc. can
To express or implicitly include one or more this feature.In the description of the invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
Describe the present invention in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Due to real random sequence and it is not present, we can only go approximate random using pseudo-random sequence in real work
Sequence.M sequence is a kind of typical pseudo-random sequence.Pseudo-random sequence as a kind of signal form have good randomness and
Close to the correlation function of white noise, therefore the occasion of random signal can be applied to instead of white noise.At the beginning of sequence is set
It is worth for non-zero status, computing is iterated to this sequence using n primitive polynomial, using sequence highest order as output, you can
Obtain the pseudo-random sequence that cycle period is 2n-1.When n is sufficiently large, the length long enough of the sequence just can be approximated to be not
The noise random sequence repeated.
The sinusoidal signal of IF-FRE is realized using the IP kernel in FPGA, by rationally setting sinusoidal signal and M sequence
Digit is exported, is exported after two signals are mixed to DAC chip, you can obtains the adjustable intermediate-freuqncy signal of signal to noise ratio.
As shown in Figures 1 to 5, the adjustable signal generator of intermediate frequency of a kind of signal to noise ratio, including input module, control module,
Fpga chip, D/A converting circuit, the signal input part of the signal output part link control module of the input module；
Configurable clock generator module, digital frequency synthesizer, frequency mixer in the fpga chip, the clock module connection numeral
Frequency synthesizer, the fpga chip also include M sequence generative circuit and M sequence sample circuit, and the M sequence generative circuit connects
Connect clock module, the input of the output end connection M sequence sample circuit of the M sequence generative circuit, the connection M sequence amount
Change the output end of circuit and the output end of digital frequency synthesizer all connects frequency mixer；
The output end connection D/A converting circuit of the frequency mixer, intermediate-freuqncy signal is exported by D/A converting circuit.
As shown in figure 4, control module uses AT89S52 chips.AT89S52 is a kind of low-power consumption, high-performance CMOS 8
Microcontroller, it is compatible with 51 series monolithics, has high-performance, high reliability and low-cost advantage.Control chip master
Complete display and the control function of signal.The control of signal is mainly completed by input through keyboard.By keyboard, can set
The signal to noise ratio of signal generator and the transmission frequency of intermediate-freuqncy signal, and shown by display module.
Aobvious module point uses dot character liquid crystal display, and dot character liquid crystal display is used exclusively for showing various words
The display of symbol.Display screen and AT89S52 data transfer can use the transmission of 8 parallel-by-bits or the transmission of 4 parallel-by-bits, can show
Two dot characters of row 32, therefore can be come out the Chinese characters such as signal to noise ratio and signal frequency point with numerical monitor by programming.Screen with
Control chip AT89S52 connection is as shown in Figure 4.
Keyboard circuit as shown in figure 5, using standard 4x4 keyboards, input module is determinant keyboard, and keyboard is provided with 16 altogether
Individual key, including numerical key, unit key and function key, input control is carried out to required signal-to-noise ratio and the frequency of signal by keyboard
System.The design of keyboard need to meet that the I/O mouths of keyboard interface occupancy single-chip microcomputer lack, while can provide enough bond numbers, therefore use
Determinant keyboard.Finally shown again by LCD screen.Clock module includes the crystal oscillating circuit that output frequency is 25MHz,
The crystal oscillating circuit connects digital phase-locked loop, and the clock signal for realizing 100MHz by digital phase-locked loop exports.
Keyboard button function table is as follows：
| Key number | Function | Key number | Function |
| S1 | Numeral 1 | S9 | Numeral 9 |
| S2 | Numeral 2 | S10 | Numeral 0 |
| S3 | Numeral 3 | S11 | Reset |
| S4 | Numeral 4 | S12 | Retain |
| S5 | Numeral 5 | S13 | Retain |
| S6 | Numeral 6 | S14 | Modification is set |
| S7 | Numeral 7 | S15 | Frequency/signal to noise ratio switching |
| S8 | Numeral 8 | S16 | Confirm |
D/A converting circuit uses AD9117 type DAC chips.The D/A converting circuit uses AD9117 type DAC chips.
The chip is the DAC chip of 14-bit precision, and maximum conversion speed meets system requirements enough up to 125M/s.Due to
The relation of DAC quantization digits and signal to noise ratio is 6dB/bit, so the satisfiable signal to noise ratio of the DAC chip of 14-bit precision is most
Larger Dynamic scope is 84dB.
The implementation method of the adjustable signal generator of intermediate frequency of signal to noise ratio, comprises the following steps：
S1, control module to fpga chip send control signal, fpga chip using digital frequency synthesizer technology when
Mid-frequency sinusoidal signal is produced under clock module drive；
S2, fpga chip produce M sequence using clock module driving M sequence generative circuit, according to required signal-to-noise ratio and
The output digit of intermediate-freuqncy signal quantifies to M sequence signal；
S3, the M sequence value after quantization and intermediate-freuqncy signal be mixed, by D/A converting circuit obtain needed for intermediate frequency letter
Number.
In the step S1, the method for producing intermediate-freuqncy signal is：
S101, use output frequency to be inputted for 25MHz crystal oscillator as clock, realized using Digital Phase-Locked Loop Technology
100MHz clock signal is as system clock；
S102, using digital frequency synthesizer technology the clock signal of system driving under produce mid-frequency sinusoidal signal, letter
Number frequency is less than 50MHz according to Nyquist.
As shown in Fig. 2 in step S2, the method for generation and the quantization of M sequence is specific as follows：
S201, in order to ensure generation noise can farthest approach white noise, using the primitive polynomial of 128 ranks
To generate M sequence, its expression formula is：
F (x)=x128+x29+x27+x2+1
Sequence initial value is arranged to any non-zero status；
S202, because intermediate-freuqncy signal is full width output, according to the output digit of required signal-to-noise ratio and intermediate-freuqncy signal to M sequences
Column signal is quantified；When system requirements signal to noise ratio is higher, using relatively low quantization digit, so as to reduce the width of noise signal
Degree；Conversely, when system requirements signal to noise ratio is relatively low, the higher quantization digit of use, so as to increase the amplitude of noise signal.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements made etc., should be included in the scope of the protection with principle.
Claims (9)
- A kind of 1. adjustable signal generator of intermediate frequency of signal to noise ratio, it is characterised in that：Including input module, control module, FPGA cores Piece, D/A converting circuit, the signal input part of the signal output part link control module of the input module；Configurable clock generator module, digital frequency synthesizer, frequency mixer in the fpga chip, the clock module connect numerical frequency Synthesizer, the fpga chip also includes M sequence generative circuit and M sequence sample circuit, when the M sequence generative circuit connects Clock module, the input of the output end connection M sequence sample circuit of the M sequence generative circuit, the connection M sequence quantify electricity The output end on road and the output end of digital frequency synthesizer all connect frequency mixer；The output end connection D/A converting circuit of the frequency mixer, intermediate-freuqncy signal is exported by D/A converting circuit.
- 2. the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 1, it is characterised in that：The control module is adopted With AT89S52 chips, the control module is also connected with display module.
- 3. the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 2, it is characterised in that：The display module is Dot character liquid crystal display, the data transfer of the display module and AT89S52 is transmitted using 8 parallel-by-bits or 4 parallel-by-bits pass It is defeated.
- 4. the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 1, it is characterised in that：The input module is Determinant keyboard, keyboard is provided with 16 keys altogether, including numerical key, unit key and function key, by keyboard to required noise Than carrying out input control with the frequency of signal.
- 5. the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 1, it is characterised in that：The clock module bag The crystal oscillating circuit that output frequency is 25MHz is included, the crystal oscillating circuit connects digital phase-locked loop, realized by digital phase-locked loop 100MHz clock signal output.
- 6. the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 1, it is characterised in that：The fpga chip leads to Cross SPI interface connection D/A converting circuit；The D/A converting circuit uses AD9117 type DAC chips.
- A kind of 7. implementation method of the adjustable signal generator of intermediate frequency of signal to noise ratio described in claim 1, it is characterised in that including Following steps：S1, control module send control signal to fpga chip, and fpga chip is using digital frequency synthesizer technology in clock mould Block driving is lower to produce mid-frequency sinusoidal signal；S2, fpga chip produce M sequence using clock module driving M sequence generative circuit, according to control module required signal-to-noise ratio And the output digit of intermediate-freuqncy signal quantifies to M sequence signal；S3, the M sequence value after quantization and intermediate-freuqncy signal be mixed, required intermediate-freuqncy signal is obtained by D/A converting circuit.
- 8. the implementation method of the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 7, it is characterised in that described In step S1, the method for producing intermediate-freuqncy signal is：S101, use output frequency to be inputted for 25MHz crystal oscillator as clock, realize 100MHz's using Digital Phase-Locked Loop Technology Clock signal is as system clock；S102, mid-frequency sinusoidal signal, signal frequency are produced under clock signal of system driving using digital frequency synthesizer technology Rate is less than 50MHz according to Nyquist.
- 9. the implementation method of the adjustable signal generator of intermediate frequency of signal to noise ratio according to claim 7, it is characterised in that described In step S2, the method for generation and the quantization of M sequence is specific as follows：S201, M sequence generated using the primitive polynomial of 128 ranks, its expression formula is：F (x)=x128+x29+x27+x2+1Sequence initial value is arranged to any non-zero status；S202, because intermediate-freuqncy signal is full width output, M sequence is believed according to the output digit of required signal-to-noise ratio and intermediate-freuqncy signal Number quantified；When system requirements signal to noise ratio is higher, using relatively low quantization digit, so as to reduce the amplitude of noise signal； Conversely, when system requirements signal to noise ratio is relatively low, the higher quantization digit of use, so as to increase the amplitude of noise signal.
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