CN203387478U

CN203387478U - TMS320VC5402 chip-based programmable pulse width modulation generator

Info

Publication number: CN203387478U
Application number: CN201320508863.0U
Authority: CN
Inventors: 马胜前; 余权; 马冬梅; 范满红; 郭倩; 胡玫
Original assignee: Northwest Normal University
Current assignee: Northwest Normal University
Priority date: 2013-08-19
Filing date: 2013-08-19
Publication date: 2014-01-08
Anticipated expiration: 2023-08-19

Abstract

The utility model provides a TMS320VC5402 chip-based programmable pulse width modulation generator. The generator comprises a master control circuit, which is connected with a clock and reset circuit, a display circuit, a PWM output circuit, a power supply circuit, and a keyboard circuit. The power supply circuit is also connected with other circuits. The modulation generator fully utilizes the advantages of programmability and multi-path transmission of McBSP data clock and frame synchronous signals and reasonably sets a related register of a sampling rate generator. The frame synchronous signals after frequency division satisfy the requirement of large-scope PWM generation, and the pulse width modulation function is realized with the combination the additional PWM output circuit. The problems that a DSP5000 series does not have a highly-efficient programmable PWM system and that the employment of a timer for realizing PWM occupies much CPU resources are solved. The TMS320VC5402 chip-based programmable pulse width modulation generator is applicable to occasions which have a wide duty ratio scope and high programmability and require multi-path pulse width control.

Description

Programmable pulse width generator based on the TMS320VC5402 chip

Technical field

The utility model belongs to the signal processing technology field, relates to a kind of Programmable pulse width generator, particularly a kind of Programmable pulse width generator based on the TMS320VC5402 chip.

Background technology

Pulse-width modulation (PWM) has a wide range of applications in fields such as Electric Machine Control, signal processing and communication systems.The DSP2000 Series Controller carries the PWM function.But, in many application scenarios, need to use the controller of DSP5000 series, and the DSP5000 Series Controller do not have the function of PWM.

PWM system based on DSP has had develop rapidly at 20 century 70s, and to the eighties, the PWM technology based on DSP has been applied to each field of engineering technology.5000 series in the DSP of TI company product are not also with the function of PWM.The timer inner with it can produce PWM, but needs to consume a large amount of time of CPU, and changes the duty more complicated.Therefore, need to design a kind of PWM device that the CPU time is few, realize multichannel output that can use and programme conveniently, take on the DSP5000 Series Controller.

Summary of the invention

The purpose of this utility model is to provide a kind of Programmable pulse width generator based on the TMS320VC5402 chip that can use on the DSP5000 Series Controller, and programming is convenient, takies the CPU time few, realizes multichannel output.

For achieving the above object, the technical scheme that the utility model adopts is: a kind of Programmable pulse width generator based on the TMS320VC5402 chip, comprise governor circuit, governor circuit is connected with keyboard circuit with reset circuit, display circuit, PWM output circuit, power circuit with clock respectively; Power circuit also is connected with keyboard circuit with reset circuit, display circuit, PWM output circuit with clock respectively.

Above-mentioned governor circuit comprises main control chip, and main control chip adopts the TMS320VC5402 chip, and the 43rd pin of main control chip connects the INPUT0 end of PWM output circuit, and the 53rd pin of main control chip connects the INPUT1 end of PWM output circuit.

The utility model Programmable pulse width generator takes full advantage of the data clock of McBSP and the advantage of frame synchronizing signal programmability and multiplexing, related register to sample rate generator rationally arranges, frame synchronizing signal after frequency division meets and to produce the requirement of PWM on a large scale, and realize the pulse-width modulation function in conjunction with additional PWM output circuit, effectively solve DSP5000 series and there is no efficient PWM system able to programme, adopt timer to realize that PWM takies the problems such as cpu resource is many, be applicable to duty cycle range wide, programmability is high and need the occasions such as multichannel pulse width control.

The accompanying drawing explanation

Fig. 1 is the structural representation of the utility model modulation generator.

Fig. 2 is the connection diagram of TMS320VC5402 and PWM output circuit in the utility model modulation generator.

Fig. 3 is the schematic diagram of PWM output circuit in the utility model modulation generator.

Fig. 4 is the main program flow chart of the utility model modulation generator.

Fig. 5 is the interrupt vector program flow diagram in the utility model modulation generator flow process.

In Fig. 1 and Fig. 2: 1. clock and reset circuit, 2. governor circuit, 3. display circuit, 4.PWM output circuit, 5. power circuit, 6. keyboard circuit.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is elaborated.

As shown in Figure 1, the utility model modulation generator, comprise governor circuit 2, and governor circuit 2 is connected with reset circuit 1, display circuit 3, PWM output circuit 4, power circuit 5 and keyboard circuit 6 with clock respectively; Power circuit 5 also is connected with reset circuit 1, display circuit 3, PWM output circuit 4 and keyboard circuit 6 with clock respectively.

Key and display circuit 3 in keyboard circuit 6 forms man-machine interface, and the user can input given duty ratio and send demonstration by keyboard; Power circuit 5 is used for providing 3.3V, 1.8V and 5V power supply to governor circuit 2, clock and reset circuit 1, keyboard circuit 6, PWM output circuit 4 and display circuit 3.

Main control chip U1 in governor circuit 2 adopts the TMS320VC5402 chip, and the TMS320VC5402 chip is a DSP with two identical multichannel buffer serial ports (McBSP), and these two McBSP are respectively McBSP0 and McBSP1.The connection diagram of TMS320VC5402 chip and PWM output circuit 4, as shown in Figure 2, the pin 41 of main control chip U1 and pin 48 are respectively receive clock pin and the tranmitting data register pin of McBSP0.The 43rd pin of main control chip U1 and the 53rd pin are respectively the synchronous pin of received frame of McBSP0 and send the frame synchronization pin; The 43rd pin of main control chip U1 connects the INPUT0 end of PWM output circuit 4, and the 53rd pin of main control chip U1 connects the INPUT1 end of PWM output circuit 4.Data receiver pin and data that the 45th pin of main control chip U1 and the 59th pin are respectively McBSP0 send pin.The level control end that the 27th pin XF of main control chip U1 is PWM output circuit 4, be connected with the level control end OC of PWM output circuit 4.

The INPUT0 end of PWM output circuit 4 and INPUT1 end are the input signal end; The OUTPUT0 end of PWM output circuit 4 and OUTPUT1 end are output signal end.

PWM output circuit 4 as shown in Figure 3, comprises the first not gate U2 and the second bus buffer U7, and the 1st pin of the first not gate U2 and the 2nd pin of the second bus buffer U7 connect respectively the 43rd pin of main control chip U1; The 2nd pin of the first not gate U2 connects the 2nd pin of the first bus buffer U6; The 1st pin of the second bus buffer U7 is connected with the 2nd pin of the second not gate U3, and the 3rd pin of the second bus buffer U7 and the 3rd pin of the first bus buffer U6 connect respectively the OUTPUT0 end of PWM output circuit 4; The 1st pin of the 1st pin of the first bus buffer U6, the 1st pin of the second not gate U3, the 4th not gate U5 and the 1st pin of the 3rd bus buffer U8 all are connected with the 27th pin of main control chip U1; The 4th not gate U5 the 2nd pin connects the 1st pin of the 4th bus buffer U9, and the 3rd pin of the 3rd bus buffer U8 and the 3rd pin of the 4th bus buffer U9 connect respectively the OUTPUT1 end of PWM output circuit 4; The 2nd pin of the 3rd bus buffer U8 connects the 2nd pin of the 3rd not gate U4, and the 1st pin of the 3rd not gate U4 is connected with the 53rd pin of main control chip U1 respectively with the 2nd pin of the 4th bus buffer U9.

The 7th pin in all not gates all meets GND, and the 14th pin in all not gates all meets VCC.

The 7th pin in all bus buffers meets respectively GND, and the 14th pin in all bus buffers meets respectively VCC.

The first not gate U2, the second not gate U3, the 3rd not gate U4 and the 4th not gate U5 all adopt not gate 74ALS04; The first bus buffer U6, the second bus buffer U7, the 3rd bus buffer U8 and the 4th bus buffer U9 all adopt four bus buffer 74ALS125 of ternary output.

The McBSP of clock and 1 pair of TMS320VC5402 chip of reset circuit is resetted and clock is provided; The given duty ratio of keyboard circuit 6 input; The conversion of the output of 4 pairs of McBSP frame synchronizing signals of PWM output circuit; Display circuit 3 is used for showing change in duty cycle.

The main program flow chart of the utility model modulation generator, as shown in Figure 4.After system powers on, first start maskable interrupts INT0 and McBSP0 is resetted; Again serial ports control register SPCR1 and SPCR2, reception control register RCR1 and RCR2, transmit control register XCR1 and XCR2, sample rate generation register SRGR1 and SRGR2, pin control register PCR are carried out to initialization, the cpu clock of clock selecting DSP or external clock CLKS, then set divide ratio CLKGDV, and then can access the output clock CLKG of sample rate generator; Output clock CLKG can produce FSG again after frequency division, then produces two-way square wave FSR0 and FSX0; Finally wait for and interrupting.Produce INT0 while having key to press and interrupt, INT0 interrupt service routine flow chart, as Fig. 5, it should be noted that: in keyboard, the F1 key table shows change PWM duty ratio; The F2 key table shows input validation; Q is the value of the given duty ratio of input, and its scope is 0.2%～99.8%, and minimum interval is 0.2%, can be by keyboard and program setting q value; XF is PWM level control end; FWID is 8～15 of McBSP0 sample rate generation register SRGR1; FPER is 0～11 of McBSP0 sample rate generation register SRGR2, the cycle that FPER+1 is PWM.The cycle of setting PWM is 500 clock cycle.Be divided into two kinds so change the mode of duty ratio q: when q is not more than 50%, XF=0, by formula F WID=500 * q ﹣ 1 computed duty cycle; When q is greater than 50%, XF=1, by FWID=499 ﹣ 500 * q, computed duty cycle; Directly export according to result of calculation the duty ratio that PWM requires.Its input constraint is that 500 * q is less than or equal to 499 integer, otherwise input can be pointed out error message during q.Then the FWID value of upgrading sample rate generator gets final product.

The utility model is modulated the PWM output circuit 4 in generator, can produce the two-way PWM of Complete Synchronization.One route INPUT0 input, OUTPUT0 output; Another route INPUT1 input, OUTPUT1 output, this two paths of signals transmitting procedure is identical.Not gate in PWM output circuit 4 is for the low and high level conversion, and four bus buffers of ternary output are for selecting the output of signal.The operation principle of PWM output circuit 4 is: first the register of McBSP0 in the TMS320VC5402 chip carried out to initialization, then change the value of FWID by keyboard, reach given duty ratio.McBSP1 is the same with the McBSP0 operation principle simultaneously, also can produce the two-way pwm signal.So just being expanded, this modulation generator can produce 4 road pwm signals by enough TMS320VC5402 chips.

The utility model modulation generator is by DSP inside multichannel buffered serial port related register is carried out to initialization, then regulates the FWID of serial ports control register SPCR1, additional change-over circuit and produce PWM's.For the frame synchronizing signal reached after the sample rate generator frequency division produces the requirement of PWM on a large scale, the cycle of pwm signal can be selected between 255～4095 clock cycle, but for the duty ratio that makes PWM adjustable continuously, the cycle that this modulation generator is chosen PWM is 500 clock cycle, after PWM output circuit conversion low and high level, exports.The adjustable range of PWM duty ratio is 0.2%～99.8%, and a TMS320VC5402 is with two McBSP, and each McBSP can produce the two-way PWM of Complete Synchronization.If the interrupt mode that this modulation generator adopts does not change duty ratio, do not take the time of CPU.The interruption access times have been reduced, saved the interruption access time, therefore can effectively reduce to take the cpu resource of DSP, make the utility model modulation generator can increase the function of DSP5000 series at aspects such as signal processing, realize able to programme, the PWM scope large, multiplexing, take the few purpose of cpu resource of DSP.

Claims

1. the Programmable pulse width generator based on the TMS320VC5402 chip, it is characterized in that, comprise governor circuit (2), governor circuit (2) is connected with reset circuit (1), display circuit (3), PWM output circuit (4), power circuit (5) and keyboard circuit (6) with clock respectively; Power circuit (5) also is connected with reset circuit (1), display circuit (3), PWM output circuit (4) and keyboard circuit (6) with clock respectively.

2. the Programmable pulse width generator based on the TMS320VC5402 chip according to claim 1, it is characterized in that, described governor circuit (2) comprises main control chip (U1), main control chip (U1) adopts the TMS320VC5402 chip, the 43rd pin of main control chip (U1) connects the INPUT0 end of PWM output circuit (4), and the 53rd pin of main control chip (U1) connects the INPUT1 end of PWM output circuit (4).

3. the Programmable pulse width generator based on the TMS320VC5402 chip according to claim 2, it is characterized in that, described PWM output circuit (4) comprises the first not gate (U2) and the second bus buffer (U7), and the 1st pin of the first not gate (U2) and the 2nd pin of the second bus buffer (U7) connect respectively the 43rd pin of main control chip (U1); The 2nd pin of the first not gate (U2) connects the 2nd pin of the first bus buffer (U6); The 1st pin of the second bus buffer (U7) is connected with the 2nd pin of the second not gate (U3), and the 3rd pin of the second bus buffer (U7) and the 3rd pin of the first bus buffer (U6) connect respectively the OUTPUT0 end of PWM output circuit (4); The 1st pin of the 1st pin of the first bus buffer (U6), the 1st pin of the second not gate (U3), the 4th not gate (U5) the 1st pin and the 3rd bus buffer (U8) all is connected with the 27th pin of main control chip (U1); The 4th not gate (U5) the 2nd pin connects the 1st pin of the 4th bus buffer (U9), and the 3rd pin of the 3rd pin of the 3rd bus buffer (U8) and the 4th bus buffer (U9) connects respectively the OUTPUT1 end of PWM output circuit (4); The 2nd pin of the 3rd bus buffer (U8) connects the 2nd pin of the 3rd not gate (U4), and the 2nd pin of the 1st pin of the 3rd not gate (U4) and the 4th bus buffer (U9) is connected with the 53rd pin of main control chip (U1) respectively.

4. the Programmable pulse width generator based on the TMS320VC5402 chip according to claim 3, it is characterized in that, described the first not gate (U2), the second not gate (U3), the 3rd not gate (U4) and the 4th not gate (U5) all adopt not gate 74ALS04.

5. the Programmable pulse width generator based on the TMS320VC5402 chip according to claim 3, it is characterized in that, described the first bus buffer (U6), the second bus buffer (U7), the 3rd bus buffer (U8) and the 4th bus buffer (U9) all adopt four bus buffer 74ALS125 of ternary output.