CN102751984A - High-speed clock data recovery system realization method and structure using same - Google Patents
High-speed clock data recovery system realization method and structure using same Download PDFInfo
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- CN102751984A CN102751984A CN2012102204979A CN201210220497A CN102751984A CN 102751984 A CN102751984 A CN 102751984A CN 2012102204979 A CN2012102204979 A CN 2012102204979A CN 201210220497 A CN201210220497 A CN 201210220497A CN 102751984 A CN102751984 A CN 102751984A
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Abstract
The invention provides a high-speed clock data recovery system realization method. According to the method, the operating frequency of an interpolation controller and the operating frequency of a phase controller is reduced under a condition that modules work under different clock frequencies according to signal characteristics, and thus the burden is greatly lightened, and the operating frequency of a whole system is improved. The structure comprises a phase position detector, an upper/lower signal filter, the interpolation controller, the phase controller, a phase selector, a phase position interpolator and a phase-locked loop, wherein the upper/lower signal filter and the other modules in head of the upper/lower signal filter work under a frequency of a clock CLKI; and the structure is characterized in that the interpolation controller and the phase controller which are arranged behind the upper/lower signal filter operate work under a frequency of a clock CLK II, and the frequency of the clock CLK II is one half of the frequency of the clock CLK I.
Description
Technical field
The present invention relates to the technical field that the high-frequency clock data are recovered, be specially a kind of high-frequency clock data recovery system implementation method, the present invention also provides the structure of using this method.
Background technology
Current social information amount expands and breaks out, and the dysfunction of message handler is powerful, and the information transfer efficiency of point-to-point transmission becomes bottleneck, and simple in order to make transmission system at a high speed, effectively, the transmitting terminal of being everlasting becomes serial to signal, transmits through carrier such as optical fiber.Because have various interference in the transmission, signal distorts, the clock data recovery system of receiving terminal then will be responsible for carrying out clock and data recovery to the serial data of receiving, therefrom extracts clock and data.For higher data transmission efficiency, then require higher transmission rate, promptly the clock data recovery system is operated under the higher clock frequency, like several GHz.The CMOS technological development is advanced by leaps and bounds, with its cheap price, and low-power consumption, high integration becomes current most important chip production technology.Various clock data recovery system products based on CMOS technology emerge in an endless stream.
Traditional clock data recovery system is as shown in Figure 1.This system by phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator and phase-locked loop constitute.Because data in the process of transmission distortion have taken place, the task of system is the serial data of transmitting terminal emission, handles, and therefrom recovers clock, data, supplies receiving terminal to use, and whole system is operated under the unified clock CLKI.The logic of interpolation controller and phase controller is the most complicated in the system, and the time of signal processing is the longest, so the operating rate of these two modules has determined the operating rate of system, has also determined the efficient of transmission, becomes the bottleneck of system speed.In order to make system works under higher clock rate, then to try every possible means to make these two modules can be operated under the higher speed.
At present in order to solve above-mentioned contradiction, the method below main the employing:
1) employing more improves production technology, with littler process device, thereby the logical circuit of each module can be operated under the higher clock rate.Thereby raising transmitting speed.But more advanced production technology expense is more expensive.
2) improve more complicated framework, like half rate clock framework, 1/4th rate frameworks.Framework is more complicated, realizes more difficulty, and cost is higher.
3) adopt special process, as ambipolar, GeSi technology etc., operating speed is the technology device faster.Special production technology expense is more expensive.
4) multichannel transmission increases transmission quantity.But multichannel makes the cost of transmission higher.
Summary of the invention
To the problems referred to above; The invention provides a kind of high-frequency clock data recovery system implementation method; Its characteristics according to signal are operated under the different clock frequencies each module, make the interpolation controller, and the operating frequency of phase controller reduces; Alleviate burden greatly, thereby can improve the whole system operation frequency.
A kind of high-frequency clock data recovery system implementation method; Its technical scheme is such: it comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Said go up under traffic filter and module before thereof be operated under the frequency of clock CLKI; It is characterized in that: said go up under interpolation controller, the phase controller of traffic filter back be operated under the frequency of clock CLK II, and the frequency of clock CLK II is half of frequency of clock CLKI.
It is further characterized in that: said go up under be provided with logic module between traffic filter and the said interpolation controller, it makes the generation signal of clock CLKI can keep one-period to give clock CLK II usefulness more.
A kind of structure of high-frequency clock data recovery system; Its technical scheme is such: it comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Clock CLKI connect respectively under traffic filter and module before thereof; It is characterized in that: the end of clock CLKI is equipped with the two-divider circuit; Said two-divider circuit output clock CLK II, the frequency of clock CLK II are frequency half the of clock CLKI, clock CLK II connect respectively said go up under said interpolation controller, phase controller after the traffic filter; Said go up under be provided with logic module between traffic filter and the said interpolation controller; Said logic module specifically comprises one or gate, two d type flip flops, and two described d type flip flops are arranged in order, and wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II; Said go up under the dateout of traffic filter connect respectively or the input of gate, the input D of first d type flip flop; The output Q of first d type flip flop connects another output of said or gate, and output said or gate connects the input D of second d type flip flop, and the output Q of second d type flip flop connects the input of said interpolation controller.
It is further characterized in that: said two-divider circuit comprises a d type flip flop, and clock CLKI connects the input end of clock CLK of said d type flip flop, and the D of said d type flip flop end, QB end are interconnected, said d type flip flop output Q output clock CLK II.
After adopting the present invention, go up under interpolation controller, the phase controller of traffic filter back be operated under the frequency of clock CLK II, and the frequency of clock CLK II is half of frequency of clock CLKI; Make full use of the characteristics of each module; Each module is operated under the different clock rates, makes the interpolation controller, the operating frequency of phase controller reduces; Alleviate burden greatly, thereby can improve the whole system operation frequency; And then make clock data recovery system under identical production technology, to be operated in higher transmission rate, improve the efficient of transmission.
Description of drawings
Fig. 1 is existing clock data recovery system framework sketch map;
Fig. 2 be go up under traffic filter input and output waveform sketch map;
Fig. 3 is a framework sketch map of the present invention;
Fig. 4 is logic module circuit figure of the present invention and oscillogram;
Fig. 5 is frequency-halving circuit of the present invention and oscillogram.
Embodiment
A kind of high-frequency clock data recovery system implementation method; See Fig. 3; It comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Go up under traffic filter and module before thereof be operated under the frequency of clock CLKI; It is characterized in that: go up under interpolation controller, the phase controller of traffic filter back be operated under the frequency of clock CLK II, and the frequency of clock CLK II is half of frequency of clock CLKI.
Go up under be provided with logic module between traffic filter and the interpolation controller, it makes the generation signal of clock CLKI can keep one-period to give clock CLK II usefulness more.
The principle of its invention is following: in existing clock data recovery system (see figure 1) circuit was realized, each module all was operated under the unified system clock regardless of complexity.And the present invention adds logic module, has improved the original system scheme, according to the characteristics of signal each module is operated under the different clock frequencies.The output signal of phase detector: UP0, DN0, on the process under generate the logic module that signal UP1, DN1 are sent to the back behind the traffic filter.The basic functional principle of filter is that double detection UP0 (DN0) is high level such as Fig. 2 (a), then exports 1 high level, like Fig. 2 (b); Consider a kind of extreme case, UP0 (DN0) is continuously high level, and like Fig. 2 (c), the output waveform UP1 of filter (DN1) examines its waveform like Fig. 2 (d) in this case, finds its output signal frequency half the for clock rate C LKI just at the soonest.The logic that this shows the back need not be operated under the frequency of CLKI, can be operated in fully under half frequency of CLKI.Through top elaboration; Module interpolation controller and phase controller that system is the most complicated need not be operated under the system-clock rate CLKI fully; But can be operated under the half the frequency of CLKI, making it no longer to become the bottleneck of system speed, the operating rate of system can significantly improve.
A kind of structure of high-frequency clock data recovery system; See Fig. 3, Fig. 4, Fig. 5; It comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Clock CLKI connect respectively under traffic filter and module before thereof, the end of clock CLKI is equipped with the two-divider circuit, two-divider circuit output clock CLK II; The frequency of clock CLK II is frequency half the of clock CLKI; Clock CLK II connect respectively under interpolation controller, phase controller after the traffic filter, go up under be provided with logic module between traffic filter and the interpolation controller, logic module specifically comprises one or gate, two d type flip flops; Two d type flip flop is arranged in order; Wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II, go up under the dateout of traffic filter connect respectively or the input of gate, the input D of first d type flip flop, the output Q of first d type flip flop connects or another output of gate; Or the output of gate connects the input D of second d type flip flop, the input of the output Q connection interpolation controller of second d type flip flop.
The two-divider circuit comprises a d type flip flop, and clock CLKI connects the input end of clock CLK of d type flip flop, and D end, the QB end of d type flip flop are interconnected, d type flip flop output Q output clock CLK II.
The operation principle of logic module is following: the clock of first d type flip flop is CLKI; Second d type flip flop clock is CLKII; The frequency of CLKII is the half the of CLKI; First d type flip flop with or the effect of gate be the signal Data In that makes the generation signal of high-frequency clock such as Fig. 4 (b), can keep one-period, like the signal Data OR of Fig. 4 (d) more; With half rate clock CLKII resampling, like Fig. 4 (e) signal Data Out, the module that supplies the back to be operated in half rate clock CLKII is used signal Data OR for second d type flip flop, we can say the logic that increases newly be before and after the interface of two kinds of operating frequencies.The module of front is operated under the clock CLKI, and the logic working of back is under clock CLKII.
Claims (4)
1. high-frequency clock data recovery system implementation method; It comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Said go up under traffic filter and module before thereof be operated under the frequency of clock CLKI; It is characterized in that: said go up under interpolation controller, the phase controller of traffic filter back be operated under the frequency of clock CLK II, and the frequency of clock CLK II is half of frequency of clock CLKI.
2. a kind of high-frequency clock data recovery system implementation method according to claim 1; It is characterized in that: said go up under be provided with logic module between traffic filter and the said interpolation controller, it makes the generation signal of clock CLKI can keep one-period to give clock CLK II usefulness more.
3. the structure of a high-frequency clock data recovery system; It comprises phase detector, go up under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop; Clock CLKI connect respectively under traffic filter and module before thereof; It is characterized in that: the end of clock CLKI is equipped with the two-divider circuit; Said two-divider circuit output clock CLK II, the frequency of clock CLK II are frequency half the of clock CLKI, clock CLK II connect respectively said go up under said interpolation controller, phase controller after the traffic filter; Said go up under be provided with logic module between traffic filter and the said interpolation controller; Said logic module specifically comprises one or gate, two d type flip flops, and two described d type flip flops are arranged in order, and wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II; Said go up under the dateout of traffic filter connect respectively or the input of gate, the input D of first d type flip flop; The output Q of first d type flip flop connects another output of said or gate, and output said or gate connects the input D of second d type flip flop, and the output Q of second d type flip flop connects the input of said interpolation controller.
4. the structure of a kind of high-frequency clock data recovery system according to claim 3; It is characterized in that: said two-divider circuit comprises a d type flip flop; Clock CLKI connects the input end of clock CLK of said d type flip flop; The D of said d type flip flop end, QB end are interconnected, said d type flip flop output Q output clock CLK II.
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Cited By (5)
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| CN102946306A (en) * | 2012-11-23 | 2013-02-27 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitization clock data recovery method |
| CN103259537A (en) * | 2013-04-12 | 2013-08-21 | 南京邮电大学 | Clock data recovery circuit based on phase selection interpolation type |
| CN105680831A (en) * | 2014-12-05 | 2016-06-15 | 爱思开海力士有限公司 | Clock and data recovery circuit and system using same |
| CN106656174A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | High-speed clock data recovery circuit of novel structure |
| CN106844253A (en) * | 2016-12-15 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2661328C1 (en) * | 2017-09-12 | 2018-07-13 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
| RU2665241C1 (en) * | 2017-10-13 | 2018-08-28 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
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| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
| US20110064176A1 (en) * | 2009-09-14 | 2011-03-17 | Kabushiki Kaisha Toshiba | Clock recovery circuit and data recovery circuit |
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| CN101505149A (en) * | 2008-02-08 | 2009-08-12 | 恩益禧电子股份有限公司 | Local signal generation circuit |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102946306A (en) * | 2012-11-23 | 2013-02-27 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitization clock data recovery method |
| CN102946306B (en) * | 2012-11-23 | 2016-03-02 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitlization clock and data recovery method |
| CN103259537A (en) * | 2013-04-12 | 2013-08-21 | 南京邮电大学 | Clock data recovery circuit based on phase selection interpolation type |
| CN103259537B (en) * | 2013-04-12 | 2016-01-06 | 南京邮电大学 | A kind of based on phase selection interpolation type clock data recovery circuit |
| CN105680831A (en) * | 2014-12-05 | 2016-06-15 | 爱思开海力士有限公司 | Clock and data recovery circuit and system using same |
| CN105680831B (en) * | 2014-12-05 | 2020-08-14 | 爱思开海力士有限公司 | Clock and data recovery circuit and system using the same |
| CN106656174A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | High-speed clock data recovery circuit of novel structure |
| CN106844253A (en) * | 2016-12-15 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
| CN106844253B (en) * | 2016-12-15 | 2019-07-23 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
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| CN102751984B (en) | 2015-04-22 |
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Denomination of invention: High-speed clock data recovery system realization method and structure using same Effective date of registration: 20180207 Granted publication date: 20150422 Pledgee: Agricultural Bank of China Limited by Share Ltd. Wuxi science and Technology Branch Pledgor: SteadiChips Inc. Registration number: 2018990000133 |
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Date of cancellation: 20220929 Granted publication date: 20150422 Pledgee: Agricultural Bank of China Limited by Share Ltd. Wuxi science and Technology Branch Pledgor: STEADICHIPS Inc. Registration number: 2018990000133 |
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Effective date of registration: 20221219 Address after: No. 295, Building 17, No. 2723, Fuchunwan Avenue, Chunjiang Street, Fuyang District, Hangzhou, Zhejiang, 310000 Patentee after: Hangzhou Sitai Microelectronics Co.,Ltd. Address before: No. 16, Changjiang Road, New District, Wuxi City, Jiangsu Province, 214028 Patentee before: STEADICHIPS Inc. |