RU2661328C1 - Frequency tuning method and phase detector - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention relates to the radio engineering. For this, a frequency tuning method is provided, in which at the phase detector (PD) output pulses are generated, which filter and control the oscillator frequency, after the reference signal (RS) front appearance in the first half period, generating the pulse front, and in the absence of it is at the period second half beginning, with the RS front appearance in the period first three quarters, at the period fourth quarter beginning generating the pulse slice, and with the RS front appearance in the period fourth quarter, the slice is generated in the cycles next period. PD contains three D-flip-flops.

EFFECT: elimination of the “arbitrage” influence in the retention zone, as well as the ability to work with the different duty cycles RS, which period is a multiple of the cycles period, and frequency tuning by the received data fronts.

7 cl, 10 dwg

Description

The invention relates to radio engineering.

There is a known method of frequency adjustment [1], in which a pulse is generated at the first output of the phase detector along the front of the reference signal, a pulse is generated at the second output of the phase detector at the clock front, and after the appearance of both pulses, pulse slices are formed at both outputs of the phase detector, pulses at the first and the second outputs of the phase detector are converted respectively into signals of positive and negative polarity, which are then added, filtered and controlled by the frequency of the generator, the frequency of the generator is divided and formed so you. The method has a search and hold zone from 0 ° to 360 °.

The method [1] has the following disadvantages:

• in the hold mode, it works only with signals of equal frequencies (cannot adjust clock cycles according to received data);

• its implementation requires a current converter, which is not in digital FPGAs;

A known method of frequency adjustment [2], in which the reference and clock signals are multiplied, the received signal is filtered and the frequency of the generator is controlled, the frequency of the generator is divided and clock cycles are formed. For logical signals, the multiplier function is performed by the exclusive OR logic element (see, for example, the description of phase detector 1 of the CD 4046 chip RCA or its analogs: HEF 4046B, CDD 4046B, or K564GP [3]).

The method [2] is characterized by a simple phase detector, but has the following disadvantages:

• duty cycle of pulsed signals should be close to 2;

• works only at equal and multiple frequencies;

• cannot adjust the clock frequency on the edges of the data when receiving discrete signals;

• tuning takes place along the edges and cuts of pulses, which reduces accuracy and increases phase noise, because in reality, duty cycle always differs from 2;

• the search (hold) region is from 0 ° to 180 ° (in the zone from 180 ° to 360 ° the duty cycle of the output signal of the multiplier and the tuning sign are inverted, which increases the search time, and in the hold mode the phase difference moves away from the nominal 90 ° beyond the boundaries of the region 0 ÷ 180 ° will lead to loss of capture and a new search).

Known phase detector [1], containing contains two D-flip-flops, two logical elements And, two buffers. Comparison of any pair of edges of the reference and clock signals in the phase detector [1] leads to “arbitration” at the moment of reset of D-flip-flops. In “arbitration”, an unstable transition process, an increase in switching time during front formation, an oscillation anomaly, or a metastable anomaly are possible [4], which leads to an increase in phase noise and a decrease in speed.

Known logical element "exclusive OR" [3], which performs the function of a phase detector of pulsed signals - a multiplier in the method [2]. Its advantages and disadvantages are determined by the method of frequency adjustment [2] and have been described above.

The closest (prototype) is a phase detector [5], which contains three D-flip-flops and four logical elements I. This device can operate at multiple frequencies, which allows you to use it to adjust the clock frequency on the edges of the data when receiving discrete signals. The phase detector has the following disadvantages:

• Designed for collaboration with a bipolar current driver, which is not available in digital FPGAs;

• when the reference signal front appears in the vicinity of the clock front, “arbitration” appears [4]. The width of the dangerous time interval is less than the switching time of the D-trigger, but it is located in the center of the holding area. Possible vibrational or metastable anomalies [4] increase phase noise and reduce performance.

Closest to the proposed are the method [2] and phase detector [5] (prototypes).

The purpose of the invention (technical result) is to increase functional reliability (elimination of "arbitration" in the holding zone) and expanding the functionality of the frequency adjustment method, in part:

• expanding the search and retention area;

• ensuring operation with an arbitrary frequency ratio of the reference signal to clock cycles, the possibility of changing this frequency, the variable duty cycle of the reference signal during operation (the ability to adjust the frequency of clock cycles on the data fronts when receiving discrete signals);

• improving accuracy and reducing phase noise due to the transition from tuning along the edges and cuts to tuning along the edges.

The technical result is achieved by the fact that:

1) in the frequency adjustment method, in which pulses are generated at the output of the phase detector, which are filtered, and the generator frequency is controlled by the generated signal, the generator frequency is divided and clock signals are generated for the phase detector, while after the appearance of the clock signal front edges in the first half of the period, they form the pulse front at the output of the phase detector, and in the absence of a reference signal front in the first half of the cycle period, the pulse front at the output of the phase detector is formed at the beginning of the second half of the period acts, with the appearance of the front of the reference signal in the first three quarters of the period of clock cycles slice pulse at the output of the phase detector is formed in the beginning of the fourth quarter of the period of clock cycles and when a reference edge in the fourth quarter cycle clocks pulse slice at the output of the phase detector is formed in the next period cycles.

2) when the front of the reference signal appears in the fourth quarter of the cycle period, a pulse slice at the output of the phase detector is formed at the beginning of the second quarter of the period of the next cycle period

3) the generator frequency is divided in two stages, while in the second stage, the 4-fold clock frequency is divided 4 times to the clock frequency, and pulses of 4 times the clock frequency and several signals from the outputs of the second divider are used in the phase detector.

4) in the phase detector, two OR elements and a logic converter are additionally introduced, the reference frequency input is connected to the D-input of the first D-trigger, the output of which is connected to the D-input of the second D-trigger, the output of the first AND element is connected to the first input of the first element OR and with the D-input of the third D-trigger, the first output of which is connected to the first input of the second OR element, the output of which is connected to the CE-input of the third D-trigger, the output of the second AND element is connected to another input of the first OR element, the output of the second OR element connected to you during the phase detector, the three outputs of the logic converter are connected in pairs, respectively, with the CE input of the first D-trigger and other inputs of the second AND and OR elements, the inputs of the logic converter are connected in pairs, respectively, with the additional clock inputs of the phase detector.

The group of inventions is related by a common concept and satisfies the requirement of unity of invention, because a phase detector is part of a device for implementing the proposed method. When analyzing the level of technology and novelty of the claimed objects, no analogues were found with the above set of the above features. Therefore, the described technical solution meets the criterion of "novelty."

The proposed method is presented in figure 1 ÷ 4. Timing diagrams of FIG. 2, 3 and 4 are plotted for the edges of the reference signal appearing in the first half, in the third and fourth quarters of the clock period, respectively. In FIG. 5 shows a diagram of a phase detector with a logical converter of the reflex code (Liebau-Craig code) according to 4 and 5 of the claims. In FIG. Figures 6 and 7 show the logical converters of the unitary and binary codes, respectively. In FIG. 8, 9 and 10 are time diagrams of the phase detector operation (Fig. 5) at different phases of the fronts of the reference frequency.

In FIG. 1 shows a frequency adjustment method in which Q pulses are generated at the output of phase detector 1 and filtered 2, and the frequency of oscillator 3 is controlled by the received signal U. The frequency of oscillator 3 is divided by 4 and clock signals T are generated for phase detector 1.

At the second stage of frequency division 42, the 4-fold clock frequency 4f is divided 4 times to the clock frequency. The phase detector uses a 4-fold clock frequency 4f and several clock signals from the outputs of the divider 42. When filtering 2 unipolar pulses from the output of the phase detector, the DC component level should be shifted down the input half the logic level of the Q signal (for CMOS circuits, by half supply voltage), the allocation of the constant component of the "shifted" signal Q and the shift of the signal U to the center of the working area of the frequency control of the generator 3. In the working area of the generator 3, the filtering should be linear: the equality of the growth and decay rates of voltage U and their independence from the values of U. It is possible to use digital filtering.

In the time diagrams, the abstract signal is a clock signal T, representing several signals from the outputs of the divider 42, conditionally depicted as a pulse in the fourth quarter of the cycle period, the polarity of the signals Q and U correspond to an increase in the frequency of generator 3 with increasing voltage U and the following notation is used:

1/4, 2/4, 3, / 4 and 4/4 - part of the period of measures;

Uo is the voltage value U at the end of the adjustment. In FIG. 2 shows that:

• after the front of the reference signal Fo appears in the first half of the period, a pulse front is formed at the output Q of the phase detector (the first four fronts Q);

• in the absence of a reference signal front in the first half of the cycle period, the pulse front at the output of the phase detector Q is formed at the beginning of the second half of the cycle period, and the pulse slice is formed at the end of the period (fifth front Q);

• when the front of the reference signal Fo appears in the first two quarters of the cycle period, a pulse slice at the output of the phase detector Q is formed at the beginning of the fourth quarter of the cycle period (the first four edges Q).

FIG. 3 illustrates the operation when the front of the reference signal F ₀ appears in the third quarter of the cycle period, (signal fronts F ₀ 1 ÷ 3) In the first half of these periods, there are no fronts F ₀ and at the beginning of the second half they form pulse fronts at the output of the phase detector Q, and slices pulses form at the beginning of the fourth quarter of the periods of cycles. In the clock period, when the edge of the signal F ₀ appears in the third quarter of the period, the duty cycle of the pulse Q is 4. The average duty cycle of Q will be more than 2, the voltage U and the frequency of the generator 3 decrease, therefore, after several periods, the edge of the signal F ₀ goes into the second quarter of the period ( last edge of the signal F ₀ ).

FIG. 4 illustrates the operation for the front of the reference signal F ₀ in the fourth quarter of the cycle period. In the first half of the cycle period, there is no front F ₀ , and at the beginning of the second half of the cycle period, a pulse front is formed at the output of the phase detector Q, and its signal slice is formed at the beginning of the second quarter the next period of ticks (according to claim 2 of the claims). In the clock period in which the signal front F ₀ appears, the pulse duty cycle Q is 4/3. The average duty cycle Q will be less than 2, the voltage U and the frequency of the generator 3 increase, therefore, after several periods of clock cycles, the signal front F ₀ goes into the first quarter of the next period (the last edge of the signal F ₀ in the diagram).

In FIG. 5 is a diagram of a phase detector containing three D-flip-flops 101, 102 and 103 and two elements And 111 and 112, a clock input 4f is connected to the C-inputs of three D-flip-flops, the second outputs of the second and third D-flip-flops 102 and 103 are connected in pairs respectively, with the first inputs of the first and second elements And 111 and 112, the D-input of the first D-flip-flop 101 is connected to another input of the first element And 111, the phase detector contains two elements OR 121, 122 and a logic converter 13, the reference frequency input 4Fo connected to D-input of the first D-flip-flop 101, the output of which is connected to the D-input of the WTO of the D-flip-flop 102, the output of the first AND 111 element is connected to the first input of the second OR element 122 and to the D-input of the third D-flip-flop 103, the first output of which is connected to the first input of the second OR element 122, the output of which is connected to the CE input of the third D-flip-flop 103, the output of the second element AND 112 is connected to the second input of the second element OR 122, the output of the second element OR 122 is connected to the output of the phase detector Q, the three outputs of the logic converter Y1, Y2 and Y3 are connected in pairs with the CE input of the first D- trigger 101, the second input of the first element nt OR 121 and the second input of the second element And 112, the inputs of the logical Converter 13 are connected in pairs, respectively, with additional clock inputs of the phase detector T1 and T2.

The logical converter 13 is designed as a logical converter of the reflex code 131, which contains the logical elements OR 123 and AND 113, the three outputs of the logical converter 131 Y1, Y2 and Y3 are connected in pairs with the output of the OR element 123, the output of the element AND 113 and the second input of the reflex code converter T2, the first and second inputs of the logical converter of the reflex code 131 are connected in pairs with the first and second inputs of the elements OR 123 and AND 113, respectively.

In FIG. 5 also shows the well-known counter circuit in reflex code 42 on two D-flip-flops 421 and 422 (see, for example, [6, 7]).

In FIG. 6 shows a logic converter of a unitary code 132, which contains an OR gate 124 and an inverter 141, three outputs of a logic converter of a unitary code 132 Y1, Y2 and Y3 are connected in pairs with the output of the inverter 141, the second input of the unitary code converter 132, and the output of the OR element 124, the inputs of which are connected in pairs with the second and third inputs of the unit logic code 132, the first input of which is connected to the input of the inverter 141. In FIG. 6 also shows the connections of the inputs of the phase detector T1, T2, TK with the logic converter 13 and the outputs of the 4-bit unitary encoded 42 with the inputs of the phase detector T1, T2, TK. Note that here the second output of the counter 42 is not used. The sequence of states {1000, 0100, 0010, 0001} is used (see, for example, [6,7]).

In FIG. 7 shows the logic converter of the binary weighted code 133, which contains the logical elements OR 125 and AND 114, and the first input of the element AND 114 is inverse, the three outputs of the logical converter of the binary code 133 Y1, Y2 and Y3 are connected in pairs with the output of the element OR 125, the output of the element And 114 and the second input of the binary code converter 133 and the output of the AND element 114, the first and second inputs of the logical binary code converter 133 are connected in pairs with the first and second inputs of the OR elements 125 and And 114, respectively. In FIG. 7 also shows the connections of the inputs of the phase detector T1, T2, TK with the logic converter 132 and the outputs of the 2-bit binary counter 42. The sequence of states: 00, 01, 01 and 11 (see, for example, [6]).

In FIG. Figure 8 shows the timing diagram of the phase detector (Fig. 5) when the Fo front appears in the first quarter of the cycle period (1st and 2nd periods) and in the center of the holding zone at the boundary of the first and second quarters (5th period). The first D-trigger 101 does not switch at the beginning of the second quarter of the cycle period. The second D-flip-flop 102 can switch in any quarter of the period. The third D-flip-flop 103 can switch to log. 1 only at the beginning of the fourth quarter of the cycle period, and - at 0 in any quarter of the period. When the front Fo appears in the first quarter of the cycle period, a pulse with linear pulse width modulation (PWM) duration is formed at the output of the phase detector Q in the range from 1/2 to 4/3 of the cycle period, while the pulse duty cycle Q (the ratio of the cycle period to duration pulse) lies in the range from 4/3 to 2 (in Fig. 8 - 8/5). This corresponds to an increase in voltage U and generator frequency 3. In other periods, the duty cycle is 2.

Functional reliability (no arbitration) in the hold mode is ensured by the fact that the first D-trigger 101 does not switch in the center of the hold zone (at the end of the first quarter of the measure period).

In FIG. Figure 9 shows the time diagram of the phase detector when the fronts of the reference frequency Fo appear: in the fourth quarter of the period (1st and 2nd periods), in the second quarter of the period (3rd and 4th period) and on the border of the first and second quarters period (5th period). In the following periods after the appearance of the fronts of the reference frequency Fo in the fourth quarter of the period of the cycle periods, the duty cycle of the signal Q is 4/3 (in the 2nd and 3rd in Fig. 9). This corresponds to the correct increase in the frequency of the generator 3 in the zone 270 ° ÷ 360 °.

For the front Fo received in the second quarter of the period, the phase detector operates linearly with the PWM and the duty cycle Q is limited to the interval from 2 to 4 (in Fig. 9-8/3). This corresponds to a decrease in the voltage U and the frequency of the generator 3.

In other periods, the signal duty cycle Q is 2.

The appearance of the front of the reference frequency Fo at the boundary of the first and second quarters of the period (5th period of Fig. 9) corresponds to the absence of a phase error.

In FIG. 10 shows the time diagram of the phase detector when the fronts of the reference frequency Fo appear in the third quarter of the period (1st and 2nd periods). In the first two periods of cycles, the signal front Y3 at the beginning of the third quarter is ahead of the front Fo and a pulse is generated in the fourth quarter of the period at the output of the third D-trigger Q3. At the output Q, a pulse is formed in the third quarter of the period. In the first two periods of cycles, the duty cycle of the signal Q is 4, which corresponds to a decrease in the voltage U and the frequency of the generator 3. In other periods, the duty cycle of the signal Q is 2.

Phase detectors with other options for constructing a logic converter (Fig. 6 and 7) work similarly

Thus, the method according to the proposal can work with a reference signal of different duty cycle, for any multiplicity of the period of the reference signal to clock cycles and for changes in the frequency ratio and duty cycle during operation, adjust the clock frequency on the data fronts, and the phase detector is not subject to “arbitration” in the hold zone .

Information sources

1. Patent US 5892380, CL 337/172, 04/06/1999.

2. Greben A.V. Design of analog integrated circuits, Per. from English - M.: Energy 1976, 266 s, p. 196 images 9-17.

3. Shilo V.L. Popular Digital Chips: A Guide. - M.: Metallurgy 1988, 352 s, p. 279 p. 2.73 a, p., 282 fig. 2.75 a, b.

4. Automated control of asynchronous processes in computers and discrete systems / Ed. IN AND. Warsaw. - M.: Science, Ch. ed. Fizmat, lit., 1986. 400 s, p. 284-294 § 9.1-9.3, p. 310 § 9.6.

5. RF patent 2622628, IPC H03D 13/00, 08/08/2016 (Fig. 3 and 4).

6. Trachik V. Discrete automation devices: TRANS. from Polish .; Ed. YES. Pospelova. - M .: Energy, 1978 - 456 s, p. 325 p. 5 - 37 a and 6, p. 328 fig. 5 - 39 a and 6, p. 329 fig. 5-41 a and 6.

7. Design of microelectronic digital devices / Ed. S.A. Mayorova - M .: Sov. radio, 1977, 272 p. 175 p. 5-18 a and 6, p. 182 fig. 5-22.

Claims (7)

1. A frequency adjustment method, in which pulses are generated at the output of the phase detector and filtered, and the generator frequency is controlled by the received signal, the generator frequency is divided and clock signals are generated for the phase detector, while after the appearance of the clock signal front edges in the first half of the period, they form a front a pulse at the output of the phase detector, characterized in that in the absence of a reference signal front in the first half of the cycle period, a pulse front at the output of the phase detector is formed at the beginning of the second halves of the cycle period, when the front of the reference signal appears in the first three quarters of the cycle period, the pulse cut at the output of the phase detector is formed at the beginning of the fourth quarter of the cycle period, and when the front of the reference signal appears in the fourth quarter of the cycle period, the pulse cut at the output of the phase detector is formed in the next period beats. 2. The method according to p. 1, characterized in that when the front of the reference signal appears in the fourth quarter of the cycle period, a pulse cut at the output of the phase detector is formed at the beginning of the second quarter of the period of the next cycle period. 3. The method according to p. 1, characterized in that the generator frequency is divided in two stages, at the last stage, the 4-fold clock frequency is divided 4 times to the clock frequency, and in the phase detector, pulses of 4-fold clock frequency and several signals with outputs of the second divider. 4. Phase detector containing three D-flip-flops and two And elements, the clock input is connected to the C-inputs of three D-flip-flops, the second outputs of the second and third D-flip-flops are connected in pairs with the first inputs of the first and second elements And, D-input the first D-trigger is connected to the second input of the first AND element, characterized in that the phase detector contains two OR elements and a logic converter, the reference frequency input is connected to the D-input of the first D-trigger, the output of which is connected to the D-input of the second D-trigger , output of the first element AND connected to the first input of the first OR element and to the D-input of the third D-trigger, the first output of which is connected to the first input of the second OR element, the output of which is connected to the CE-input of the third D-trigger, the output of the second AND element is connected to the second input of the second element OR, the output of the second element OR is connected to the output of the phase detector, the three outputs of the logic converter are connected in pairs with the CE-input of the first D-trigger, the second input of the first OR, and the second input of the second element AND, the inputs of the logic converter zovatelya connected in pairs respectively with the additional clock inputs of the phase detector. 5. The phase detector according to claim 4, characterized in that the logic converter of the reflex code is used, which contains the logical elements OR and AND, the three outputs of the logical converter are connected in pairs with the output of the OR element, the output of the AND element, and the second input of the reflex code converter, the first and the second inputs of the logic converter of the reflex code are connected in pairs, respectively, with the first and second inputs of the elements OR and I. 6. The phase detector according to claim 4, characterized in that the unitary code logic converter is used, which contains the OR logic element and the inverter, the three outputs of the unitary code logic converter are connected in pairs respectively with the inverter output, the second input of the unitary code converter and the output of the OR element, the inputs of which are connected in pairs, respectively, with the second and third inputs of the logical converter of the unitary code, the first input of which is connected to the input of the inverter. 7. The phase detector according to claim 4, characterized in that the binary logic converter is used, which contains the logical elements OR and AND, and the first input of the AND element is inverse, the three outputs of the binary logic converter are connected in pairs, respectively, with the output of the OR element, the output of the element And with the second input of the binary code converter, the first and second inputs of the logical binary code converter are connected in pairs with the first and second inputs of the elements OR and I.

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