CN102751984B - High-speed clock data recovery system realization method and structure using same - Google Patents
High-speed clock data recovery system realization method and structure using same Download PDFInfo
- Publication number
- CN102751984B CN102751984B CN201210220497.9A CN201210220497A CN102751984B CN 102751984 B CN102751984 B CN 102751984B CN 201210220497 A CN201210220497 A CN 201210220497A CN 102751984 B CN102751984 B CN 102751984B
- Authority
- CN
- China
- Prior art keywords
- clock
- phase
- type flip
- flip flop
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention provides a high-speed clock data recovery system realization method. According to the method, the operating frequency of an interpolation controller and the operating frequency of a phase controller is reduced under a condition that modules work under different clock frequencies according to signal characteristics, and thus the burden is greatly lightened, and the operating frequency of a whole system is improved. The structure comprises a phase position detector, an upper/lower signal filter, the interpolation controller, the phase controller, a phase selector, a phase position interpolator and a phase-locked loop, wherein the upper/lower signal filter and the other modules in head of the upper/lower signal filter work under a frequency of a clock CLKI; and the structure is characterized in that the interpolation controller and the phase controller which are arranged behind the upper/lower signal filter operate work under a frequency of a clock CLK II, and the frequency of the clock CLK II is one half of the frequency of the clock CLK I.
Description
Technical field
The present invention relates to the technical field of high-frequency clock date restoring, be specially a kind of high-frequency clock data recovery system realization method, present invention also offers the structure using the method.
Background technology
Society amount of information expands and breaks out, and the dysfunction of message handler is powerful, and the information transfer efficiency of point-to-point transmission becomes bottleneck, and in order to make transmission system at a high speed, simply, effectively, transmitting terminal of being everlasting becomes signal into serial, by carrier as optical fiber transmits.Owing to there is various interference in transmission, signal distorts, and the clock data recovery system of receiving terminal then will be responsible for the serial data received to carry out clock and data recovery, therefrom extracts clock and data.In order to higher data transmission efficiency, then require higher transmission rate, under namely clock data recovery system is operated in higher clock frequency, as several GHz.CMOS technology development is advanced by leaps and bounds, and with the price that it is cheap, low-power consumption, high integration becomes current most important chip production process.Various clock data recovery system products based on CMOS technology emerge in an endless stream.
Traditional clock data recovery system as shown in Figure 1.This system by phase detector, upper under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator and phase-locked loop form.Because data there occurs distortion in the process of transmission, the task of system is the serial data that transmitting terminal is launched, and processes, therefrom recovers clock, data, for receiving terminal, under whole system is operated in unified clock CLKI.In system, the logic of interpolation controller and phase controller is the most complicated, and the time of signal transacting is the longest, so the operating rate of these two modules determines the operating rate of system, also determines the efficiency of transmission, becomes the bottleneck of system speed.In order to make system works under higher clock rate, then under will trying every possible means to make these two modules can be operated in higher speed.
At present in order to solve above-mentioned contradiction, the method that main employing is following:
1) more improvement of production process is adopted, with less process device, thus under making the logical circuit of each module can be operated in higher clock rate.Thus improve the speed of transmission.But more advanced production technology expense is more expensive.
2) more complicated framework is improved, as half rate clock architecture, 1/4th rate frameworks.Framework is more complicated, and realize more difficult, cost is higher.
3) adopt special process, as ambipolar, GeSi technique etc., operating speed is process devices faster.Special production technology expense is more expensive.
4) multichannel transmission, increases transmission quantity.But multichannel makes the cost of transmission higher.
Summary of the invention
For the problems referred to above, the invention provides a kind of high-frequency clock data recovery system realization method, it makes each module work at different clock frequencies according to the feature of signal, make interpolation controller, the operating frequency of phase controller reduces, significantly reduce burden, thus the operating frequency of whole system can be improved.
A kind of high-frequency clock data recovery system realization method, its technical scheme is such: it comprise phase detector, upper under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop, described upper under traffic filter and module work before thereof under the frequency of clock CLKI, it is characterized in that: described upper under under traffic filter interpolation controller below, phase controller be operated in the frequency of clock CLK II, and the frequency of clock CLK II is the half of the frequency of clock CLKI.
It is further characterized in that: described upper under be provided with logic module between traffic filter and described interpolation controller, it makes the generation signal of clock CLKI that one-period can be kept to clock CLK II use more.
A kind of structure of high-frequency clock data recovery system, its technical scheme is such: it comprises phase detector, upper under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop, clock CLKI connect respectively under traffic filter and module before thereof, it is characterized in that: one end of clock CLKI is provided with two-divider circuit, described two-divider circuit output clock CLK II, the frequency of clock CLK II is the half of the frequency of clock CLKI, clock CLK II connect respectively described upper under described interpolation controller after traffic filter, phase controller, described upper under be provided with logic module between traffic filter and described interpolation controller, described logic module specifically comprises one or gate, two d type flip flops, d type flip flop described in two arranges in turn, wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II, described upper under the output data of traffic filter connect respectively or the input of gate, the input D of first d type flip flop, the output Q of first d type flip flop connects another output that is described or gate, output that is described or gate connects the input D of second d type flip flop, the output Q of second d type flip flop connects the input of described interpolation controller.
It is further characterized in that: described two-divider circuit comprises a d type flip flop, and clock CLKI connects the input end of clock CLK of described d type flip flop, and the D of described d type flip flop end, QB end are interconnected, described d type flip flop output Q output clock CLK II.
After adopting the present invention, upper under under traffic filter interpolation controller below, phase controller be operated in the frequency of clock CLK II, and the frequency of clock CLK II is the half of the frequency of clock CLKI, make full use of the feature of each module, make each module work under different clock rates, make interpolation controller, the operating frequency of phase controller reduces, significantly reduce burden, thus the operating frequency of whole system can be improved; And then make clock data recovery system under identical production technology, higher transmission rate can be operated in, improve the efficiency of transmission.
Accompanying drawing explanation
Fig. 1 is existing clock data recovery system block schematic illustration;
Fig. 2 be upper under traffic filter input-output wave shape schematic diagram;
Fig. 3 is block schematic illustration of the present invention;
Fig. 4 is logic module circuit figure of the present invention and oscillogram;
Fig. 5 is frequency-halving circuit of the present invention and oscillogram.
Embodiment
A kind of high-frequency clock data recovery system realization method, see Fig. 3, it comprise phase detector, upper under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop, upper under traffic filter and module work before thereof under the frequency of clock CLKI, it is characterized in that: upper under under traffic filter interpolation controller below, phase controller be operated in the frequency of clock CLK II, and the frequency of clock CLK II is the half of the frequency of clock CLKI.
Upper under be provided with logic module between traffic filter and interpolation controller, it makes the generation signal of clock CLKI that one-period can be kept to clock CLK II use more.
Its invention principle as follows: in existing clock data recovery system (see figure 1) circuit realiration, each module regardless of complexity, under being all operated in unified system clock.And the present invention adds logic module, improve original system scheme, make each module work at different clock frequencies according to the feature of signal.The output signal of phase detector: UP0, DN0, through upper under generate signal UP1, DN1 after traffic filter and be sent to logic module below.The basic functional principle of filter be double detection UP0 (DN0) for high level is as Fig. 2 (a), then export 1 high level, as Fig. 2 (b); Consider the most extreme case of one, UP0 (DN0) is continuously high level, as Fig. 2 (c), in this case the output waveform UP1 (DN1) of filter is as Fig. 2 (d), examine its waveform, find that its output signal frequency is just the half of clock rate C LKI at the soonest.Under logic below need not be operated in the frequency of CLKI as can be seen here, under the half frequency of CLKI can be operated in completely.By setting forth above, under the module interpolation controller that system is the most complicated and phase controller need not be operated in system-clock rate CLKI completely, but under the frequency of CLKI half can be operated in, making it the bottleneck no longer becoming system speed, the operating rate of system can significantly improve.
A kind of structure of high-frequency clock data recovery system, see Fig. 3, Fig. 4, Fig. 5, it comprises phase detector, upper under traffic filter, interpolation controller, phase controller, phase selector, phase interpolator, phase-locked loop, clock CLKI connect respectively under traffic filter and module before thereof, one end of clock CLKI is provided with two-divider circuit, two-divider circuit output clock CLK II, the frequency of clock CLK II is the half of the frequency of clock CLKI, clock CLK II connect respectively under interpolation controller after traffic filter, phase controller, upper under be provided with logic module between traffic filter and interpolation controller, logic module specifically comprises one or gate, two d type flip flops, the d type flip flop of two arranges in turn, wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II, upper under the output data of traffic filter connect respectively or the input of gate, the input D of first d type flip flop, the output Q connection of first d type flip flop or another output of gate, or the output of gate connects the input D of second d type flip flop, the output Q of second d type flip flop connects the input of interpolation controller.
Two-divider circuit comprises a d type flip flop, and clock CLKI connects the input end of clock CLK of d type flip flop, and D end, the QB end of d type flip flop are interconnected, d type flip flop output Q output clock CLK II.
The operation principle of logic module is as follows: the clock of first d type flip flop is CLKI, second d type flip flop clock is CLKII, the frequency of CLKII is the half of CLKI, first d type flip flop and or the effect of gate be make the generation signal of high-frequency clock as the signal Data In of Fig. 4 (b), one-period can be kept, as the signal Data OR of Fig. 4 (d) more; Second d type flip flop is signal Data OR half rate clock CLKII resampling, as Fig. 4 (e) signal Data Out, for the module being operated in half rate clock CLKII below, the logic newly increased is the interface of front latter two operating frequency.Module work is above under clock CLKI, and logic working is below under clock CLKII.
Claims (2)
1. a high-frequency clock data recovery system, it comprises phase detector, described phase detector be connected with in turn under traffic filter and interpolation controller, described interpolation controller is connected to phase interpolator and phase controller, described phase controller is connected with phase selector, described phase selector is connected with phase interpolator, it also comprises phase-locked loop, described phase-locked loop is connected with described phase selector, clock CLKI connect respectively under traffic filter and module before thereof, it is characterized in that: one end of clock CLKI is provided with two-divider circuit, described two-divider circuit output clock CLK II, the frequency of clock CLK II is the half of the frequency of clock CLKI, clock CLK II connect respectively described upper under described interpolation controller after traffic filter, phase controller, described upper under be provided with logic module between traffic filter and described interpolation controller, described logic module specifically comprises one or gate, two d type flip flops, d type flip flop described in two arranges in turn, wherein first d type flip flop connects clock CLKI, second d type flip flop connects clock CLK II, described upper under the output data of traffic filter connect respectively or the input of gate, the input D of first d type flip flop, the output Q of first d type flip flop connects another output that is described or gate, output that is described or gate connects the input D of second d type flip flop, the output Q of second d type flip flop connects the input of described interpolation controller.
2. a kind of high-frequency clock data recovery system according to claim 1, it is characterized in that: described two-divider circuit comprises a d type flip flop, clock CLKI connects the input end of clock CLK of described d type flip flop, D end, the QB end of described d type flip flop are interconnected, the output Q output clock CLK II of described d type flip flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210220497.9A CN102751984B (en) | 2012-06-29 | 2012-06-29 | High-speed clock data recovery system realization method and structure using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210220497.9A CN102751984B (en) | 2012-06-29 | 2012-06-29 | High-speed clock data recovery system realization method and structure using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102751984A CN102751984A (en) | 2012-10-24 |
| CN102751984B true CN102751984B (en) | 2015-04-22 |
Family
ID=47031917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210220497.9A Active CN102751984B (en) | 2012-06-29 | 2012-06-29 | High-speed clock data recovery system realization method and structure using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102751984B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844253A (en) * | 2016-12-15 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
| RU2661328C1 (en) * | 2017-09-12 | 2018-07-13 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
| RU2665241C1 (en) * | 2017-10-13 | 2018-08-28 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102946306B (en) * | 2012-11-23 | 2016-03-02 | 中国电子科技集团公司第三十二研究所 | Clock data recovery circuit structure and digitlization clock and data recovery method |
| CN103259537B (en) * | 2013-04-12 | 2016-01-06 | 南京邮电大学 | A kind of based on phase selection interpolation type clock data recovery circuit |
| KR20160069093A (en) * | 2014-12-05 | 2016-06-16 | 에스케이하이닉스 주식회사 | Clock and data recovery circuit and system using the same |
| CN106656174A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | High-speed clock data recovery circuit of novel structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101505149A (en) * | 2008-02-08 | 2009-08-12 | 恩益禧电子股份有限公司 | Local signal generation circuit |
| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5300671B2 (en) * | 2009-09-14 | 2013-09-25 | 株式会社東芝 | Clock recovery circuit and data recovery circuit |
-
2012
- 2012-06-29 CN CN201210220497.9A patent/CN102751984B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101505149A (en) * | 2008-02-08 | 2009-08-12 | 恩益禧电子股份有限公司 | Local signal generation circuit |
| CN101577617A (en) * | 2008-05-08 | 2009-11-11 | 台湾积体电路制造股份有限公司 | Fast locking clock and data recovery |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844253A (en) * | 2016-12-15 | 2017-06-13 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
| CN106844253B (en) * | 2016-12-15 | 2019-07-23 | 北京时代民芯科技有限公司 | A kind of serial communication clock data recovery system of low sampling rate |
| RU2661328C1 (en) * | 2017-09-12 | 2018-07-13 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
| RU2665241C1 (en) * | 2017-10-13 | 2018-08-28 | Геннадий Сендерович Брайловский | Frequency tuning method and phase detector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102751984A (en) | 2012-10-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102751984B (en) | High-speed clock data recovery system realization method and structure using same | |
| CN202713274U (en) | Structure of high speed clock data recovery system | |
| CN101951313B (en) | FPGA-based SFI4.1 device | |
| CN102999467A (en) | High-speed interface and low-speed interface switching circuit and method based on FPGA (Field Programmable Gate Array) | |
| CN103141066A (en) | Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor | |
| CN101729234A (en) | Phase interpolation controller | |
| US10218492B2 (en) | Clock and data recovery for pulse based multi-wire link | |
| CN102340316A (en) | FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer | |
| CN102801414B (en) | For the bang-bang phase discriminator of half rate clock data recovery circuit | |
| CN102707766B (en) | signal synchronization device | |
| CN103197728A (en) | Method for realizing burr-free clock switching circuit in different clock domains as well as circuit | |
| CN102325066A (en) | Compound network card integrated with Gigabit and 10-Gigabit Ethernet | |
| CN102790605B (en) | asynchronous signal synchronizer | |
| CN110059041B (en) | Transmission system | |
| CN103326808A (en) | Method, device and system for data transmission | |
| CN102946306B (en) | Clock data recovery circuit structure and digitlization clock and data recovery method | |
| CN201804327U (en) | Universal serial interface circuit | |
| CN102754407A (en) | Providing a feedback loop in a low latency serial interconnect architecture | |
| CN101572538A (en) | Semiconductor device | |
| CN103684473A (en) | High-speed serial-parallel conversion circuit based on FPGA | |
| CN103412615A (en) | Glitch-free self-adaptive clock switching method for UART (Universal Asynchronous Receiver Transmitter) interface chip | |
| CN112989748A (en) | Integrated circuit capable of reducing wiring quantity | |
| CN113127403A (en) | Semiconductor chip | |
| CN202127418U (en) | Composite network card integrating gigabit Ethernet and ten gigabit Ethernet | |
| CN202662010U (en) | FPGA (Field Programmable Gate Array) interaction device, verification board and SOC (System On Chip) system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: High-speed clock data recovery system realization method and structure using same Effective date of registration: 20180207 Granted publication date: 20150422 Pledgee: Agricultural Bank of China Limited by Share Ltd. Wuxi science and Technology Branch Pledgor: SteadiChips Inc. Registration number: 2018990000133 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20220929 Granted publication date: 20150422 Pledgee: Agricultural Bank of China Limited by Share Ltd. Wuxi science and Technology Branch Pledgor: STEADICHIPS Inc. Registration number: 2018990000133 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221219 Address after: No. 295, Building 17, No. 2723, Fuchunwan Avenue, Chunjiang Street, Fuyang District, Hangzhou, Zhejiang, 310000 Patentee after: Hangzhou Sitai Microelectronics Co.,Ltd. Address before: No. 16, Changjiang Road, New District, Wuxi City, Jiangsu Province, 214028 Patentee before: STEADICHIPS Inc. |
|
| TR01 | Transfer of patent right |