RU2665241C1 - Frequency tuning method and phase detector - Google Patents

Abstract

FIELD: radio engineering and communication.

SUBSTANCE: invention relates to the radio engineering. For this purpose, a frequency tuning method is provided in which the signals at the two outputs of the phase detector (PD) control the connection and disconnection of the two unipolar sources. Then the total signal is filtered and it is controlled by the generator, the first source is connected along the front of the reference signal (RS), the first source is disconnected at the first incoming clock front or RS slice, the second source is connected after the front of the RS on the front of the bars, if it comes before the RS cutoff, the second source is disconnected at the first slice of the cycles.

EFFECT: increase of functional stability (elimination of influence of dangerous controversies) in a mode of deduction.

5 cl, 7 dwg

Description

The invention relates to radio engineering.

There is a known method of frequency adjustment [1], in which the pulses at the first and second outputs of the phase detector are converted respectively into bipolar signals of the same amplitude, these signals are summed, filtered and control the frequency of the generator, the generator frequency is divided and clock cycles are generated, and at the first and second outputs of the phase detectors are generated pulses, respectively, along the front of the reference signal or along the front of the clocks, after the appearance of the last pulse, pulse slices are formed at both outputs of the phase detector.

Known for working according to the method of [1] are phase detectors containing two D-flip-flops and logical elements AND (see, for example, [1, 2]). At any phase shift of the reference frequency and clocks when the D-triggers are reset, dangerous events arise in the phase detector, which in the “slow” trigger can lead to dangerous effects for the method [1]: missed reset, vibrational or metastable anomalies [3].

The method [1] has the following disadvantages:

- in the hold mode it works only with signals of equal frequencies and cannot adjust clock cycles along the edges of the received data;

- at any phase shift of the reference frequency and clocks, dangerous contests appear.

A known method of frequency adjustment [4], in which the pulses at the first and second outputs of the phase detector are converted respectively into different polar signals of the same amplitude. These signals summarize, filter and control the oscillator frequency, divide the oscillator frequency and form the clock cycles, after the front of the reference signal appears, form a pulse front at the first output of the phase detector, wait for any clock switching and form a pulse slice at the first output of the phase detector. The pulse at the second output of the phase detector is formed under the condition that the front of the reference signal appears later than the clock front, while the pulse front at the second output of the phase detector is formed by a slice of clocks after the front of the reference signal, a clock front is expected and a pulse slice is formed at the second output of the phase detector .

This method can work at multiple frequencies and with a variable duty cycle of the reference frequency signal, which allows you to use it to adjust the clock frequency on the edges of the data when receiving discrete signals.

A phase detector is known [4], which contains three D-flip-flops and four logical elements I. In the center of the hold region with small lag of the clock front from the front of the reference frequency signal, when switching the signal at the D-input is ahead of the pulse front at the C-input of the trigger for a while , which is shorter than the trigger switching time, but more than half of it, there is a time interval in which “arbitration” is possible in the first D-trigger. In the case of “arbitration”, switching skipping, increasing switching time, oscillatory anomaly, or metastable anomaly are possible [3]. Dangerous for this method are oscillatory and metastable anomalies, which, taking into account the probability, lead to an increase in phase noise in the hold mode.

Closest to the proposed are the method and phase detector [4] (prototypes).

The purpose of the invention (technical result) is to increase functional stability (eliminating the influence of dangerous competitions) in the hold mode.

The technical result is achieved by the fact that:

1) In the frequency adjustment method, in which the reference signal is supplied to the first input of the phase detector in the phase comparison device, in which the signals at the two outputs of the phase detector with two keys control the connection and disconnection of two different-polar DC sources for summing. Next, the total signal is filtered and the received signal is controlled by the generator frequency, the generator frequency is divided and the clocks are generated, which are fed to the second input of the phase detector in the phase comparison device. The first source is connected at each edge of the reference signal. The connected first source is disconnected on the first clock edge received after the front of the reference signal, or on the cutoff of the reference signal, if it arrives earlier than the first clock edge after the front of the reference signal. The second source is connected after the front of the reference signal along the front of the clocks, if it arrives before the cutoff of the reference signal, the connected second source is disconnected according to the first cut of the clocks.

2) The ratio of the signal of the second source to the signal of the first source is set equal to (or less) 1/2 of the ratio of the smallest of the values of the pulse width of the reference frequency or period of ticks to the pulse width of the clock.

3) In a phase detector containing two D-flip-flops, two And elements, additionally the second input of the first And element is connected to the second output of the first trigger. The clock input is connected to the inverse C-input of the second trigger, the reference frequency input is connected to the D-input of the first trigger, the first output of the first trigger is connected to the D-input of the second trigger,

4) The phase detector additionally contains two OR-NOT elements. The reference frequency input is connected to the first inputs of the OR-NOT elements, the second inputs of the first and second elements OR-NOT are connected in pairs with the second output of the second trigger and the first output of the first trigger, respectively. The outputs of the first and second elements are NOT connected in pairs, respectively, with the reset inputs of the first and second triggers.

5) The phase detector has an additional permission input, which is connected to the third inputs of the first and second elements OR-NOT.

The group of inventions is related by a common concept and satisfies the requirement of unity of invention, because a phase detector is part of a device for implementing the proposed method. When analyzing the level of technology and novelty of the claimed objects, no analogues were found with the above set of the above features. Therefore, the described technical solution meets the criterion of "novelty."

A frequency tuning method is shown in FIG. 1 and 2. In FIG. 3, 4 and 5, phase detector circuits are shown, and in FIG. 6 and 7 are timing diagrams of their operation.

The reference signal Fo (Figs. 1 and 2) is fed to the first input of the phase detector 2 in the phase comparison device 1, in which the signals at the two outputs P and N of the phase detector 2, using two keys 131 and 132, control the connection and disconnection of two different-polarity constant sources current 121 and 122 for summation. Next, the total signal S is filtered 3 and the received signal U is controlled by the frequency of the generator 4, the frequency of the generator 4 is divided 5 and the clocks are generated, which are fed to the second input Fc of the phase detector 2 in the phase comparison device 1. A first source 121 is connected to each edge of the reference signal Fo, The connected first source 121 is switched off on the first edge of the clock cycles Fc received after the edge of the reference signal Fo, or on the cutoff of the reference signal Fo if it arrives before the first edge of the clocks Fc after the edge of the reference signal Fo. The second source 122 is connected at the edge of the reference clock signal Fc, if it arrives before the cutoff of the reference signal Fo. The connected second source 122 is turned off by the first slice of the clock cycles Fc. In FIG. Figure 1 also shows the connection of the sources to the Vcc power supply and the GND common wire.

The ratio of the signal of the second source S _n to the signal of the first source S _{p is} set according to the formula:

where T _si is the pulse duration of the ticks;

T _SP - the duration of a pause of measures;

T _oi - the pulse duration of the reference signal;

T _s - the duration of the period of ticks (T _s = T _si + T _SP ).

In the timing diagram of FIG. 2 also used the notation:

Uo is the average voltage level at the input of the generator 4;

T _f - the current shift between the edges of the signal of the reference frequency and clocks;

T _ph - the nominal value of the shift between the edges of the signal of the reference frequency and cycles in the hold mode.

The nominal value of the shift between the edges of the signal of the reference frequency and the clocks in the holding mode T _pho is determined by the formula;

For the values of S _n and S _p in accordance with (1), formula (2) is reduced to the condition;

The polarity of the terms P and N implies an increase in the frequency of the oscillator 4 with an increase in the voltage U. When the front of the reference signal Fo is ahead of the clock front Fc by a time less than T _ph , then the clock frequency is reduced, and if this time is more than T _ph , then the clock frequency is increased.

For the first two pulses (Fig. 2) T _oi <T _s and T _fo ≤T _oi / 2. Adjustment for multiple periods is illustrated by the third pulse in the time diagram of FIG. 2, for which it is possible to choose T _fo ≤T _s / 2, if you do not need to work in the first mode.

The linear operation of the device comparing the phases 1 is carried out in the range of values of T _f less than T _oi . In the angular representation, the linear region is located from 0 to 2π × T _oi / T _s and in it, after working out the front of the reference shear frequency by T _f, upon completion of all transients, the change in the DC component of the voltage at the filter output ΔU is determined by the formula:

where K is the transmission coefficient of the filter.

In the zone from 0 to 2π × T _pho / T _s , a negative ΔU (second pulse) is obtained, and in the range from 2π × T _pho / T _s to 2π, a positive one (first and third pulse) is obtained. If T _oi <T _s , then a nonlinear zone appears from 2π × T _oi / T _s to 2π, in which ΔU is positive, constant and equal to:

Loop stability is ensured by filter parameters.

After capture in the holding zone, the switching signal of the reference frequency and the clocks are separated by the time T _pho , which ensures the functional stability of the method (as the ability to build a device free from the influence of dangerous competitions).

The phase detector (Fig. 3) contains two triggers 211 and 212, two elements And 221 and 222. The clock input of the device Fc is connected to the C-input of the first trigger 211. The first P and second N outputs of the phase detector 2 are connected in pairs, respectively, with the outputs of the first 221 and the second element 222 And, the first input of the first element And 221 is connected to the D-input of the first trigger 211, the inputs of the second element And 222 are connected in pairs with the D-input and the second output of the second trigger 212. The second input of the first element And 221 is connected to the second output first trigger 211, clock input Fc with connected to the inverse C-input of the second trigger 212, the reference frequency input Fo is connected to the D-input of the first trigger 211, the first output Q1 of the first trigger is connected to the D-input of the second trigger 212. In addition, Fig. 3 also shows the elements of the phase comparison device 1: keys 131, 132 and miscellaneous sources 121, 122.

Both D-flip-flops are two-stage.

In addition to the circuit (Fig. 3), the phase detector (Fig. 4) contains two elements OR 231 and 232, the input of the reference frequency Fo is connected to the first inputs of the elements OR 231 and 232. The second inputs of the first and second elements OR NOT 231 and 232 are connected in pairs, respectively, with the second output of the second trigger 212 and the first output Q1 of the first trigger 211. The outputs of the first and second elements OR 231 and 232 are connected in pairs with the reset inputs of the first and second triggers 211 and 212, respectively. The reset inputs of both triggers are asynchronous .

In FIG. 5 shows an addition to a phase detector (Fig. 4.), in which an additional EN enable input is connected to the third inputs of the first and second elements OR 231 and 232.

In FIG. 6 solid lines show the timing diagrams of all the signals of the circuit (Fig. 3), and the dotted line shows the signals Q1, Q2, signals at the outputs of the elements OR-NOT 231 and 232 of the circuit (Fig. 4).

In the circuit of FIG. 3, after the front Fo (Fig. 6) switches to the log. 1 first element And 221 (output signal P). If the slice of the pulse Fo appears earlier than the clock front (the third pulse Fo of the diagram in Fig. 6), then the first element And 221 (output signal P) switches to the log. 0, and trigger 211 remains in the log state. 0. If the front of the clocks appears before the slice of the pulse Fo (the first and second pulse Fo in the diagram in Fig. 6), then the first trigger 211 (the designation in the diagrams is Q1) switches to the log. 1, then the first 221 and second 222 AND elements (output signals P and N) will switch respectively to the log. 0 and 1. Next, by the cut of the clocks, the second trigger 212 (the designation on the diagrams is Q2) will switch to log.1, then the second 222 element And will switch to the log. 0. The first edge of the clocks after cutting the pulse Fo will switch the first trigger 211 Q1 to the log. 0, then on the next cut of measures in a log. 0 will go over the second trigger 212 Q2.

With equal nominal frequencies of the reference frequency and clocks, the first trigger 211 does not have time to recover, therefore, the circuit (Fig. 3) can be used to fine-tune the reference frequencies Fo, the period of which is a multiple of the clock period by 2 or more times.

The functional stability of the device (Fig. 3) is provided by mixing transients in the triggers for half the cycle period.

The operation of the circuit (Fig. 4) for multiple periods is illustrated by a diagram (Fig. 6) taking into account the dashed lines. Until the moment of switching to the log.1 of the second trigger 212 Q2 with the signal log. 0 at the input Fo of the circuit shown in FIG. 3 and 4, operate identically (solid lines in FIG. 6). After this switch, in parallel with the switch to the log. 0 of the second element AND 222, the first element OR-NOT 231 is switched to log.1 (dashed lines in Fig. 6), after which the trigger 211 Q1 is reset asynchronously. Then sequential switching of the second element OR NOT 232 to the log. 1, asynchronously reset the second trigger 212 Q2 and switch the first element OR NOT 231 to the log. 0. The second element OR NOT 232 will switch to the log. 0 only after the front Fo. In the diagram of FIG. 6, it can be seen that despite differences in some trigger switching, the output signals for the circuits shown in FIG. 3 and 4 are the same.

The phase detector (Fig. 4) can operate at equal nominal frequencies. The timing diagram (Fig. 7) explains its operation in this mode. The switching sequence in the time diagram is shown by arrows. By cutting the pulse of the clock cycles Fc, the second switch 212 Q2 is switched sequentially to the log. 1 and then the first element OR NOT 231 to the log. 1. After the asynchronous reset of the trigger 211 Q1 is performed, then the second element OR-NOT 232 is switched to the log. 1. Then, the second trigger 212 Q2 is asynchronously reset and the first OR-NOT 231 element is switched to the log. 0. After these switches, the auxiliary trigger as part of the first trigger should have time to switch before the beat front. The duration of a pause of measures must be greater than the sum of the delays of 3 elements, asynchronous reset of 2 triggers and writing to the D-trigger.

The phase detector (Fig. 4) is functionally stable (resistant to competition), because Elements for sequential asynchronous reset of triggers do not introduce dangerous contests and the operation of the circuit does not depend on the spread of delays.

Phase detector (Fig. 5) at the log. 0 at the EN input also works like a circuit (Fig. 4), with any multiplicity of the reference frequency period to the clock period. When the log. 1 at the EN input, it works similarly to the circuit (Fig. 3).

Thus, the proposed method and phase detector are functionally stable (free from the influence of competition), work with a reference signal with any period multiplicity to the cycle period, and can adjust the cycle frequency according to the data edges.

Information sources

1. Patent US 5892380, CL 337/172, 04/06/1999.

2. Patent US 8975924, cl. 337/12, 03/10/2015.

3. Automated control of asynchronous processes in computers and discrete systems / Ed. IN AND. Warsaw. - M .: Science Ch. ed. physical mat. lit., 1986 .-- 400 p. (chapter 9)

4. RF patent 2622628, IPC H03D 13/00, 08/08/2016.

Claims (5)

1. A frequency adjustment method in which the reference signal is supplied to the first input of the phase detector in a phase comparison device, in which the signals at the two outputs of the phase detector using two keys control the connection and disconnection of two different-polar DC sources for summing, then the total signal is filtered and the received signal is controlled by the frequency of the generator, the frequency of the generator is divided and the clocks are fed to the second input of the phase detector in the phase comparison device, I connect the first source t on each edge of the reference signal, characterized in that the connected first source is turned off on the first clock edge received after the edge of the reference signal, or on the cutoff of the reference signal, if it arrives earlier than the first clock edge after the edge of the reference signal, the second source is connected after the edge of the reference signal on the front of the clock, if it arrives before the cutoff of the reference signal, the connected second source is disconnected by the first cut of the clock. 2. The method according to p. 1, characterized in that the ratio of the signal of the second source to the signal of the first source is set equal to or less than 1/2 of the ratio of the smallest of the values of the pulse width of the reference frequency or period of ticks to the pulse width of the ticks. 3. A phase detector containing two D-flip-flops, two And elements, the clock input being connected to the direct C-input of the first trigger, the first and second outputs of the phase detector are connected in pairs with the outputs of the first and second And elements, the first input of the first And element is connected with the D-input of the first trigger, the inputs of the second element And are connected in pairs with the D-input and the second output of the second trigger, characterized in that the second input of the first element And is connected to the second output of the first trigger, the clock input is connected to with the C-input of the second trigger, the reference frequency input is connected to the D-input of the first trigger, the first output of the first trigger is connected to the D-input of the second trigger, 4. The phase detector according to claim 3, characterized in that it contains two OR-NOT elements, the reference frequency input is connected to the first inputs of the OR-NOT elements, the second inputs of the first and second OR-NOT elements are connected in pairs, respectively, with the second output of the second trigger and the first output of the first trigger, the outputs of the first and second elements OR NOT connected in pairs, respectively, with the reset inputs of the first and second triggers. 5. The phase detector according to claim 4, characterized in that it additionally has a resolution input that is connected to the third inputs of the first and second elements OR-NOT.

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