RU2447576C2 - Method for phase lock-in of generated pulse sequence to external triggering pulse - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: method is related to conversion of delay into digital code with storage of output signals of multidrop delay line through which syncro clock wave passes at the moment of external triggering pulse arrival; received digital code is converted into multiplexor control signals in order to extract one signal from multidrop delay line with required delay time of syncro clock.

EFFECT: accuracy improvement of phase clock-in for reference generator syncro to external triggering pulse which allows generation of delay with any preset duration counted starting from external triggering pulse.

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Description

The invention relates to devices of pulsed technology and can be used in precision pulse generators.

In precision pulse generators designed to generate pulse sequences with a given duration, time delay and repetition period, the problem of phase linking of the generated pulse sequence to an external trigger pulse arises. This means that any time parameters of the generated pulse sequence are counted relative to the external trigger pulse.

If the permissible error of reference is comparable with the repetition period of clock pulses generated by an internal reference (usually quartz) generator and synchronizing the operation of all nodes of the pulse generator, then this problem can be easily solved by digital circuitry, i.e. The formation of the output pulse sequence begins with the first clock pulse following the external trigger pulse. Since the external trigger pulse is not tied to clock pulses in any way, the error of their binding to the external trigger pulse can vary within the same period of clock pulses. This is manifested in the form of jitter (jitter) of all fronts and decays of the generated pulse sequence relative to the external trigger pulse. If the permissible temporal error of the binding should be significantly (one or two orders of magnitude) less than the period of the clock pulses, then there is a need for phase binding of the clock pulses. Classical methods of phase-accurate synchronization (for example, phase-locked loop - PLL) are not applicable here due to the high inertia of the used crystal oscillators and the possible irregularity of external triggering pulses.

In general terms, the essence of the methods used is that the clock pulses are delayed until the beginning of the next clock pulse coincides with the beginning of the external trigger pulse (more often than not, a copy delayed for the period of the clock pulses).

A known method of phase locking, based on the means of analog circuitry used in the pulse generator G5-66 [G5-66 pulse generator. Technical description and operating instructions [Text]: 3.269.085 TO]. In accordance with it, the delay between the previous clock pulse and the external trigger pulse is stored in the form of a voltage proportional to it. To do this, the delay is converted into voltage using the first linearly varying voltage generator (GLIN), which is triggered by a clock pulse and stopped by an external trigger (delayed by an external trigger pulse to simplify implementation). Each subsequent clock pulse is delayed by the method of the inverse transformation of the voltage into a delay value using a second GLIN identical to the first one, triggered by a clock pulse and reset to the initial state when the voltage stored by the first GLIN is reached. The moment of voltage equality is fixed by the comparator, and the voltage drop formed at its output is phase-locked to an external trigger pulse. The output pulses of the comparator are delayed clock pulses that are phase-locked to an external trigger pulse.

The method is implemented as follows. The incoming external trigger pulse permits the passage of clock pulses to the phase locking device and is simultaneously delayed by the delay line for the period of the clock pulses. The first clock pulse following the external trigger pulse starts the first linearly varying voltage generator (GLIN), built as an integrator based on the DC capacitor charge, which is disabled by the delayed external trigger pulse. With the arrival of a delayed external trigger pulse, the integrator's constant current is turned off and the voltage level corresponding to the delay of the external trigger pulse relative to the previous clock pulse is stored at the output of the first GLIN (on its capacitor). This converts the delay delay of the external trigger pulse relative to the nearest previous reference clock pulse to the voltage level. All subsequent clock pulses start the second GLIN, the output voltage of which is compared by the comparator with the stored voltage of the first GLIN, and when the voltage coincides at the output of the comparator, a delayed clock pulse is generated. Since the ramp up rates of the linearly varying voltage for both GLINs are the same, the clock pulses at the output of the comparator turn out to be phase-locked to the external trigger pulse. They are used as clock pulses for all other generator nodes.

Thus, the pulse generator uses an intermediate conversion of the delay to voltage, its storage, and the inverse transformation to the delay.

However, the described phase locking method has significant drawbacks.

1. Over time, the storage capacitor of the first GLIN will be discharged, which will inevitably lead to a proportional increase in the error in the restoration of the delay time. A few milliseconds after the arrival of the external trigger pulse, the integrator storage capacitor is completely discharged and the phase synchronization disappears.

2. Precision analog high-speed nodes operate on the background of powerful digital signals (clock pulses), which leads to significant errors when converting the delay to voltage and vice versa. Therefore, significant residual jitter remains.

As a prototype, we select the method implemented by the device [RU 2256290 C2. A device for phase linking a generated pulse sequence to an external trigger pulse. 05/05/2003], which eliminates the first drawback. The essence of the method consists in converting the delay between the external trigger pulse and the preceding clock pulse into a proportional voltage and, further, using an analog-to-digital converter to a digital code, storing it as a digital code, and then converting the stored digital code to a voltage level using digital-to-analog converter and, further, the conversion of voltage into the delay of all subsequent clock pulses. Thus, the method of [RU 2256290 C2. A device for phase linking a generated pulse sequence to an external trigger pulse. 05/05/2003] differs from [G5-66 pulse generator. Technical description and operating instructions [Text]: 3.269.085 TO] by additional conversion of voltage to code and code to voltage. Saving the delay value in the form of a digital code eliminates its change over time.

From the delayed clock pulses, sequences of pulses of a precision generator with the specified duration, time delay and repetition period are formed.

The formation is carried out due to the fact that previously all the time parameters of the pulse sequence are converted into a sequence of codes representing time shifts relative to the beginning of the period, and are stored in a storage device, from where they are sequentially (in increasing order) fed to the code comparison device, where they are compared with the contents of the counter clock pulses connected to the second input of the code comparison device. In this case, the code comparison device is gated by delayed clock pulses, phase-locked to an external triggering pulse. The output pulses of the code comparison device reproduce time shifts relative to the beginning of the period specified by the external trigger pulse. For this reason, the phase reference accuracy of the delayed clock pulses determines the phase reference accuracy of the generated pulse train of the precision generator.

The first method of phase binding of clock pulses to an external triggering pulse [G5-66 pulse generator. Technical description and operating instructions [Text]: 3.269.085 TO] is based on the intermediate conversion of the time interval into voltage, and then the inverse conversion of voltage into the time interval. This means that there is an accumulation of errors of two transformations. In the second embodiment [RU 2256290 C2. A device for phase linking a generated pulse sequence to an external trigger pulse. 05/05/2003] the number of intermediate transformations increases and the error of the phase reference even increases, remaining, however, at large time intervals from the external trigger pulse to the current delayed clock pulse.

The technical problem to which the present invention is directed is to increase the accuracy of the phase reference of clock pulses to an external trigger pulse in the entire interval of time parameters of the generated sequence.

The solution to this problem is provided by a complete rejection of analog nodes when storing and reproducing the delay. A method that implements this approach consists in directly converting the delay into a digital code, storing this code, and then converting the code into a delay of clock pulses.

The delay is converted into a digital code by storing in the memory register, at the moment of the appearance of the external trigger pulse, the output signals of the multi-tap delay line along which the electromagnetic wave of the clock pulse propagates. The resulting digital code is converted by the decoder into control signals of the multiplexer, which selects only one of the output signals of the multi-tap delay line, which is a delayed clock pulses associated with an external trigger pulse.

The structural diagram of a device that implements the method is shown in figure 1 and consists of: multi-tap delay line 1; memory register 2; decoder 3 and multiplexer 4.

A multi-tap delay line can be built on any element base, including repeaters logic elements, representing a chain of repeaters connected in series with branches Di at the points of the output and input connection points of adjacent circuit elements (for example, τ ₁ and τ ₂ - in Fig. 1 ) The input of the multi-tap delay line is clocked (CLK). Passing through a multi-tap delay line, clock pulses are delayed on each of its elements for a fixed time t _i equal to the time the signal passed through each delay element (Fig. 2). The total delay time of the clock signal can be calculated by the formula:

where t _i is the delay time on one element.

The number of elements n in the multi-tap delay line 1 must be such that the total delay time of the multi-tap delay line 1 is equal to the repetition period T of the clock pulses, i.e.:

Or, with the same t _i :

At the moment of arrival of the external trigger pulse (SYNC), the memory register 2 stores the instantaneous value of the signals (D _n -D ₁ ) at the connection points of the elements of the multi-tap delay line 1. The code (D _n -D ₁ ) stored in the memory register 2 is converted by the decoder 3 into signals control (A _k -A ₁ ) multiplexer 4, in order to switch one of the delayed clock signals to the output of the device. Figure 2 shows the signal (CLKi) delayed on i elements of the multi-tap delay line and passed to the output of multiplexer 4. Figure 2 shows the delay inherent in real digital elements between signals (CLKi) and (Di). The number of information inputs (n) of multiplexer 4, register-latch 2 and the number of inputs of decoder 3 are determined by the number of delay line elements 1. The number of outputs (k) of decoder 3 is determined by the number of control lines (k) of multiplexer 4, which depends on how it is controlled (parallel binary or unitary code). For example, for a multiplexer having n input lines, the number of control lines can be found by the formula:

where n is the number of input lines of the multiplexer, k is the number of control lines of the multiplexer.

For a multi-tap delay line 1 having eight delay elements (τ ₈ −τ ₁ ), the signal passage through each delay element is shown in FIG. 3. For multiplexer 4, which will have eight input (D ₈ -D ₁ ) and three control lines (A ₃ A ₂ A ₁ ), a decoder 3 can be constructed according to the truth table presented in figure 4 and obtained as follows. One period of the clock sequence (CLK) is divided into quanta, the number of which corresponds to the number of elements in the multi-tap delay line 1. In fact, the quantum duration corresponds to the delay time (t _i ) on one element of the multi-tap delay line 1. For one quantum, the signals remain constant the outputs of the multi-tap delay line 1, therefore, the code shown in figure 3 is a quantized sequence of codes (D ₈ -D ₁ ) at the outputs of the multi-tap delay line 1, in accordance with which the post Alen control code for multiplexer 4 (A ₃ A ₂ A ₁ ). Decoder 3 will perform the conversion of the following form [Water carriers AM Digital elements of automation systems [Text]. Tutorial. - Vologda. VSTU, 2001. - 108 p., Ill.]:

For example, the incoming external trigger pulse will click in the register - latch 2 code (D ₈ -D ₁ ), highlighted in figure 4 by two horizontal bold lines, according to which the control code of multiplexer 4 will be generated at the output of decoder 3 (A ₃ A ₂ A ₁ ). By means of a control code supplied to the control inputs of multiplexer 4, one of the input lines of multiplexer 4 is switched to its output. The first pulse at the output of the multiplexer after the pulse of the external start will have a shorter duration than the pulse width of the clock sequence, caused by delays in the latching of the code by the register-latch 2, decryption and switching of the multiplexer 4 (Fig. 3, the first pulse at the output of CLK5). Subsequent pulses of the delayed clock signal at the output of the multiplexer 4 will have a nominal duration and will be delayed by the delay time the signal passes through the multiplexer.

It should be noted that the unevenness of the links of the multi-tap delay line, the temperature drift of the parameters are not of fundamental importance, since the direct conversion of the delay to the code and the reverse conversion of the code to the delay is carried out using the same multi-tap delay line 1. The error value (manifested as a random component - aperture tremor or jitter) t _j caused by the discreteness of the conversion is determined by the amount of delay on one element of the multi-tap delay line 1:

The presented method of digital phase locking has the following advantages.

1. The value of the binding error in the form of jitter, determined by the value of the delay of one element. The reduction in error is achieved by reducing the delay of each delay element, accompanied by a proportional increase in the number of elements of the multi-tap delay line;

2. The smooth dependence of the jitter value (aperture tremor) of the delayed clock pulses on the time interval between the external trigger pulse and the current clock pulse, which is determined mainly by the characteristics of the clock generator, which is due to the storage of the delay value in the form of a digital code.

3. The small drift of the systematic component of the phase reference error in the form of slow changes in the average delay value (aperture delay), due to the use of the delay-code of the same delay line for direct and inverse transforms.

4. Manufacturability due to the absence of any settings associated with minimizing the jitter.

5. Small error due to the use of digital processing methods.

Claims (1)

The method of phase linking the generated pulse sequence to an external trigger pulse, which consists in converting the delay between the next clock pulse and the subsequent external trigger pulse into a digital code, storing this code and delaying all subsequent clock pulses by the delay value stored as a digital code based on the digital conversion code into a delay value, characterized in that the delay is converted to a digital code by storing the output signals of the multi-tap line the delay in which the wave of the clock pulse propagates at the moment of the arrival of the external trigger pulse in the memory register, and the resulting digital code is converted into control signals of the multiplexer, which selects only one of the output signals of the multi-tap delay line, on which the clock delay corresponds to the stored one.

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