RU2785070C1 - Method for phase binding of the generated sequence of pulses to an external trigger pulse - Google Patents

Abstract

FIELD: pulse technology.

SUBSTANCE: invention relates to the field of pulse technology and can be used in precision pulse generators. To achieve the effect, the method consists in storing the current position of the front of the clock pulse propagating in the multi-tap delay line in flip-flops at the moment the external trigger pulse arrives. In this case, the active trigger (having retained the position of the clock pulse front) switches the clock pulse from one of the outputs of the multi-tap delay line to the input of the logical summation element, at the output of which there are clock pulses that are phase-locked to the external trigger pulse.

EFFECT: reducing hardware costs, as well as increasing the accuracy of the phase reference of the reference oscillator clock pulses to the external trigger pulse, which makes it possible to form delays of any duration from them, counted from the external trigger pulse, with high accuracy.

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Description

The invention relates to the field of pulse technology and can be used in precision pulse generators.

In precision pulse generators designed to generate sequences of pulses with specified time parameters: duration, time delay and repetition period, there is a problem of phase binding of the generated pulse sequence to the external trigger pulse. This means that the counting of any time parameters of the generated sequence of pulses is carried out relative to the external trigger pulse.

Typically, pulse generators are built as digital devices, and have their own accurate clock generator. If the built-in source of clock pulses is selected as the source of the synchronization signal, then the time parameters of the generated pulses are a multiple of the period of the clock pulses, and the error of their setting is determined mainly by the error of the period of the clock pulses. However, when synchronizing from an external trigger pulse that is not tied to the clock pulses of the oscillator itself, the error of reference to the external trigger pulse can vary within one clock period. To eliminate this variability, the position of the clock pulse relative to the external trigger pulse must be the same, that is, the clock edge delay must be constant relative to the edge of the external trigger pulse.

A device is known [Patent RU No. 2256290 MPCH03L3/00. Device for phase reference of the generated sequence of pulses to an external trigger pulse. 05.05.2003], which implements the phase referencing method, the essence of which is to convert the delay between the external trigger pulse and the preceding clock pulse into a proportional voltage and, further, using an analog-to-digital converter to a digital code, saving it in the form of a digital code and the subsequent reverse conversion of the stored digital code into a voltage level using a digital-to-analog converter and, further, the conversion of voltage into a delay of all subsequent clock pulses. From the delayed clock pulses, sequences of output pulses of a precision generator are formed with specified time parameters - the delay from the beginning of the period, the delay between paired pulses, the duration of the pulses, the repetition period.

The formation of time parameters (time intervals) is carried out by classical methods using clock pulse counters, registers containing codes of time parameters, and coincidence circuits. The outputs of the coincidence circuits are synchronized with a delayed clock. Therefore, slow changes in their position relative to the external trigger pulse under the influence of destabilizing factors and jitter of the fronts (jitter - a rapid change in position) lead to an error in the formation of a sequence of pulses.

Converting the clock delay relative to the external trigger pulse into voltage, then into a digital code, then back into voltage, and finally back into delay, leads to the accumulation of errors in a long chain of conversions. In addition, the conversion of the time interval into voltage and inverse conversion is carried out by analog devices against the background of impulse noise generated by the operation of the digital devices of the generator, which also increases the phase referencing error.

There is also a way to overcome these disadvantages [Patent RU No. 2447576 IPC H03L7/00. The method of phase binding of the generated sequence of pulses to an external trigger pulse. 06/29/2010], consisting in the direct conversion of the delay into a digital code, saving this code and then converting the code into a clock pulse delay. The delay is converted into a digital code by storing in the memory register, at the moment the external trigger pulse appears, the output signals of the multi-tap delay line, along which the electromagnetic wave of the clock pulse propagates. The resulting digital code is converted by the decoder into control signals of the multiplexer, which selects only one of the output signals of the multi-tap delay line, which is a delayed clock pulse tied to an external trigger pulse.

This method provides a complete rejection of analog nodes in the storage and playback of the delay.

Its disadvantage is the need to precisely match the duration of the delay and the period of the clock pulses. In addition, the clock pulses must have a fixed duty cycle, for example, equal to 2. Since during operation the delay value changes under the influence of temperature and as a result of degradation, and the total delay can be either less or more than the cycle time of the clock pulses, when using the converter codes designed for the above conditions, its performance is violated, since unforeseen codes appear in the input sequence of codes (for example, when the delay value decreases, the number of ones in the code is not equal to the number of zeros, and with a nominal delay value, this equality is always observed). This leads to the inoperability of the device with absolute delay changes approaching, or exceeding the delay of one element. The code converter can be designed to operate in a predetermined range of delay changes, while, if the delay is less than a period, the synchronization error increases by an amount equal to the difference between the period of the clock pulses and the duration of the delay. In addition, the volume of code converter equipment increases dramatically, and the scalability of the solution, i.e. there is no need to redesign the device when changing the number of taps of the multi-tap delay line in order to improve the synchronization accuracy.

Reducing the error in the formation of time intervals when changing the duration of the total delay of the multi-tap delay line due to the influence of technological factors and operating conditions, as well as the elimination of failures is achieved by the method adopted as a prototype [Patent RU No. 2693595 IPC H03L7/00 launch. 03/15/2018], consisting in the selection of a clock pulse at the output of the multi-tap delay line, on which the clock pulse propagating along the multi-tap delay line is delayed by a minimum time interval with respect to the external trigger pulse, while the clock pulses from each output of the multi-tap delay line are divided synchronous frequency dividers of the same type, the triggering of which is allowed by an external trigger pulse, and at the input of the logical summation circuit of the output signals of synchronous frequency dividers, clock pulses are formed by that synchronous frequency divider, at the clocking input of which a pulse edge appears with a minimum delay relative to the external trigger pulse, and the output signal of the mentioned synchronous frequency divider, with its high level, blocks the edges of the output signals of the remaining synchronous frequency dividers, while blocking the edges of the output signals of the remaining synchronous frequency dividers must continue for a period Yes, the following pulses on each of the outputs of the multi-tap delay line.

The disadvantage of this method is that in order to obtain synchronized clock pulses with a frequency equal to the frequency of the input clock pulses, it is necessary to use a frequency multiplier with a division factor equal to the division factor of synchronous frequency dividers. In addition, the volume of equipment due to the use of a multiplier and synchronous frequency dividers is large. The frequency multiplication also increases the phase noise by 6 dB for each frequency doubling. This increases the clock jitter.

The technical problem to be solved by the proposed method is to reduce the volume of equipment and increase the accuracy of binding clock pulses to an external trigger pulse.

The problem is solved by storing the current position of the front of the clock pulse propagating in the multi-tap delay line in flip-flops at the moment the external trigger pulse arrives. In this case, the active trigger (having retained the position of the clock pulse front) commutates the clock pulse from one of the subsequent outputs of the multi-tap delay line to the input of the logical summation element, at the output of which clock pulses are generated, phase-locked to the external trigger pulse.

Two short pulses are formed from the external trigger pulse - the trigger reset pulse and the delayed external trigger pulse. In this case, the duration of the delayed external trigger pulse is chosen so that at least one trigger is guaranteed to work.

The reset pulse transfers flip-flops to the initial state, blocking the passage of clock pulses from the outputs of the multi-tap line to the input of the logical summation element.

The delayed external trigger pulse is fed to the information inputs of the triggers, to the synchronization inputs of which signals are fed from the corresponding outputs of the multi-tap delay line. Since the signals from the pins of the multi-tap delay line are received at the synchronization inputs of the triggers during each period of clock pulses, the subsequent change in their state is blocked until the next external trigger pulse arrives, from which a reset signal is generated that transfers the triggers to the initial state and prepares them for the next recording of the current position of the front of the clock pulse.

The duration of the delayed external trigger pulse t _W supplied to the information inputs of the triggers must exceed the sum of the delay of one element of the multi-tap delay line t _i , the data preset time relative to the front of the clock pulse t _P , and the data hold time relative to the clock pulse t _y , i.e.:

t _Z > t _i + t _P + t _U .

Depending on the ratio of the delay of one element of the multi-tap delay line and the trigger parameters, more than one trigger can go into the active state, which will not disrupt the correct operation of the device, since the clock pulse that arrives first at the logical summation element blocks the edges of subsequent pulses. Such a situation can only change the duration of the pause of the clock pulses at the output of the logical summation element.

Active triggers pass to the input of the logic sum element clock pulses from the output of the multi-tap delay line at which the edge of the clock signal is delayed relative to the output connected to the synchronization input of the active trigger for an interval exceeding the settling time of the signal at the trigger output, i.e.

k × t _i > t _SO ,

where k is the number of delay elements between the output of the multi-tap delay line connected to the active trigger and the switched output, t _i is the delay of one element, t _SO is the signal propagation time from the synchronization input to the trigger output.

This solution eliminates the distortion of the position of the front of the first synchronized clock pulse at the output of the logical summation element.

This phenomenon would occur when switching the same clock pulse from the output of the tapped delay line that enters the active trigger clock input, since its edge would be additionally delayed by the trigger time in the current clock cycle, and in subsequent periods it would not observed.

Blocking flip-flops from subsequent state changes is achieved in a different way, depending on the type of rising/falling trigger being used. For example, for JK flip-flops, this is achieved by applying a logic zero to the K input of the flip-flop, and a delayed external trigger pulse to the J input. pulses will only confirm the state of the trigger as logical zeros will be present at the inputs J and K, which corresponds to the storage mode. Triggers clocked from other pins of the multi-tap delay line will assert a low output level, since at the time of writing their information inputs (here J) are low (the short delayed external trigger pulse is not yet there or has already been completed).

When a new external trigger pulse arrives, all triggers are set to their initial state.

The method does not impose stringent requirements on the speed of the element base, on the stability of the duration of the delayed external trigger pulse, and requires less hardware costs compared to the prototype.

The proposed solution is explained: Fig. 1 is a block diagram of a device that implements the method of phase binding of the generated pulse sequence to an external trigger pulse; fig. 2 - timing diagram.

The method is implemented by the device shown in figure 1 and consisting of: multi-tap delay line 1; front-synchronized D-flip-flops 2; logic elements "OR" 3; logical elements "And" 4; logical summation element 5 ("OR"); single vibrators 6 and 7 (here is a variant of the device implemented on front-synchronized D-flip-flops).

Clock pulses ( CLK ) are fed to the input of the multi-tap delay line 1. The outputs of the multi-tap delay line 1 are connected to the synchronization inputs C of the corresponding flip-flops 2, the information inputs D of which receive a signal from the output of the logic elements "OR" 3. In this case, the first inputs of the logic elements " OR 3 are connected to the outputs of the corresponding triggers, and the second inputs are combined together and connected to the output of one-shot 7. The input of one-shot 7 is connected to the output of one-shot 6 and the inputs of the initial setting R of triggers 2, and the input of one-shot 6 is supplied with an external trigger pulse "SYNC". The outputs of triggers 2 are connected to the first inputs of the corresponding logic elements "AND" (they act as switches that switch clock pulses to the inputs of the logical summation element), the second inputs of which are connected to the outputs of the multi-tap delay line 1, on which the front of the clock pulse lags behind the front of the clock pulse at the trigger synchronization input for a given interval (in Fig. 1 and Fig. 2 this interval is equal to 2× t _i ). The outputs of the logic elements "AND" are connected to the inputs of the logical summation element 5, the output of which is the output of the synchronized clock pulses "SCLK".

The device works as follows. The input of the tapped delay line 1 receives clock pulses CLK. The front of the next pulse appears in turn on the first output of the multi-tap delay line C 1, then on the second - C 2, etc. With the arrival of the external trigger pulse "SYNC", the single vibrator 6 generates a negative pulse of a fixed duration, sufficient to reset triggers 2 on the inverse input R (initial state). In this case, a low level from the outputs of triggers 2 is fed to the first input of the logic elements "OR" 3, and at the second inputs of the logic elements "AND" combined together, connected to the output of the one-shot 7, there is also a logic zero level. Therefore, at the outputs of flip-flops 2 remains the level of logical zero.

On the trailing edge of the output signal of the one-shot 6, the one-shot 7 is started and generates a positive delayed external trigger pulse of duration t _W . While the second inputs and outputs of logic elements "OR" 3 and, consequently, the inputs of triggers ( D ) is set to a logical unit.

Trigger 2, to the synchronization input ( C ) of which, during the interval t _W , the edge of the clock pulse arrives from the output of the multi-tap delay line, is set to a logical unit state (there will be 1 or 2 such triggers). In this case, a high level from its output goes to the first input of the corresponding logic element "AND", which leads to its blocking in this state (the front of the next clock pulse confirms the state of the trigger).

A high level from the output of these flip-flops is fed to the first inputs of the corresponding logic elements "AND" 4, and their output signal will be determined by the signal at the second input. At the time of the appearance of a clock pulse at this input (in Fig. 2, after two delay intervals of the element of the multi-tap delay line), a clock pulse will appear at the output of the logic element "AND" 4 and go to the input of the logical summation element 5. At the same time, it will appear at its output tied to an external trigger pulse and the output signal “SCLK” shifted relative to it by a certain interval.

If two triggers are active, then the second trigger will be set one delay interval of the multi-tap delay line element after the first trigger, and two clock pulses shifted relative to each other will be present at the inputs of the logical summation element. At the end of the clock pulse controlled by the first of the active flip-flops, the second clock pulse will continue for one delay interval, which will shorten the pause between clock pulses, but their period will remain unchanged. Since the active flip-flops are locked in a logic-one state until the next external trigger pulse arrives, the clock pulses will continuously come to the output from the selected tap of the multi-tap delay line.

A multi-tap delay line can be built on any element base. The delay value of the tapped delay line must be equal to the period of the clock pulses. In this case, the clock pulses at the output of the last element of the multi-tap delay line (C6) approximately coincide in phase with the input signal "CLK", and at the first output (C1) they lag behind it by t _i . Therefore, the flip-flop clocked from the tapped delay line pin C5 switches the clock from C1, and the flip-flop clocked from C6 switches the clock from C2. An alternative approach would require the introduction of two additional delay line pins with outputs C7 and C8 replacing the clock pulses from pins C1 and C2, respectively.

The device timing diagram (FIG. 2) is derived from device simulation and illustrates the phase lock method. On the diagram: C1 ... C6 - output signals of the multi-tap delay line; Q1 ... Q6 - output signals of triggers; CLR is a short reset pulse generated from an external trigger pulse; SYNC is a short delayed pulse generated from an external trigger pulse, CLK is an input clock (the reference clock is an external device), SCLK is a clock generator pulses phase-locked to an external trigger pulse.

At the moment of arrival of the external trigger pulse, the short CLR pulse formed from it (highlighted by a circle in Fig. 2) resets all triggers (in Fig. 2, Q6 and Q1 are set to zero, and the rest of the trigger outputs were previously in a logical zero state).

The left cursor on the diagram highlights the front of the clock pulse C5, synchronizing the trigger. Since the high level of the SYNC pulse comes to the input D of the trigger through the logical element "OR" at this time, the output of the trigger Q5 is set to a high level (through the trigger delay interval). In this case, the high level of the signal Q5 at the input of the logic element "AND" allows the passage of clock pulses from the output of C1 to the input of the logical summation element 5 (Fig. 1, Fig. 2).

The right cursor marks the edge of clock pulse C4 on the 4th pin of the tapped delay line, which clocks the flip-flop during the next SYNC pulse. The flip-flop output Q4 enables the passage of clock pulses from the output C6 of the tapped delay line to the input of the logic sum element.

Thus, this method requires only one flip-flop per pin of the tapped delay line. When using a universal JK-flip-flop, there is no need for OR logic elements that provide blocking of D-flip-flops. There is no need to use a frequency multiplier, which introduces additional instability in the position of the clock edges. If the total delay time of the tapped delay line is chosen to be greater than the clock pulse period by the value of the trigger switching time, then its variations under operating conditions will monotonically affect the value of the clock pulse binding error.

Claims (1)

A method for phase-locking clock pulses to an external trigger pulse, consisting in switching clock pulses from one of the outputs of a multi-tap delay line, on which the clock pulse propagating along it is delayed by a fixed time interval with respect to the external trigger pulse, to the corresponding input of the logical summation element, with the output of which the phase-locked clock pulses are taken, characterized in that the position of the front of the clock pulse relative to the external trigger pulse is stored along this front in flip-flops for a short time interval determined by the duration of the generated pulse from the external trigger pulse, and the flip-flop that has changed its state switches the output multi-tap delay line, on which the edge of the clock pulse lags behind the interval exceeding the switching time of the trigger, while the possibility of changing the state of the triggers is blocked until the next external trigger pulse, formed The th of which the reset pulse sets the flip-flops to the initial state.

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