US20080030246A1 - Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines - Google Patents

Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines Download PDF

Info

Publication number
US20080030246A1
US20080030246A1 US11869935 US86993507A US2008030246A1 US 20080030246 A1 US20080030246 A1 US 20080030246A1 US 11869935 US11869935 US 11869935 US 86993507 A US86993507 A US 86993507A US 2008030246 A1 US2008030246 A1 US 2008030246A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
clock
signal
staging
circuitry
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11869935
Inventor
William Huott
Charlie Hwang
Timothy McNamara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/502Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two

Abstract

Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. application Ser. No. 11/341,032, filed Jan. 27, 2006, the contents of which are incorporated herein in their entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • This invention relates to generating a ratio clock signal using a global clock signal. More particularly, this invention relates to generating a ratio clock signal at any integer divided by two of a global clock signal.
  • 2. Description of Background
  • This application is related to U.S. patent application, filed on Jan. 27, 2006, entitled “Method for Locally Generating Non-Integral Divided Clocks with Centralized State Machines,” Ser. No. 11/341,038, attorney docket number POU920050175US1 (Z04-0001), having William V. Huott, Charlie C. Hwang and Timothy G. McNamara and as named inventors, the entire contents of which are incorporated herein by reference.
  • It is common for an integrated circuit chip (chip) to operate with multiple different clock speeds. Often, chip architecture allows different regions of the chip to have different clock speeds. To achieve multiple different clock speeds, a chip may employ multiple clock grids throughout the entire chip with each clock grid producing a distinct clock speed. However, employing multiple clock grids creates additional expense for chip production. Higher clock skews between clocks of different clock grids may reduce the maximum clock speed and reduce chip performance. Thus, to keep costs down and keep chip performance up, it has been common practice to use a single clock grid to generate a global clock and obtain different clock speeds by developing ratio clock speeds at a specific ratio to the global clock.
  • It is common to use external control signals to develop derivative clock speeds at a ratio to the global clock. Additionally, absent external control signals, derivative clock speeds are generally limited to having whole number ratios to the global clock of, for example, 2-to-1, 4-to-1, etc. Generally, there is known in the art circuits which centrally generate clocks with multiple frequencies or phases with multiple phase locked loops, and which use an integral divider. Additionally, complex circuits used to generate derivative clock speeds may create a time delay between the global clock and the derivative clock.
  • An existing solution is provided in U.S. patent application Ser. No. 11/056,024, the entire contents of which are incorporated herein by reference. This application describes a circuit and power device for a local state machine, which while well suited for its intended purpose, is primarily effective when there are only a few local circuits. However, there are embodiments where a high number of circuits use a non-integral divided clock locally. Thus, there is a need for a more compact solution than that described in U.S. patent application Ser. No. 11/056,024.
  • SUMMARY OF THE INVENTION
  • Embodiments include circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.
  • Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
  • TECHNICAL EFFECTS
  • As a result of the summarized invention, technically we have achieved a solution that provides for generation of an (n+0.5)-to-1 ratio clock signal by providing a control signal to staging latches and combination logic. This allows the duty cycle of the ratio clock to be controlled by the control signal.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
  • FIG. 1 illustrates one example of multiple state machines in the central control unit for control signal generation;
  • FIG. 2 illustrates a connection between a centralized state machine and local staging latches and logic;
  • FIG. 3 illustrates one example of staging latches and logic for (n+0.5)-to-1 clock generation;
  • FIG. 4 illustrates one example of a local passgate circuit;
  • FIG. 5 illustrates one example of timing diagrams of two 1.5-to-1 clocks with different duty cycles;
  • FIG. 6 illustrates one example of a method of determining required clkl and clkh pattern;
  • FIG. 7 illustrates one example of determining the timing relationship of clkl and clkh;
  • FIG. 8 illustrates one example of a circuit for generating 1.5-to-1 clock with 4 latches;
  • FIG. 9 illustrates centralized programmable state machines and local clock generation circuits;
  • FIG. 10 illustrates one example of a 1.5-to 1 clock with 33.3% duty cycle;
  • FIG. 11 illustrates one example of a circuit for generating 1.5-to-1 clock with 3 latches;
  • FIG. 12 illustrates one example of a circuit for generating 1.5-to-1 clock with 2 latches and the associated timing diagram, and
  • FIG. 13 illustrates a block diagram of an existing ratio clock generator.
  • The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 13 illustrates a block diagram of an existing ratio clock generator, such as that described in U.S. patent application Ser. No. 11/056,024. FIG. 13 shows a centralized clock control 12 that provides a start-up signal to a local clock generation circuit 14. The local clock generation circuit 14 includes staging latches 16, state machine and logic 18 and passgates 20. The output of the passgates 20 is the (n+0.5)-to-1 clock signal. Local clock buffers 22 store the clock signals for local devices.
  • Circuits used to provide a ratio clock generator are now described with reference to FIGS. 1-12. FIG. 1 depicts centralized state machines 30 that generate clock control signals. The control signals are generated centrally from the centralized state machines 30 and may be reconfigurable from external controls. One example is to generate different control signal patterns from a clock control unit 28 using multiple state machines 30 and select control signal patterns through a multiplexer 32. The state machine 30 could be a simple counter or a counter with some logic depending on the control patterns required.
  • As described in co-pending application Ser. No. 11/056,024 the state machine 30 may employ counters to increment logic states as described in U.S. patent application Ser. No. 11/056,024. In exemplary methods, the state machine creates a “count-to-three counter” that counts in binary, for example, 0, 1, 2, 0, 1, etc. The count-to-three counter passes through (counts) three incremental logic states twice during three complete clock cycles of a global clock. Therefore, the output of the count-to-three counter goes through a complete cycle every one and one-half global clock cycles (or a 1.5-to-1 ratio). In general, the control signal can have a non-integer number of cycles in response to a single global clock cycle.
  • FIG. 2 illustrates a connection between a centralized state machine 30 and local staging latches and logic 34 in alternate embodiments. The control signals sent from the state machine 30 are distributed through a tree like structure to the local staging latches and logic 34. The control signals are periodic patterns, which contain timing information. The delay is equalized between the state machine 30 and the staging latches and logic 34 for all branches so all staging latches and logic are synchronized properly.
  • FIG. 3 illustrates one example of staging latches and logic for (n+0.5)-to-1 clock generation. The staging latches and logic comprised of one or multiple latches for generating delayed control signal of two phases, L1 and L2. A global clock signal clkg and inverted global clock signal clkgb are provided to gate the latches 36 to generate delayed control signals 1 l . . . 1N. The first staging latches 36 also serve the purpose of aligning the timing of the control signals. Combination logic 38 is positioned between each pair of connected latches 36. The combination logic 38 between latches 36 may be used to alter the control signal patterns. Alternatively, the combination logic 38 can simply pass through the control signals without alteration but serve as a delay element to prevent early-mode timing fails. A group combination logic 40 combines the delayed or altered control signals 1 l . . . 1N from all the latches 36 to generate the clock high signal (clkh) and clock low signal (clkl) to be sent to the passgates. The clock high signal (clkh) and clock low signal (clkl) have patterns derived from a waveform of a target divided ratio clock. The clock high signals and clock low signals have patterns that match the targeted divided clock frequency and duty cycle
  • FIG. 4 illustrates one example of a local passgate circuit. The clock high signal clkh is passed through the passgates 44 when the global clock clkg is high as shown in FIG. 4. The clock low signal clkl is passed by passgates 44 when the global clock signal clkg is low as shown in FIG. 4. The global clock signal clkg is the 1:1 global clock, which is the reference of the generated ratio clock. The output of the passgates 44 is the (n+0.5)-to-1 ratio clock.
  • FIG. 5 illustrates one example of timing diagrams of two 1.5-to-1 clocks with different duty cycle. Since the clock high signal clkh is passed by passgates 44 when the global clock signal clkg is high, the clock high signal clkh needs to be stable when the global clock signal clkg is high. That means that the clock high signal clkh is sourced from an L2 latch having a first phase delay shown in FIG. 3. For the same reason, the clock low signal clkl is sourced from an L1 latch having a second phase delay as shown in FIG. 3.
  • With the above basic structure, the number of staging latches 36, the control signal pattern generated from the state machine 30 and the combination logic 38 can be manipulated to achieve the intended (n+0.5)-to-1 clock with desired duty cycle. Since the passgates 44 can only switch at rising or falling edges of the global clock clkg, the achievable duty cycle is an increment of 100/(2n+1) %.
  • FIG. 6 illustrates one example of a method of determining a clock low signal clkl and clock high signal clkh pattern. First, the desired pattern of (n+0.5)-to-1 clock is determined, for example: 1.5-to1 clock with a 66.7% duty cycle. Then, the required clock low signal clkl and clock high signal clkh patterns are determined that will generate the (n+0.5)-to-1 clock. The clock low signal clkl is valid when the global clock signal clkg is low. The clock high signal clkh is valid when global clock signal clkg is high.
  • FIG. 7 illustrates one example of determining the timing relationship of the clock low signal clkl and the clock high signal clkh. If a two-state-machine option is used as shown in FIG. 1, each state machine 30 will generate the needed clock low signal clkl and clock high signal clkh patterns. No staging latch is required in the embodiments with multiple state machines. If staging latches and logic are used, the relationship between the clock low signal clkl and the clock high signal clkh is determined. A single state machine 30 with staging latches 34 instead of two state machines 30 may be used due to the patterns of the clock low signal clkl and the clock high signal clkh being related. In the example above, the clock low signal clkl has the pattern of 011011, while the clock high signal clkh has 101101. The clock high signal clkh can be obtained by delaying the clock low signal clkl by 1.5 global clock signal clkg cycles.
  • FIG. 8 illustrate one example of a circuit for generating 1.5-to-1 clock defined in FIG. 6 with 4 latches. The logic circuitry 38 (delay elements in this example), number of staging latches 36, and control signal pattern are selected to generate the clock low signal clkl and the clock high signal clkh. In the example above, the clock low signal clkl will be taken directly from delayed control signal 1 l, while the clock high signal clkh is taken from delayed control signal l4. No group combination logic 40 is used in this example. A similar structure in FIG. 8 may be used to generate 2.5-to-1 clock by adding two more staging latches. For (n+0.5)-to-1 clock, 2n+2 staging latches may be used.
  • The staging latch circuit is generally associated with the frequency of the clock to be generated. If the completely centralized approach is taken as shown in FIG. 9, the local clock generation circuits 46 only contain passgates 44. The frequency and duty cycle of the generated clock become completely programmable by controlling the state machines 48 in the central clock control unit. This may be a solution of choice if complete programmability of the ratio clock is desired.
  • The table below shows examples of generating different ratio clocks with different clock low signal clkl and clock high signal clkh patterns. Any n/2 clock may be generated by changing the clock low signal clkl and the clock high signal clkh generated from the central state machines. The change of frequencies can even be done dynamically during chip operations.
    clkl clkh ratio clock
    000000 111111 1-to-1
    111111 000000 1-to-1 inverted
    011011 101101 1.5-to-1  
    010101 111111 2-to-1
    01111 11011 2.5-to-1  
  • FIG. 10 illustrate one example of a 1.5-to1 clock with 33.3% duty cycle. With the staging latch circuit shown in FIG. 8, the input control signal may be used to control the duty cycle of (n+0.5)-to-1 clock. Since there is no change to the staging latch circuit, this can be achieved by reconfiguring or controlling the centralized state machine. FIG. 12 shows an example with an input control signal pattern of 100100 to alter the duty cycle.
  • FIG. 11 illustrates one example of a circuit for generating a 1.5-to-1 clock with 3 latches. If the staging latches and logic reside inside the local clock generation circuit, further compaction of the circuit may be desired to save area. Extra logic may be added to the combination logic part to reduce the number of staging latches required. The extra logic required depends on the intended frequency and duty cycle of (n+0.5)-to-1 clock. The example in FIG. 11 shows 1.5-to-1 clock implementation with only 3 staging latches 36.
  • FIG. 12 illustrate one example of a circuit for generating 1.5-to-1 clock with 2 latches and the associated timing diagram. This provides an even more compact circuit, using only 2n staging latches to generate (n+0.5)-to-1 clock if only the falling or rising of the edge of the clock is important and it's acceptable to have varying duty cycle on the generated clock.
  • The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
  • As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
  • Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
  • The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
  • While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Claims (18)

  1. 1. Circuitry for locally generating a ratio clock on a chip, comprising:
    circuitry for generating a global clock signal having a global clock cycle;
    a state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter;
    staging latches receiving the control signal and generating a clock high signal and a clock low signal;
    a local pass gate receiving the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.
  2. 2. The circuitry of claim 1 wherein the clock high signal and clock low signal have patterns derived from a waveform of a target divided ratio clock.
  3. 3. The circuitry of claim 2 wherein the clock high signal and clock low signal having patterns that match the targeted divided clock frequency and duty cycle.
  4. 4. The circuitry of claim 1 further comprising combination logic positioned between pairs of staging latches.
  5. 5. The circuitry of claim 4 wherein the combination logic is a delay.
  6. 6. The circuitry of claim 1 further comprising group combination logic for receiving delayed control signals from the staging latches, the group combination logic generating the clock low signal and clock high signal.
  7. 7. The circuitry of claim 1 wherein the state machine includes multiple state machines, each of which generates different control signal patterns.
  8. 8. The circuitry of claim 7 further comprising a multiplexer for selecting between the different control signal patterns.
  9. 9. The circuitry of claim 1 wherein equal delays are maintained between the state machine and local clock generation circuits including the passgates.
  10. 10. The circuitry of claim 4 wherein the pair of latches are clocked by alternate clock phases.
  11. 11. The circuitry of claim 1 wherein a first staging latch is used to synchronize timing.
  12. 12. The circuitry of claim 1 wherein the staging latches include 4 staging latches, one staging latch directly generating the clock low signal and another staging latch directly generating the clock high signal for generating a 1.5-to-1 ratio clock.
  13. 13. The circuitry of claim 12 further comprising a delay positioned between a first staging latch and a second staging latch, a delay position between the second staging latch and a third staging latch and a delay positioned between the third staging latch and the fourth staging latch, the first and third staging latches being clocked by a first phase of the global clock, the second and fourth staging latches being clocked by a second phase of the global clock signal, the second phase being opposite the first phase, the first staging latch generating the clock low signal and the fourth staging latch generating the clock high signal for generating a 1.5-to-1 ratio clock.
  14. 14. The circuitry of claim 6 wherein the staging latches include 3 staging latches and the group combination logic includes a NAND gate.
  15. 15. The circuitry of claim 14 further comprising a delay positioned between a first staging latch and a second staging latch and a delay position between the second staging latch and a third staging latch, the output of the first staging latch and the third staging latch being applied to the NAND gate to generate the clock low signal, the output of the second staging latch defining the clock high signal.
  16. 16. The circuitry of claim 6 wherein the staging latches include 2 latches and the group combination logic is an inverter.
  17. 17. The circuitry of claim 16 further comprising a delay position between a first staging latch and a second staging latch, the output of the first staging latch defining the clock low signal and the output of the second staging latch being applied to the inverter to generate the clock high signal.
  18. 18. Circuitry for locally generating a ratio clock on a chip, comprising:
    circuitry for generating a global clock signal having a global clock cycle;
    a state machine including a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter;
    staging latches receiving the control signal and generating a clock high signal and a clock low signal;
    a local pass gate receiving the clock low signal and the clock high signal and generating a clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.
US11869935 2006-01-27 2007-10-10 Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines Abandoned US20080030246A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11341032 US7319348B2 (en) 2006-01-27 2006-01-27 Circuits for locally generating non-integral divided clocks with centralized state machines
US11869935 US20080030246A1 (en) 2006-01-27 2007-10-10 Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11869935 US20080030246A1 (en) 2006-01-27 2007-10-10 Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11341032 Continuation US7319348B2 (en) 2006-01-27 2006-01-27 Circuits for locally generating non-integral divided clocks with centralized state machines

Publications (1)

Publication Number Publication Date
US20080030246A1 true true US20080030246A1 (en) 2008-02-07

Family

ID=38321447

Family Applications (2)

Application Number Title Priority Date Filing Date
US11341032 Expired - Fee Related US7319348B2 (en) 2006-01-27 2006-01-27 Circuits for locally generating non-integral divided clocks with centralized state machines
US11869935 Abandoned US20080030246A1 (en) 2006-01-27 2007-10-10 Circuits for Locally Generating Non-Integral Divided Clocks with Centralized State Machines

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11341032 Expired - Fee Related US7319348B2 (en) 2006-01-27 2006-01-27 Circuits for locally generating non-integral divided clocks with centralized state machines

Country Status (1)

Country Link
US (2) US7319348B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7319348B2 (en) * 2006-01-27 2008-01-15 International Business Machines Corporation Circuits for locally generating non-integral divided clocks with centralized state machines

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416443A (en) * 1993-12-22 1995-05-16 International Business Machines Corporation Reliable clock source having a plurality of redundant oscillators
US5596765A (en) * 1994-10-19 1997-01-21 Advanced Micro Devices, Inc. Integrated processor including a device for multiplexing external pin signals
US5926053A (en) * 1995-12-15 1999-07-20 National Semiconductor Corporation Selectable clock generation mode
US6134670A (en) * 1998-02-02 2000-10-17 Mahalingaiah; Rupaka Method and apparatus for generation and synchronization of distributed pulse clocked mechanism digital designs
US6272646B1 (en) * 1996-09-04 2001-08-07 Cypress Semiconductor Corp. Programmable logic device having an integrated phase lock loop
US6326812B1 (en) * 1997-05-23 2001-12-04 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US20020153933A1 (en) * 1997-04-21 2002-10-24 Fujitsu Limited Semiconductor device using complementary clock and signal input state detection circuit used for the same
US6550013B1 (en) * 1999-09-02 2003-04-15 International Business Machines Corporation Memory clock generator and method therefor
US6583648B1 (en) * 2002-03-19 2003-06-24 Intel Corporation Method and apparatus for fine granularity clock gating
US6611920B1 (en) * 2000-01-21 2003-08-26 Intel Corporation Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit
US6721081B1 (en) * 2002-09-26 2004-04-13 Corning Incorporated Variable duty cycle optical pulses
US7129764B2 (en) * 2005-02-11 2006-10-31 International Business Machines Corporation System and method for local generation of a ratio clock
US20070176653A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Methods and systems for locally generating non-integral divided clocks with centralized state machines
US20070176652A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Method for locally generating non-integral divided clocks with centralized state machines
US20070176651A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Circuits for locally generating non-integral divided clocks with centralized state machines

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416443A (en) * 1993-12-22 1995-05-16 International Business Machines Corporation Reliable clock source having a plurality of redundant oscillators
US5596765A (en) * 1994-10-19 1997-01-21 Advanced Micro Devices, Inc. Integrated processor including a device for multiplexing external pin signals
US5926053A (en) * 1995-12-15 1999-07-20 National Semiconductor Corporation Selectable clock generation mode
US6272646B1 (en) * 1996-09-04 2001-08-07 Cypress Semiconductor Corp. Programmable logic device having an integrated phase lock loop
US20020153933A1 (en) * 1997-04-21 2002-10-24 Fujitsu Limited Semiconductor device using complementary clock and signal input state detection circuit used for the same
US6326812B1 (en) * 1997-05-23 2001-12-04 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6134670A (en) * 1998-02-02 2000-10-17 Mahalingaiah; Rupaka Method and apparatus for generation and synchronization of distributed pulse clocked mechanism digital designs
US6550013B1 (en) * 1999-09-02 2003-04-15 International Business Machines Corporation Memory clock generator and method therefor
US6611920B1 (en) * 2000-01-21 2003-08-26 Intel Corporation Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit
US6583648B1 (en) * 2002-03-19 2003-06-24 Intel Corporation Method and apparatus for fine granularity clock gating
US6721081B1 (en) * 2002-09-26 2004-04-13 Corning Incorporated Variable duty cycle optical pulses
US7129764B2 (en) * 2005-02-11 2006-10-31 International Business Machines Corporation System and method for local generation of a ratio clock
US20070176653A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Methods and systems for locally generating non-integral divided clocks with centralized state machines
US20070176652A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Method for locally generating non-integral divided clocks with centralized state machines
US20070176651A1 (en) * 2006-01-27 2007-08-02 International Business Machines Corporation Circuits for locally generating non-integral divided clocks with centralized state machines
US7319348B2 (en) * 2006-01-27 2008-01-15 International Business Machines Corporation Circuits for locally generating non-integral divided clocks with centralized state machines
US7355460B2 (en) * 2006-01-27 2008-04-08 International Business Machines Corporation Method for locally generating non-integral divided clocks with centralized state machines

Also Published As

Publication number Publication date Type
US20070176651A1 (en) 2007-08-02 application
US7319348B2 (en) 2008-01-15 grant

Similar Documents

Publication Publication Date Title
US6326812B1 (en) Programmable logic device with logic signal delay compensated clock network
US4853653A (en) Multiple input clock selector
US6104228A (en) Phase aligner system and method
US7187742B1 (en) Synchronized multi-output digital clock manager
US7378893B1 (en) Circuit and method for digital delay and circuits incorporating the same
US6600355B1 (en) Clock generator circuit providing an output clock signal from phased input clock signals
US5687202A (en) Programmable phase shift clock generator
US6380774B2 (en) Clock control circuit and clock control method
US5786715A (en) Programmable digital frequency multiplier
US6563349B2 (en) Multiplexor generating a glitch free output when selecting from multiple clock signals
US5365119A (en) Circuit arrangement
US6259295B1 (en) Variable phase shifting clock generator
US6906562B1 (en) Counter-based clock multiplier circuits and methods
US6882196B2 (en) Duty cycle corrector
US6744289B2 (en) Clock divider circuit with duty cycle correction and minimal additional delay
US20060250168A1 (en) Highly configurable PLL architecture for programmable logic
US6014047A (en) Method and apparatus for phase rotation in a phase locked loop
US5204555A (en) Logic array having high frequency internal clocking
US6316982B1 (en) Digital clock with controllable phase skew
US7956664B2 (en) Clock distribution network architecture with clock skew management
US7913103B2 (en) Method and apparatus for clock cycle stealing
US20050212570A1 (en) Programmable frequency divider
US6441657B1 (en) Combinational delay circuit for a digital frequency multiplier
US6538957B2 (en) Apparatus and method for distributing a clock signal on a large scale integrated circuit
US7301385B2 (en) Methods and apparatus for managing clock skew