CN103647558A

CN103647558A - Manchester encoder circuit

Info

Publication number: CN103647558A
Application number: CN201310637006.5A
Authority: CN
Inventors: 匙嘉敏; 赵彦光
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2013-12-03
Filing date: 2013-12-03
Publication date: 2014-03-19

Abstract

The invention provides a Manchester encoder circuit realization structure suitable for double subcarriers. According to the circuit, double-subcarrier encoding is realized by changing the frequency of an input clock in different encoding cycles. Based on clock input of different frequencies, the encoder realizes double-subcarrier-based Manchester encoding waveform output by controlling and managing the encoding state. The encoder circuit realized through the method has the characteristics of simple structure, low input clock frequency and low power consumption.

Description

A kind of manchester encoder circuit

Technical field:

The present invention relates to Manchester's code field in ISO/IEC15693 standard

Background technology:

Manchester's code is a kind of coding with hopping edge transmission information.Compare with the flat pass binary code of transmission information of electricity consumption, tool has the following advantages: (1) waveform has saltus step in the middle of each bit, therefore has abundant timing information, is convenient to receiving terminal and receives timing information; (2) Manchester code has level transitions in each, during transmission, without DC component, can reduce the power consumption of system.Therefore, Manchester's code mode is highly suitable for the load-modulate mode of this employing subcarrier of rfid system.

The rfid system that meets ISO/IEC15693 standard, the carrier frequency between its electronic tag and reader is 13.56MHz.The mode that reader is encoded by pulse position sends to electronic tag by data, and the mode of electronic tag by Manchester's code sends to reader by data.The present invention carries out the design after optimised power consumption improvement to the design of the Manchester's code module in the electronic tag based on this standard.

According to ISO/IEC15693 standard, Manchester's code module must be supported the carrier wave of two kinds of patterns: single carrier and two carrier wave.The carrier frequency fc of system is 13.56MHz.While selecting single carrier, carrier wave fs1 frequency is fc/32 (423.75kHz); While selecting two carrier wave, the frequency of carrier wave fs1 is fc/32 (423.75kHz), and the frequency of carrier wave fs2 is fc/28 (484.28kHz), and both phase places must be continuous.Meanwhile, Manchester's code module also must be supported two kinds of data-transmission modes: fast mode and low-speed mode.The request signal that concrete data-transmission mode and carrier wave preference pattern are sended over by reader determines.The time that low-speed mode is lasting and pulse number are 4 times of fast mode, and coded system difference corresponding to the carrier wave of different mode.

The clock that general traditional design proportion is fc/4, as work clock, for two carrier modulation, adopts counter to clock count, produces respectively the carrier wave that frequency is fc/32 and fc/28.

Summary of the invention:

A kind of Manchester's code circuit structure that the present invention proposes, proportion is that the clock of fc/16 or fc/14 is as the clock input of encoder, replace the fc/4 clock input of traditional design, by input clock is carried out to 2 frequency divisions, realized the carrier wave output of fc/32 and fc/28.The method effectively reduces encoder operating frequency, is conducive to reduce chip power-consumption.

A kind of manchester encoder circuit structure disclosed by the invention, it is comprised of encoder and clock generating module two large divisions.Encoder is for generation of Manchester's code waveform, and it selects control signal according to coded frame data State-output clock division; Clock generating module is selected the input of control signal according to clock division, source clock is carried out to the clock division of different frequency dividing ratios, and the clock after this frequency division is exported to coder module for generation of coding waveforms.This encoder implementation structure, by changing encoded clock frequency, can be simplified code Design, reduces working clock frequency, reaches the optimization of area and power consumption.

Object of the present invention is mainly the dynamic power consumption that reduces encoder circuit, and a kind of manchester encoder circuit implementation structure is provided, and it mainly comprises two large divisions: clock generation circuit and encoder circuit.Circuit structure as shown in Figure 1.

Clock generation circuit, for generation of encoded clock, for reducing to greatest extent encoder working clock frequency, is simplified encoder design, and the clock frequency of encoded clock is to be twice in the carrier frequency that coding produces.Coding module can directly adopt the two divided-frequency output of this encoded clock to export as code period.

Encoder circuit is realized final code signal output, according to the indication of system enabling signal, produces required coded data waveform; Encoder circuit need produce clock frequency frequency division index signal according to coded data state, gives clock generation circuit, to produce satisfactory coding input clock.

A manchester encoder circuit, comprises clock generation circuit and encoder, and wherein clock generation circuit, utilizes the clock division of encoder output to select signal, constantly exports the clock signal of different frequency at different coding; Encoder comprises three parts: clock frequency division module, framing module and state conversion and control module, and clock frequency division module is for generation of the two divided-frequency output to encoded clock; State conversion and control module controls coding module produces the status indicator signal that frame starts SOF, frame end EOF and data ' 0 ' and data ' 1 '; Framing module is for generation of final coded data, and it utilizes encoded clock and status indicator signal after frequency division to produce coded data.State conversion and control module is according to the residing state of coded data, and cycle count value, and output clock frequency division selects signal to clock frequency division module.2 frequencys multiplication that the clock signal frequency of clock generation circuit output is coding frequency.

The coding circuit that the present invention realizes has feature simple in structure, input clock frequency is low, low in energy consumption.

Accompanying drawing explanation:

Fig. 1 manchester encoder circuit structure block diagram

Fig. 2 clock division selects signal to produce schematic diagram

Fig. 3 coding waveforms and timing relationship figure

Embodiment:

To meet the chip coding of ISO/IEC15693, be embodied as example below, introduce circuit implementation structure.The system clock frequency fc=13.56MHz of chip, as shown in Figure 1, src_clk clock frequency is 13.56MHz.When chip adopts twin subcarrier modulation, the frequency of carrier wave fs1 is fc/32, and the frequency of carrier wave fs2 is fc/28, and both phase places must be continuous.Therefore clock generating module should, according to different carrier wave output frequencies, be exported corresponding clock clk_encode.When coding module outgoing carrier frequency is fc/32, clk_encode clock frequency is fc/16; When coding module outgoing carrier frequency is fc/28, clk_encoder clock frequency is fc/14.Clock generation circuit is according to the indication of clk_div_sel signal, and producing frequency is the work clock clk_encode of fc/16 or fc/14.

Clk_div_sel signal is produced by the state conversion control circuit of encoder, and state conversion control circuit is realized the state conversion and control that coding sends, and comprises SOF, DATA0, DATA1 and EOF state.According to difference, send the requirement of state phase to carrier frequency, can produce clk_div_sel signal, physical relationship, can take ISO/IEC15693 coding protocol as example referring to Fig. 2 in figure, has described the relation between the generation of clk_div_sel signal and each encoding state.Wherein, clk_div_sel is 16 frequency divisions of ' 1 ' expression system clock, is 14 frequency divisions of ' 0 ' expression system clock.Clk_div_sel signal can overturn in each encoding state, the concrete moment that upset occurs, and can be referring to concrete protocol requirement.The relation of clk_div_sel and clk_encode clock can be referring to Fig. 3.

The frequency dividing circuit module of encoder is responsible for producing qualified carrier waveform, due to 2 frequencys multiplication of the encoded clock producing for coding carrier frequency, therefore encoded clock clk_encode need be carried out to 2 frequency division processing, as the carrier signal source of coding.

The framing module of encoder is responsible for according to coding transmission state and coding carrier wave, the opening and closing that startup and control coding send, and output meets the modulation waveform signal modu_data of protocol requirement.Relation is referring to Fig. 3 in detail.

Should be understood that, the present embodiment is used for illustrative purposes only, but not limitation of the present invention.Therefore person skilled in the relevant technique, without departing from the spirit and scope of the present invention, can also make various conversion or variation, and all technical schemes that are equal to also should belong to category of the present invention and limited by each claim.

Claims

1. a manchester encoder circuit, is characterized in that comprising clock generation circuit and encoder, and wherein clock generation circuit, utilizes the clock division of encoder output to select signal, constantly exports the clock signal of different frequency at different coding; Encoder comprises three parts: clock frequency division module, framing module and state conversion and control module, and clock frequency division module is for generation of the two divided-frequency output to encoded clock; State conversion and control module controls coding module produces the status indicator signal that frame starts SOF, frame end EOF and data ' 0 ' and data ' 1 '; Framing module is for generation of final coded data, and it utilizes encoded clock and status indicator signal after frequency division to produce coded data.

2. circuit as claimed in claim 1, is characterized in that state conversion and control module is according to the residing state of coded data, and cycle count value, and output clock frequency division selects signal to clock frequency division module.

3. circuit as claimed in claim 1, is characterized in that 2 frequencys multiplication that the clock signal frequency of clock generation circuit output is coding frequency.