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CN102567778A - Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates - Google Patents

Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates Download PDF

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CN102567778A
CN102567778A CN 201110450409 CN201110450409A CN102567778A CN 102567778 A CN102567778 A CN 102567778A CN 201110450409 CN201110450409 CN 201110450409 CN 201110450409 A CN201110450409 A CN 201110450409A CN 102567778 A CN102567778 A CN 102567778A
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coding
circuit
signal
control
selecting
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CN 201110450409
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CN102567778B (en )
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丁一
张俊
李晶
王德明
胡建国
谭洪舟
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广州中大微电子有限公司
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Abstract

The invention discloses a radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates. The coding circuit comprises a counter unit, a coding mode selecting circuit, a coding state machine, a coding output control circuit and a byte coding control circuit, wherein the counter unit is used for receiving a system coding clock signal and outputting a counting signal to the coding mode selecting circuit; the coding mode selecting circuit is respectively connected with a double-speed selecting signal, a single and double subcarrier selecting signal and a rate selecting signal and used for outputting a counting signal for distinguishing multiple coding modes to the coding state machine; the coding state machine is used for receiving bit information from the byte coding control circuit and outputting a control signal to the coding output control circuit; and the coding output control circuit is connected with an analog front end of an RFID tag chip. The multiple coding modes are supported by the coding circuit, so that the area of the chip is reduced, the power consumption of a system is reduced, and the circuit is simple in structure, high in stability and convenient to maintain.

Description

一种支持单双副载波和高低速率的RFID标签芯片编码电 Subcarriers for supporting single and double rate and low power RFID tag chip encoding

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技术领域 FIELD

[0001] 本发明涉及射频识别技术,尤其是一种RFID标签芯片编码电路。 [0001] The present invention relates to radio frequency identification technology, in particular an RFID tag encoding circuit chip. 背景技术 Background technique

[0002] 射频识别技术即RFID,是一种非接触的,能自动识别目标物体的通信技术。 [0002] i.e. the RFID radio frequency identification technology, is a non-contact communication technology can automatically identify the target object. 为了实现阅读器和标签芯片之间的可靠数据传输,不同的RFID技术其编码方法也有所不同,如符合IS0/IEC 15693协议的芯片采用脉冲位置编码和曼彻斯特编码、符合IS0/IEC 14443协议的芯片则采用曼彻斯特编码和改进型密勒编码。 In order to achieve reliable data transfer between the reader and tag chips, different RFID technology which coding methods are different, chips such as compliance with IS0 / IEC 15693 protocol using a pulse position encoding and Manchester encoding, in line with IS0 / IEC 14443 protocol chip Manchester encoding is used and a modified Miller code. 本发明将针对符合IS0/IEC 15693协议的编码电路。 The present invention will be in line with respect IS0 / IEC 15693 protocol encoder circuit.

[0003] 从标签芯片(VICC)到阅读器(V⑶)有六种编码模式:单副载波高速、单副载波低速、双副载波高速、双副载波低速、单副载波双高速和单副载波双低速模式。 [0003] from the tag chip (the VICC) to the reader (V⑶) in six coding modes: a single sub-carrier high-speed, low-speed single subcarrier, subcarrier double-speed, low-bis subcarriers, subcarrier single double and single-speed subcarriers double speed mode. 每次通信可以选择任何一种编码方式,如果VICC编码电路对每种模式采用一个编码电路,那么必须要6 个编码电路,这样就会大大增加VICC的面积和功耗。 Each communication can choose any encoding, if VICC encoding circuit for each mode uses a coding circuit, then the coding circuit 6 must be, which would greatly increase the area and power consumption VICC.

[0004] 由于单副载波和双副载波采用不同的频率进行编码,前者编码数据频率采用fc/32 ;后者编码数据频率采用fc/32和fc/观两个频率,这就为编码带来难度,一般的做法都需要分别对单副载波和双副载波进行编码,因此至少需要两个独立的编码电路。 [0004] Since the single sub-carrier and dual-frequency subcarrier to encode different, the former coded data using the frequency fc / 32; which encodes data using the frequency fc / 32 and fc / View two frequencies, which brings coding difficulty, general practice requires each sub-carrier and dual single subcarrier is encoded, and therefore requires at least two separate encoding circuit.

发明内容 SUMMARY

[0005] 本发明要解决的技术问题是:本发明提供一种支持单双副载波和高低速率的RFID标签芯片编码电路,该编码电路能对多种不同模式进行编码。 [0005] The present invention is to solve the technical problem: The present invention provides an RFID tag encoding circuit chip for supporting single and double subcarriers and low rate, the encoding circuit can be encoded on a number of different modes.

[0006] 为了解决上述技术问题,本发明所采用的技术方案是: [0006] To solve the above technical problem, the technical solution employed in the present invention:

本发明采用低功耗小面积的设计理念,只需要一个编码电路,就能对六种不同的编码模式进行选择编码。 The present invention uses a small area of ​​low-power design, only one encoding circuit for different coding modes can be selected six kinds of encoding. 本发明支持单双副载波和高低速率的RFID标签芯片编码电路,包括计数器单元、编码模式选择电路、编码状态机、编码输出控制电路和字节编码控制电路,所述计数器单元接收系统编码时钟信号并输出计数信号给编码模式选择电路,所述编码模式选择电路分别连接有双速选择信号、单双副载波选择信号及速率选择信号,所述编码模式选择电路输出用于区别多种编码模式的计数信号给编码状态机,所述编码状态机还接收来自字节编码控制电路的比特信息并输出控制信号给编码输出控制电路,所述编码输出控制电路与RFID标签芯片的模拟前端连接。 Subcarriers and the level of support for single and double rate coding circuit chip of the RFID tag of the present invention, comprising a counter unit, the coding mode selection circuit, a state machine coded, the coding control circuit and the output circuit of the control byte encoding, said encoding system counter unit receiving clock signal and outputs the count signal to the coding mode selection circuit, said encoding mode selection circuit are connected to a double speed selection signal, and odd and even sub-carrier selection signal rate selection signal, the encoding mode selecting circuit outputs a difference between a plurality of coding modes count signal to the coding state machine, the state machine also receives the encoded bit information from the byte codes and the control circuit outputs a control signal to the encoding output control circuit, said control code output analog front end circuit chip is connected with the RFID tag.

[0007] 进一步作为优选的实施方式,所述计数器单元包括第一计数器和第二计数器,系统时钟信号和编码使能信号相与后分别与第一计数器和第二计数器的输入端连接,所述第一、第二计数器的复位端还连接有来自编码状态机的计数器复位信号,所述第一、第二计数器输出的计数信号分别传输给所述编码模式选择电路的输入端。 After [0007] As a further preferred embodiment, the counter unit comprises first and second counters, the system clock signal and a phase encode enable signal are respectively connected to the input terminals of the first and second counters, the first, the reset terminal of the second counter is also connected to the counter reset signal from the encoder state machine, the first, the second counter output count signal are transmitted to said coding mode selection input of the circuit.

[0008] 进一步作为优选的实施方式,所述编码输出控制电路输入端分别连接有系统时钟第一分频信号、系统时钟第二分频信号、编码使能信号及单双副载波选择信号,控制端接收来自编码状态机输出的控制信号。 [0008] As a further preferred embodiment, the encoder output control circuit are connected to an input terminal of the first frequency-divided system clock signal, a second frequency-divided system clock signal, and enable signal encoded odd and even sub-carrier selection signal, the control a control terminal for receiving signal output from the encoder state machine.

[0009] 进一步作为优选的实施方式,所述编码输出控制电路包括一三输入与非门,系统时钟第一分频信号、编码使能信号和单双副载波选择信号经所述三输入与非门连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门,所述二输入与非门的一路信号来自系统时钟第二分频信号、另一路为单双副载波选择信号取反后与编码使能信号相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机输出的控制信号。 [0009] As a further preferred embodiment, the encoded output control circuit includes a three-input NAND gate, a first frequency-divided system clock signal, and the encoding enable signal to select odd and even sub-carriers via said three-input NAND signal gate connected with a multiplexer, the other input terminal of the multiplexer is connected to a twelve-input NAND gate, said two-input NAND gate of one signal from the second frequency-divided system clock signal, the other way signal selection signal obtained after the odd and even sub-carrier signal after the phase encoding or negated so, the selection control signal input terminal of the multiplexer control signal is output from the encoder state machine.

[0010] 进一步作为优选的实施方式,所述字节编码控制电路采用位编码,接收来自编码状态机的副载波计数信号并输出帧尾输出控制信号给编码状态机。 [0010] As a further preferred embodiment, the control circuit employs byte encoding bit code received subcarrier counted from a state machine coded signal and outputting a control signal to the output end of frame coding state machine.

[0011] 进一步作为优选的实施方式,所述编码状态机根据来自编码模式选择电路的所述区别多种编码模式的计数信号和所述帧尾输出控制信号切换状态。 [0011] As a further preferred embodiment, the coding state machine count signals and said plurality of coding mode control signal for switching the output end of frame state based on the difference from the coding mode selection circuit.

[0012] 进一步作为优选的实施方式,所述编码状态机的状态包括帧头状态、数据状态和帧尾状态,所述帧头状态的切换与帧尾状态的切换首尾对应。 [0012] As a further preferred embodiment, the coding header includes State Machine status, and last data state and the switching state of the end frame, the switching state of the header and the end of the frame corresponding to the state.

[0013] 进一步作为优选的实施方式,所述编码模式选择电路支持多种编码模式编码,包括单副载波高速、单副载波低速、单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 [0013] As a further preferred embodiment, the coding mode selection circuitry supports multiple coding mode, sub-carrier comprises a single high-speed, low-speed single subcarrier, subcarrier single double-speed, low-speed single-subcarrier double, double-speed subcarriers , bis subcarriers low.

[0014] 本发明的有益效果是:本发明RFID标签芯片编码电路采用编码模式选择电路实现了对多种编码模式的选择编码,节省了芯片面积、降低了系统功耗,并且通过一个编码状态机实现了编码电路中帧头、数据和帧尾多状态的切换,电路结构简单、稳定性高并且便于维护。 [0014] Advantageous effects of the invention are: RFID tag chip of the present invention employs an encoding circuit encoding mode selecting function of selecting the encoding circuit of a plurality of coding modes, saves chip area, power reduction, and by a coding state machine encoding circuit implements header, data and tail switching frame of multi-state circuit structure is simple, and easy to maintain high stability.

附图说明 BRIEF DESCRIPTION

[0015] 下面结合附图对本发明的具体实施方式作进一步说明: 图1是本发明RFID标签芯片编码电路实施例的原理方框图; [0015] DETAILED DESCRIPTION OF THE DRAWINGS Embodiment of the present invention will be further illustrated: FIG. 1 is a schematic block diagram of an embodiment of the present invention, RFID tag encoding circuit chip;

图2是本发明编码电路中编码输出控制电路实施例的具体电路原理图; 图3是本发明编码电路中编码状态机实施例的状态转换图。 FIG 2 is a specific circuit diagram of the present invention, an encoding circuit encoding the output control circuit of the embodiment; FIG. 3 is a state transition diagram of an embodiment of an encoding circuit encoding the state machine of the present invention.

具体实施方式 detailed description

[0016] 本发明提供了一种支持单双副载波和高低速率的RFID标签芯片编码电路,该编码电路能够对六种编码方式进行帧格式的编码,并将编码结果输出给芯片模拟前端。 [0016] The present invention provides an RFID tag encoding circuit chip for supporting single and double subcarriers and low rate encoding circuitry capable of encoding the frame format of six kinds of encoding, the encoded result is output to the analog front-end chip.

[0017] 参照图1,本发明编码电路包括计数器单元1、编码模式选择电路2、编码状态机3、编码输出控制电路5和字节编码控制电路4,计数器单元1接收系统编码时钟信号clk_ encoder并输出计数信号Cnt28、Cnt32给编码模式选择电路2,所述编码模式选择电路2分别连接有双速选择信号fast_inv_read、单双副载波选择信号Sub_carrier_flag及速率选择信号data_rate_flag,所述编码模式选择电路2输出用于区别多种编码模式的计数信号给编码状态机3,所述编码状态机3还接收来自字节编码控制电路4的比特信息cnt_bit并输出控制信号doU_r给编码输出控制电路5,所述编码输出控制电路5与RFID标签芯片的模拟前端连接并输出编码信号dout。 [0017] Referring to FIG 1, the present invention comprises a counter unit coding circuit 1, the coding mode selection circuit 2, a state machine 3 coding, the coding control circuit 5 and the output byte coding control circuit 4, the counter unit 1 receives the system clock signal encoded clk_ encoder and outputs the count signal Cnt28, Cnt32 circuit 2 to the coding mode, the coding mode selection are connected to the selection circuit 2 select the two-speed signal fast_inv_read, odd and even sub-carrier selection signal and the rate selection signal Sub_carrier_flag data_rate_flag, said encoding mode selection circuit 2 an output count signal for distinguishing a plurality of coding modes to the encoder state machine 3, the state machine 3 also receives the encoded bit information cnt_bit bytes from the coding control circuit 4 and outputs a control signal to the encoding doU_r output control circuit 5, the encoding analog front end output control circuit 5 is connected with the RFID tag chip and outputs the encoded signal dout.

[0018] 进一步,所述计数器单元1包括第一计数器11和第二计数器12,系统编码时钟信号clk_enc0der为系统时钟信号elk与编码使能信号tX_en经与门IlO相与后的输出。 [0018] Further, the counter unit 1 comprises a first counter 12 and second counter 11, the system clock signal clk_enc0der is encoded system clock signal elk tX_en encoding enable signal through the output phase of the door IlO. 在编码使能信号tX_en为低电平时,与门IlO输出为低电平,这时系统编码时钟信号clk_ encoder无效,这种门控时钟可在没有编码请求时使编码电路不工作,可降低芯片的功耗。 TX_en coding enable signal is at low level, the AND gate IlO output is low, then the system clock signal clk_ encoder encoding invalid, this may be gated clock encoding circuit does not work when a request is not encoded, the chip may be reduced power consumption. 系统编码时钟信号cllencoder作为第一计数器11和第二计数器12的工作时钟,连接到第一计数器11和第二计数器12的时钟输入端。 Cllencoder signal encoding system as the first clock counter 11 and the second operating clock counter 12 is connected to the clock input of the first counter 11 and second counter 12. 编码使能信号tX_en连接到第一计数器11和第二计数器12的使能输入端,在编码使能时,使其工作,在没有编码请求时,关闭计数器。 TX_en encoding enable signal connected to the first counter 12 and second counter enable input 11, is enabled when coding to make it work, in the absence of a code request to close the counter. 第一计数器11和第二计数器12的复位信号为Cnt_Clr,当编码状态机3发生状态跳变时,编码状态机3使能Cnt_Clr信号,使第一计数器11和第二计数器12复位,从而在下一个状态可利用这两个计数器重新计数。 A reset signal the first counter 11 and second counter 12 is Cnt_Clr, when the encoding unit 3 state transition occurs, the state machine 3 coding Cnt_Clr enable signal, the first counter 11 and second counter 12 is reset to the next state may be utilized both counters count again.

[0019] 在介绍编码模式选择电路2之前,先介绍本发明提到的六种编码模式: [0019] The selection circuit 2 before introducing the coding mode, the coding mode introduce six kinds mentioned in the present invention:

对单副载波高速模式来说,其帧头(SOF)包含三个部分:非调制时间56. 64 μ S、频率为fc/32 (423. 75kHz)的M个脉冲、逻辑1以非调制时间18. 88 μ s开始,接着是频率为fc/32 (423. 75kHz)的8 个脉冲。 Single subcarrier high speed mode, its header (SOF) consists of three parts: a non-modulation time 56. 64 μ S, a frequency of fc / 32 (423. 75kHz) of M pulses, a logical 1 to a non-modulation time 18. 88 μ s starts, followed by a frequency of fc / 32 (423. 75kHz) 8 pulses.

[0020] 对单副载波低速模式来说,其帧头(SOF)的三个部分分别是单副载波高速模式时间的4倍,第一部分非调制时间是226. 56 μ s,第二部分是96脉冲,第三部分逻辑1开始是75. 52 μ s的非调制时间,接着是32个脉冲。 [0020] The low speed mode of the single subcarrier, the three partially header (SOF), respectively, four times the single sub-carrier high speed mode time, a first portion of the non-modulation time 226. 56 μ s, the second part pulse 96, the third portion is non-modulated logic begins a time 75. 52 μ s, followed by 32 pulses.

[0021] 单副载波双速模式SOF的时间是各自高低速模式时间的二分之一。 [0021] double speed mode of the single subcarrier SOF is one-half of the time each time the high speed mode.

[0022] 双副载波高速模式的帧头(SOF)也包括三个部分:频率为fc/观的27个脉冲、频率为fc/32的M个脉冲、逻辑1以频率为fc/28的9个脉冲开始,接着是频率为fc/32的8个脉冲。 Header [0022] bis subcarrier high speed mode (SOF) also consists of three parts: a pulse frequency of 27 fc / concept, a frequency of M pulses fc / 32, the logic 1 frequency of fc / 9 28 start pulse followed by a frequency of fc / 32 8 pulses. 双副载波低速模式SOF的三个部分的时间是双副载波高速模式的4倍,分别是: 频率为fc/28的108个脉冲、频率为fc/32的96个脉冲、逻辑1以频率为fc/28的36个脉冲开始,接着是频率为fc/32的32个脉冲。 Time three part double speed mode SOF subcarriers is four times subcarrier double speed mode, namely: a pulse frequency of 108 fc / 28, the frequency of 96 pulses fc / 32, the logic 1 frequency 36 pulses fc / 28 starts, followed by a frequency of fc / 32 32 pulses.

[0023] 上述六种模式的帧尾(EOF)是和各自的帧头(SOF)是首尾对应的,即它们SOF的第一部分是EOF的第三部分、SOF的第三部分是EOF的第一部分。 [0023] The above-described six patterns of the frame end (EOF) is the header and the respective (SOF) is the corresponding end to end, i.e., a first portion thereof SOF EOF is the third part, the third part of the SOF is the first portion of the EOF .

[0024] VICC到VCD的数据编码采用位编码。 [0024] VICC VCD data encoded using bit encoding. 对单副载波模式来说,逻辑0以频率为fc/32 (约423. 75kHz)的8个(高速模式)或32个(低速模式)脉冲开始,接着是非调制时间256/fc (高速模式)或lOM/fc (低速模式)。 Single subcarrier pattern, a logic 0 at frequency fc / 32 (about 423. 75kHz) 8 (high speed mode) or 32 (low speed mode) start pulse followed by a non-modulation time 256 / fc (high-speed mode) or lOM / fc (low-speed mode). 单副载波双速模式的逻辑0开始是4个(双高速模式)或16个(双低速模式)频率为fc/32的脉冲,接着是非调制时间U8/fc (双高速模式)或512/fc (双低速模式)。 Logic zero single sub-carrier, double-speed mode is four (double speed) or 16 (two low speed mode) frequency is fc / 32 pulse, followed by a non-modulation time U8 / fc (double speed) or 512 / fc (dual low-speed mode). 对双副载波,逻辑0以频率为fc/32的8个(高速模式)或32个(低速模式)脉冲开始,接着是频率为fc/28的9个(高速模式)或36个(低速模式)脉冲。 Double subcarriers, logic 0 at frequency fc / 32 8 (high speed mode) or 32 (low speed mode) start of the pulse, followed by a frequency of 9 (high speed mode) fc / 28 or 36 (low-speed mode )pulse. 逻辑1和各自模式的逻辑0相对应,即逻辑0的第一部分是逻辑1的第二部分,而其第二部分是逻辑1的第一部分。 Logic 1 and logic 0 corresponding to the respective mode, i.e. the first part of the logic 0 is the second part of the logic 1, while the second part is the first part of the logical 1.

[0025]所述编码模式选择电路 2 的输出S0F_12_NUM、S0F_34_NUM、DATA_01、CNT_NUM、 CNT_DATA、cnt接编码状态机的输入端,这些输出信号都是用于区别各种编码模式的信息计数信号。 The [0025] output S0F_12_NUM encoding mode selecting circuit 2, an input terminal S0F_34_NUM, DATA_01, CNT_NUM, CNT_DATA, cnt pick coding state machine, the output signals are used to distinguish between the various count signal coding mode information. 其中,S0F_12_NUM是用于区别单双副载波帧头第一,第二部分高低速模式的副载波计数值,S0F_34_NUM是用于选择单双副载波帧头第三部分高低速模式的副载波计数值。 Wherein, S0F_12_NUM is a first, a second portion of the count value of the difference between odd and even sub-carriers sub-carriers of the header high-speed mode, S0F_34_NUM subcarrier count value for odd and even sub-carriers selected header of the third portion of the high speed mode . DATA_01是用于选择单双副载波数据编码速率的计数值。 DATA_01 the count value for selecting single or double data subcarrier coding rate. CNT_NUM、CNT_DATA用于对齐波形的计数值。 CNT_NUM, CNT_DATA aligned waveform count value. cnt用于选择各种编码模式的副载波类型的计数值,可以为cnt32或cnt28。 cnt for selecting various coding modes of the count value of the sub-carrier type, or may be cnt32 cnt28. 当双速选择信号fast_inv_read为高电平且单双副载波信号sub_Carrier_f lag为低电平时, When the selection signal fast_inv_read two-speed is high and when the odd and even sub-carrier signal is low sub_Carrier_f lag,

5若速率选择信号data_rate_flag为“1”时,即选择单副载波双高速模式,则S0F_12_NUM值为12,S0F_34_NUM值为4 ;若速率选择信号data_rate_flag为“0”时,即选择单副载双波低速模式,则S0F_12_NUM值为48,S0F_34_NUM值为16。 5 If data_rate_flag rate selection signal is "1", i.e., select a single subcarrier double speed mode, the value S0F_12_NUM 12, S0F_34_NUM value of 4; data_rate_flag if the rate selection signal is "0", i.e., select a single sub-carrier wave bis low-speed mode, the value S0F_12_NUM 48, S0F_34_NUM value of 16. 当双速选择信号fast_inv_read和单双副载波信号sub_carrier_flag皆为低电平时,若速率选择信号data_rate_flag为高电平时,即选择单副载波高速模式,S0F_12_NUM值为24,S0F_34_NUM值为8 ;若速率选择信号data_rate_flag为低电平时,即选择单副载波低速模式,S0F_12_NUM值为96,S0F_34_NUM 值为32。 When the two-speed and the odd and even select signals fast_inv_read sub_carrier_flag subcarrier signals are all low level, if the selection signal data_rate_flag rate is high, i.e., select a single sub-carrier high-speed mode, S0F_12_NUM value 24, S0F_34_NUM is 8; if rate selection data_rate_flag signal is low, i.e. low speed mode select single subcarrier, S0F_12_NUM value 96, S0F_34_NUM is 32. 当双速选择信号fast_inv_read为低电平且单双副载波选择信号sub_Carrier_ flag为高电平时,若速率选择信号data_rate_flag为高电平时,即选择双副载波高速模式,S0F_12_NUM值为27,S0F_34_NUM值为9 ;若速率选择信号data_rate_f lag为低电平时, 即选择双副载波低速模式,S0F_12_NUM值为108,S0F_34_NUM值为36。 When the two-speed is low and the selection signal fast_inv_read odd and even sub-carriers sub_Carrier_ flag selection signal is high, if selection signal data_rate_flag rate is high, i.e., subcarrier selection double speed mode, S0F_12_NUM value 27, S0F_34_NUM value 9; data_rate_f lag when the rate selection signal is low, i.e. low speed mode select bis subcarrier, S0F_12_NUM value 108, S0F_34_NUM value of 36.

[0026] 所述编码状态机3输入端连接编码模式选择电路2的输出端。 The [0026] 3 input of the encoder state machine connected to the output terminal of the encoding mode selection circuit 2. 编码状态机3的输出为控制信号dout_r、计数器复位信号Cnt_Clr、帧编码结束信号tX_0Ver、字节编码结束信号tX_empty、副载波计数信号fs_nUm。 The state machine 3 outputs the encoded control signal is dout_r, the counter reset signal Cnt_Clr, frame coding end signal tX_0Ver, byte coding end signal tX_empty, subcarrier count signal fs_nUm. 在编码状态机3的每个状态,当cnt计数到7时,副载波计数信号fS_num加1。 Each encoder state machine in state 3, when the count cnt to 7, fS_num subcarrier count signal is incremented. 参照图3,当编码状态机3处于S0F_1状态时,判断副载波计数信号fs_num的值是否为S0F_12_NUM,如果副载波计数信号fs_num值为S0F_12_NUM,帧尾输出控制信号eof_Start (该信号为帧尾输出控制信号,即数据编码完成后,该信号置为高电平,帧尾EOF开始输出)为低电平并且cnt的值为CNT_NUM时,状态机跳转到S0F_2状态, 否则就一直处于S0F_1状态,直到条件满足。 Referring to FIG 3, when the encoder is in state 3 S0F_1 state machine, determining the value of a subcarrier whether the count signal fs_num S0F_12_NUM, if the value of the sub-carrier count signal fs_num S0F_12_NUM, end of frame output control signal eof_Start (the frame end signal to the output control signal, i.e., after the completion of data encoding, the signal is asserted, and starts outputting the EOF end of frame) is low and the value of cnt CNT_NUM the state machine jumps to state S0F_2, or has been in S0F_1 until conditions are met. 当编码状态信号enCOder_State值为S0F_2, 即编码状态机3处于S0F_2状态时,判断副载波计数信号fs_num是否为S0F_12_NUM,cnt是否为CNT_NUM,若条件满足,且e0f_Start为低电平,状态跳转到S0F_3,否则一直等待直到条件满足。 When the coding state value S0F_2 enCOder_State signal, i.e., the state machine 3 is S0F_2 coding state, it is determined whether the sub-carrier count signal is fs_num S0F_12_NUM, cnt whether CNT_NUM, if the condition is satisfied, and e0f_Start is low, state transition to S0F_3 otherwise, wait until conditions are met. 当处于S0F_3状态时,判断副载波计数信号fs_num是否为SF0_34_NUM,cnt是否为CNT_NUM,若条件满足且e0f_Start为低电平状态跳转到S0F_4。 When in S0F_3 state, it is determined whether the sub-carrier count signal is fs_num SF0_34_NUM, cnt whether CNT_NUM, if the condition is satisfied and to jump to the low state e0f_Start S0F_4. 在S0F_4状态,开始装载编码数据tX_data。 In S0F_4 state to start loading the encoded data tX_data. 当编码状态机3处于数据编码状态时,数据比特信息输出给dout_r, 作为编码输出控制电路5的控制信号。 When the state machine coded data encoded in the state 3, the data output to the bit information dout_r, as encoded outputs a control signal to control circuit 5. 当编码状态机3处于数据编码状态DATA_1时,判断副载波计数信号fs_num是否为DATA_01,cnt是否为CNT_DATA,若满足,则跳转到数据编码状态DATA_2。 When the encoded data encoded in the state machine 3 DATA_1 state, it determines whether the sub-carrier count signal is fs_num DATA_01, cnt whether CNT_DATA, if yes, then jump to the state data encoding DATA_2. 在数据编码状态DATA_2,判断字节编码控制电路4输出的数据比特信息cnt_ bit是否为7,若为7表示一个字节的数据编码完成,发出字节编码结束信号tX_empty,通知发送下一字节编码数据,在下一个时钟周期,字节编码控制电路4判断数据装载信号tx_ load是否为高电平,若为高电平则接收编码数据,若为低,向编码状态机3发送帧尾输出控制信号eof_start,表示一帧数据编码完成,编码状态机转向S0F_4,开始发送帧尾EOF信息。 DATA_2 coding state data, the coding control circuit 4 determines the byte data outputted bit information whether cnt_ bit 7, if the encoded data is 7 represents a complete byte, byte coding end signal issued TX_EMPTY, notification sending the next byte coded data in the next clock cycle, the control byte encoding circuit 4 determines whether a data load signal tx_ load is high, if the encoded data is received is high, if it is low, the output end of transmission frame to the coding control state machine 3 signal eof_start, showing a data-encoded, encoder state machine steering S0F_4, EOF end of frame transmission start information. 帧尾EOF与帧头SOF的数据正好相反,如前所述,SOF的第一部分是EOF的第三部分、 SOF的第三部分是EOF的第一部分,因此编码状态机3帧头SOF和帧尾EOF状态切换正好首尾对应,因而节省了系统的功耗和芯片面积。 End of frame header SOF and EOF data contrary, as described above, the first portion of SOF EOF is the third part, the third part of the SOF is the first portion of EOF, so the encoding state machine frame header SOF and the frame end 3 EOF end-state switching corresponds exactly, thus saving chip area and power systems. 当状态编码机3按逆序执行完帧尾EOF的状态转换后,则转入OVER状态,表示帧编码结束,发出帧编码结束信号tX_0Ver,进一步转入IDLE状态等待下一帧数据编码。 When the state machine coded EOF end of frame 3 executing the reverse order of the state transition, the process proceeds to OVER state indicates the end of frame coding, the coding end signal frame sent tX_0Ver, further into the IDLE state waiting for the next frame of data encoding.

[0027] 参照图2,所述编码输出控制电路5输入端分别连接有系统时钟第一分频信号clk28、系统时钟第二分频信号clk32、编码使能信号tX_en及单双副载波选择信号sub_ Carrier_flag,控制端接收来自编码状态机3输出的控制信号doU_r。 [0027] Referring to FIG. 2, the encoder 5 outputs the control input of the circuit are connected to a first system clock frequency divided signal clk28, the second system clock frequency divided signal clk32, tX_en encoding enable signal and the odd and even sub-carrier selection signal sub_ Carrier_flag, a control terminal for receiving a control signal from the state machine 3 doU_r encoded output. 所述编码输出控制电5包括一三输入与非门II,系统时钟第一分频信号clk28、编码使能信号tX_en和单双副载波选择信号Sub_carrier_flag经所述三输入与非门Il连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门14,所述二输入与非门14的一路信号来自系统时钟第二分频信号clk32、另一路为单双副载波选择信号SUb_carrier_flag取反后与编码使能信号tX_en相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机3输出的控制信号doU_r。 The encoded output control circuit 5 comprises a three-input NAND gate II, a first frequency-divided system clock signal clk28, and the encoded odd and even enable signal tX_en Sub_carrier_flag subcarrier selection signal via the three-input NAND gate is connected to a Il multiplexer, the other input terminal of the multiplexer is connected to a twelve-input NAND gate 14, one signal of the two-input NAND gate 14 from a system clock of a second frequency divided signal clk32, another way for the odd and even sub-carrier signal is a selection signal SUb_carrier_flag tX_en encoding enable signal or inverted phase was obtained, the control signal doU_r selection control signal input terminal of the multiplexer is unit 3 from the output coding state. 多路选择器的输出信号经过反相器15后输出为已编码数据dout。 Multiplexer output signal through the inverter 15 outputs the encoded data dout. 当单双副载波选择信号sub_carrier_flag为低电平时,控制信号dout_r为低电平时,编码输出dout没有调制信息;控制信号dout_r为高电平时,编码输出dout输出系统时钟第二分频信号clk32。 When the odd and even sub-carrier sub_carrier_flag selection signal is low, the control signal dout_r is low, no modulation coding information output dout; dout_r control signal is high, the encoded output dout output system clock of the second frequency divided signal clk32. 当单双副载波选择信号SUb_carrier_flag为高电平时,控制信号高电平时,编码输出dout输出系统时钟第二分频信号clk32 ;当控制信号dout_r为低电平时,编码输出dout为系统时钟第一分频信号clk28。 When the odd and even sub-carrier selection signal SUb_carrier_flag is high, the control signal is high level, the system clock outputs encoded output dout second frequency divided signal clk32; dout_r when the control signal is low, the encoded output dout is first divided system clock frequency signal clk28.

[0028] 本发明所述字节编码控制电路4采用位编码,接收来自编码状态机3的副载波计数信号fs_nUm并输出帧尾输出控制信号eof_Start给编码状态机3。 [0028] The present invention uses byte coding control circuit 4-bit code from the received subcarrier coding state machine 3 fs_nUm count signal and outputs the output control signal eof_Start end of frame to the coding state machine 3. 所述编码状态机3根据来自编码模式输出电路2的所述区别多种编码模式的计数信号和所述帧尾输出控制信号eof_start切换状态。 More than three kinds of the encoded state machine count signal encoding mode and said output control signal eof_start end of frame switching circuit state based on the difference between the output from the coding mode 2.

[0029] 本发明编码电路支持支持多种编码模式编码,包括单副载波高速、单副载波低速、 单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 [0029] The present invention supports coding circuit support multiple coding mode, sub-carrier comprises a single high-speed, low-speed single subcarrier, subcarrier single double-speed, low-speed double single subcarrier, subcarrier double-speed, low-bis subcarriers. 第一计数器cnU8在单副载波模式下停止工作,第一计数器cnU8和第二计数器cnt32在双副载波模式下分时工作,节省了系统的编码功耗,并且本发明帧头SOF和帧尾EOF在同一编码状态机的不同状态工作顺序下实现,首尾对应,节省了芯片的面积。 Stopping the first counter cnU8 subcarrier in single mode operation, the first counter and the second counter cnt32 cnU8 sharing subcarrier operating in dual mode, power saving coding system of the present invention and header SOF and EOF end of frame in different states of operation sequence encoding the same state machine implementation, the corresponding end to end, to save chip area.

[0030] 以上是对本发明的较佳实施进行了具体说明,但本发明创造并不限于所述实施例,熟悉本领域的技术人员在不违背本发明精神的前提下还可以作出种种的等同变形或替换,这些等同的变形或替换均包含在本申请权利要求所限定的范围内。 [0030] The foregoing is the preferred embodiment of the present invention have been specifically described, but the present invention is not limited to the creation of embodiments, those skilled in the art without departing from the spirit of the present invention, various modification may be made of equivalents or alternatively, such equivalent modifications or substitutions are included in the present application within the scope defined by the claims.

Claims (8)

  1. 1. 一种支持单双副载波和高低速率的RFID标签芯片编码电路,包括计数器单元(1)、 编码模式选择电路(2)、编码状态机(3)、编码输出控制电路(5)和字节编码控制电路(4), 所述计数器单元(1)接收系统编码时钟信号(cllencoder)并输出计数信号(cnt28、 cnt32)给编码模式选择电路(2),其特征在于:所述编码模式选择电路(2)分别连接有双速选择信号(fast_inv_read)、单双副载波选择信号(sub_carrier_flag)及速率选择信号(data_rate_flag),所述编码模式选择电路(2)输出用于区别多种编码模式的计数信号给编码状态机(3 ),所述编码状态机(3 )还接收来自字节编码控制电路(4 )的比特信息(cnt_ bit)并输出控制信号(doU_r)给编码输出控制电路(5),所述编码输出控制电路(5)与RFID标签芯片的模拟前端连接。 An odd and even subcarriers and the level of support of RFID tag chip rate encoding circuit comprises a counter unit (a), the encoding mode selection circuit (2), coding state machine (3), the encoded output control circuit (5) and a word the coding control circuit section (4), said counter unit (1) receives the encoded system clock signal (cllencoder) and outputs a count signal (cnt28, cnt32) to the coding mode selection circuit (2), characterized in that: said coding mode selection circuit (2) are connected to a double speed select signal (fast_inv_read), single and double subcarrier selection signal (sub_carrier_flag) and the rate selection signal (data_rate_flag), said encoding mode selection circuit (2) outputs a difference between a plurality of coding modes count signal to the coding state machine (3), the coding state machine (3) also receives a byte code from the control circuit (4) bits of information (cnt_ bit) and outputs a control signal (doU_r) to the code output control circuit (5 ), the encoded output control circuit (5) connected to the analog front-end chip of the RFID tag.
  2. 2.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述计数器单元(1)包括第一计数器(11)和第二计数器(12),系统时钟信号(elk)和编码使能信号(tX_en)相与后分别与第一计数器(11)和第二计数器(12)的输入端连接,所述第一、第二计数器(11、1幻的复位端还连接有来自编码状态机C3)的计数器复位信号(cnt_Clr),所述第一、第二计数器输出的计数信号(cnt28、cnt3》分别传输给所述编码模式选择电路O)的输入端。 The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag according to claim 1, wherein: said counter means (1) comprises a first counter (11) and a second counter (12 ), the system clock signal (Elk) encoding enable signal (TX_EN) phase with the first counter (11) and a second counter (12) connected to the input of the first, second counter (11, magic reset terminal 1 is also connected to the counter reset signal (cnt_Clr) from the encoder state machine C3), the first, the second counter output count signal (cnt28, cnt3 "are respectively transmitted to said coding mode selection circuit O) input.
  3. 3.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路,其特征在于:所述编码输出控制电路(5)输入端分别连接有系统时钟第一分频信号(C1M8)、系统时钟第二分频信号(clk32)、编码使能信号(tX_en)及单双副载波选择信号(SUb_carrier_flag),控制端接收来自编码状态机(3)输出的控制信号(doU_r)。 The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag according to claim 1, wherein: said encoded input output control circuit (5) are respectively connected to a first system clock divider signal (C1M8), a second system clock frequency divided signal (clk32), encoding enable signal (TX_EN), and odd and even sub-carrier selection signal (SUb_carrier_flag), a control signal (doU_r terminal receives the output from the encoder state machine (3) ).
  4. 4.根据权利要求3所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码输出控制电路(¾包括一三输入与非门(II),系统时钟第一分频信号(clM8)、编码使能信号(tX_en)和单双副载波选择信号(SUb_carrier_flag)经所述三输入与非门(Il)连接有一多路选择器,所述多路选择器的另一输入端连接有一二输入与非门(14),所述二输入与非门(14)的一路信号来自系统时钟第二分频信号(clk32)、另一路为单双副载波选择信号(sub_carrier_flag)取反后与编码使能信号(tX_en)相或后得到的信号,所述多路选择器的选择控制端的输入信号为来自编码状态机C3)输出的控制信号(dou_r)ο The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag according to claim 3, wherein: said encoder output control circuit (¾ comprises a three-input NAND gate (II), the system first clock frequency divided signal (clM8), encoding enable signal (TX_EN), and odd and even sub-carrier selection signal (SUb_carrier_flag) via the three-input NAND gate (Il) connected with a multiplexer, said multiplexer the other input terminal of the selector is connected to twelve-input NAND gate (14), the two-input NAND gate (14) all the way to the system clock signal from the second frequency divided signal (clk32), another way for the odd and even sub signal carrier selection signal (sub_carrier_flag) encoding so that the inverted enable signal (TX_EN) phase or obtained, the selection control terminal of the input signal of the multiplexer is the output from the encoder state machine C3) a control signal (dou_r) ο
  5. 5.根据权利要求1所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述字节编码控制电路(4)采用位编码,接收来自编码状态机(¾的副载波计数信号(fS_num)并输出帧尾输出控制信号(eof_Start)给编码状态机(3)。 The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag according to claim 1, wherein: said encoded byte control circuit (4) bit code, the state machine receives from the encoder ( ¾ subcarrier count signal (fS_num) and outputs a control signal output end of frame (eof_Start) to the encoder state machine (3).
  6. 6.根据权利要求5所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码状态机C3)根据来自编码模式选择电路O)的所述区别多种编码模式的计数信号和所述帧尾输出控制信号(eof_Start)切换状态。 The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag as claimed in claim 5, wherein: said encoded state machine C3) according to the difference between multiple coding mode selection circuit from O), count signal encoding modes and the end of frame output control signal (eof_Start) switching state.
  7. 7.根据权利要求6所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码状态机(3)的状态包括帧头状态、数据状态和帧尾状态,所述帧头状态的切换与帧尾状态的切换首尾对应。 The odd and even sub-carriers for supporting the high and low rate encoding circuit chip of the RFID tag according to claim 6, wherein: said coding state state machine (3) comprises a frame header status, data status and end of frame end-state switch switches the state of the header end of the frame corresponding to the state.
  8. 8.根据权利要求7所述的一种支持单双副载波和高低速率的RFID标签芯片编码电路, 其特征在于:所述编码模式选择电路(¾支持多种编码模式编码,包括单副载波高速、单副载波低速、单副载波双高速、单副载波双低速、双副载波高速、双副载波低速。 8. The odd and even sub-carriers for supporting high and low rate encoding circuit chip of the RFID tag according to claim 7, wherein: said coding mode selection circuit (¾ support multiple coding mode, sub-carrier comprises a single high-speed , low single subcarrier, subcarrier single double-speed, low-speed double single subcarrier, subcarrier double-speed, low-bis subcarriers.
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CN103647558A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Manchester encoder circuit

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CN1788293A (en) * 2003-06-05 2006-06-14 摩托罗拉公司 Subcarrier in an organic RFID semiconductor
CN101299644A (en) * 2008-06-13 2008-11-05 深圳市远望谷信息技术股份有限公司 Antenna channel detection method based on six-port circuit
US20090109003A1 (en) * 2007-09-24 2009-04-30 Cooper Tire & Rubber Cumpany Automatic antenna tuner system for RFID

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CN1788293A (en) * 2003-06-05 2006-06-14 摩托罗拉公司 Subcarrier in an organic RFID semiconductor
US20090109003A1 (en) * 2007-09-24 2009-04-30 Cooper Tire & Rubber Cumpany Automatic antenna tuner system for RFID
CN101299644A (en) * 2008-06-13 2008-11-05 深圳市远望谷信息技术股份有限公司 Antenna channel detection method based on six-port circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103647558A (en) * 2013-12-03 2014-03-19 北京中电华大电子设计有限责任公司 Manchester encoder circuit

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