CN107659272A - A kind of new up-converter circuit - Google Patents
A kind of new up-converter circuit Download PDFInfo
- Publication number
- CN107659272A CN107659272A CN201710860957.7A CN201710860957A CN107659272A CN 107659272 A CN107659272 A CN 107659272A CN 201710860957 A CN201710860957 A CN 201710860957A CN 107659272 A CN107659272 A CN 107659272A
- Authority
- CN
- China
- Prior art keywords
- fpga
- roads
- new
- converter circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a kind of new up-converter circuit, including AD9862, AD9862 produces I roads and the Q roads signal of base band, the analog signal on I roads and Q roads is input to connection FPGA, the sample rate of baseband signal is improved by FPGA, mixed afterwards with quadrature carrier, output is signally attached to AD9862, and the FPGA is connected on Cypress FX2 control chip.The present invention is effectively combined FPGA and AD9862 AD9862 flexible configuration by FPGA, reduces FGPA processing clock, saves FPGA resource, while also reduces power consumption；The present invention utilizes interpolation device in original sampled signal by inserting new sampled point, so as to improve the sample rate of signal.
Description
Technical field
The invention belongs to up-converter circuit technical field, more particularly, to a kind of new up-converter circuit.
Background technology
Digital Up Convert is in the frequency for move the baseband signal after processing suitable transmission.Baseband portion exports
Digitized data flow to be transmitted in wireless channel, it is necessary to be converted to analog signal.Digital Up Convert module is mainly completed
Work below：First, the signal for being adapted to simulation form to transmit is produced by pulse-shaping filtering；2nd, by numerically becoming after filtering
The frequency mixing module of frequency adds carrier wave and becomes intermediate-freuqncy signal；3rd, analog signal is converted into by D/A converter.
Rate digital signal processing, increase or reduce data signal exactly on the premise of nyquist sampling theorem is met
Sampling rate, to realize the subsequent treatment to signal.Multirate signal processing is to realize the key technology of Digital Up Convert,
It includes two kinds of basic processing methods：Extraction and interpolation.Extraction can reduce sampling rate, be frequently used in up-conversion.Take out
Take be sometimes integral multiple with interpolation or rational fraction times.The purpose of software radio is that use up analog signal can
The early digitlization of energy, the various functions of radio communication are realized with the method for software.
The content of the invention
In view of this, the present invention is directed to propose a kind of new up-converter circuit, up-converter circuit pass through interpolation filter
The sample rate of baseband signal is improved, is mixed afterwards with quadrature carrier, reaches the purpose of up-conversion.
To reach above-mentioned purpose, the technical proposal of the invention is realized in this way：
A kind of new up-converter circuit, including AD9862, AD9862 produce I roads and the Q roads signal of base band, by I roads and Q
The analog signal on road is input to connection FPGA, and the sample rate of baseband signal is improved by FPGA, is mixed afterwards with quadrature carrier
Close, output is signally attached to AD9862, and the FPGA is connected on Cypress FX2 control chip.
Further, the FPGA uses the Cyclone EP1C12 chips of altera corp.
Further, digital analog converter, interpolation device and the wave filter being sequentially connected, the interpolation are provided with the FPGA
Device is directly additionally provided with frequency mixer NCO with wave filter.
Further, the AD9862 provides 2 High Speed Analog digitizers, per symbol 12bit, 64M symbol/second, 2
Individual high-speed figure simulates converter, and per symbol 14bit, 128M symbol/second, this four passages are connected on FPGA.
Relative to prior art, a kind of new up-converter circuit of the present invention has the advantage that：
(1) present invention is effectively combined FPGA and AD9862 AD9862 flexible configuration by FPGA, reduces
FGPA processing clock, saves FPGA resource, while also reduces power consumption；
(2) present invention utilizes interpolation device in original sampled signal by inserting new sampled point, so as to improve signal
Sample rate.
Brief description of the drawings
The accompanying drawing for forming the part of the present invention is used for providing a further understanding of the present invention, schematic reality of the invention
Apply example and its illustrate to be used to explain the present invention, do not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the overall system design schematic diagram described in the embodiment of the present invention；
Fig. 2 is the Digital Up Convert schematic diagram described in the embodiment of the present invention
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or dark
Show that the device of meaning or element there must be specific orientation, with specific azimuth configuration and operation, thus it is it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " etc. are only used for describing purpose, and it is not intended that instruction or hint phase
To importance or the implicit quantity for indicating indicated technical characteristic.Thus, the feature for defining " first ", " second " etc. can
To express or implicitly include one or more this feature.In the description of the invention, unless otherwise indicated, " multiple "
It is meant that two or more.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, above-mentioned term can be understood by concrete condition
Concrete meaning in the present invention.
Describe the present invention in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
As shown in Figure 1, 2, a kind of new up-converter circuit, including AD9862, AD9862 produce the I roads and Q roads of base band
Signal, by the analog signal on I roads and Q roads be input to connection FPGA, by FPGA improve baseband signal sample rate, afterwards with just
Carrier wave is handed over to be mixed, output is signally attached to AD9862, and the FPGA is connected on Cypress FX2 control chip.
The FPGA uses the Cyclone EP1C12 chips of altera corp.
Digital analog converter, interpolation device and the wave filter being sequentially connected, the interpolation device and filtering are provided with the FPGA
Device is directly additionally provided with frequency mixer NCO.
The AD9862 provides 2 High Speed Analog digitizers, per symbol 12bit, 64M symbol/second, 2 high speed numbers
Type matrix intends converter, and per symbol 14bit, 128M symbol/second, this four passages are connected on FPGA.
The present invention is that the sample rate of baseband signal is improved by interpolation filter, is mixed, reached with quadrature carrier afterwards
To the purpose of up-conversion.Its core is interpolation device and digital controlled oscillator (NCO).Interpolation device is mainly in original sampled signal
In by inserting new sampled point, so as to improve the sample rate of signal.
AD9862 and FPGA are combined as shown in Fig. 2 by FPGA to AD9862's by the present invention in signal up-conversion
Together with flexible configuration makes FPGA be effectively combined with AD9862.FGPA processing clock is reduced, saves FPGA resource,
Also reduce power consumption simultaneously.
When the present invention realizes Digital Up Convert using FPGA, write first in Quartus II according to design requirement
Verilog HDL programs, are downloaded in FPGA afterwards, realize and AD9862 register is configured.In IF digital process
In, it can more easily realize and numerically become by the specific requirement for meeting to design to the flexible configuration of AD9862 registers
Frequently.By being effectively combined for AD9862 and FPGA, the function of Digital Up Convert is realized.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements made etc., should be included in the scope of the protection with principle.
Claims (4)
- A kind of 1. new up-converter circuit, it is characterised in that：Including AD9862, AD9862 produces I roads and the Q roads letter of base band Number, by the analog signal on I roads and Q roads be input to connection FPGA, by FPGA improve baseband signal sample rate, afterwards with it is orthogonal Carrier wave is mixed, and output is signally attached to AD9862, and the FPGA is connected on Cypress FX2 control chip.
- A kind of 2. new up-converter circuit according to claim 1, it is characterised in that：The FPGA is public using Altera The Cyclone EP1C12 chips of department.
- A kind of 3. new up-converter circuit according to claim 1, it is characterised in that：It is provided with the FPGA and connects successively Digital analog converter, interpolation device and the wave filter connect, the interpolation device are directly additionally provided with frequency mixer NCO with wave filter.
- A kind of 4. new up-converter circuit according to claim 1, it is characterised in that：The AD9862 provides 2 height Fast analog to digital converter, per symbol 12bit, 64M symbol/second, 2 high-speed figures simulate converter, per symbol 14bit, 128M symbols/second, this four passages are connected on FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860957.7A CN107659272A (en) | 2017-09-21 | 2017-09-21 | A kind of new up-converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860957.7A CN107659272A (en) | 2017-09-21 | 2017-09-21 | A kind of new up-converter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107659272A true CN107659272A (en) | 2018-02-02 |
Family
ID=61130779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710860957.7A Pending CN107659272A (en) | 2017-09-21 | 2017-09-21 | A kind of new up-converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107659272A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504972A (en) * | 2019-08-30 | 2019-11-26 | 航天恒星科技有限公司 | A kind of sampling rate converting method based on FPGA, device and digital-analog convertion method, device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1283057A (en) * | 1999-08-26 | 2001-02-07 | 深圳市中兴通讯股份有限公司 | Single-carrier-frequeney transmitter of GSM base station |
| CN101197606A (en) * | 2006-12-04 | 2008-06-11 | 京信通信技术(广州)有限公司 | Digital intermediate frequency conversion method and system used in repeater |
| CN101349741A (en) * | 2008-08-29 | 2009-01-21 | 西安电子科技大学 | Phased array digital multi-beam forming machine for electron reconnaissance |
| CN201533308U (en) * | 2009-10-30 | 2010-07-21 | 陕西烽火宏声科技有限责任公司 | Medium-long wave digital spread-spectrum communication apparatus |
| CN102590829A (en) * | 2012-03-14 | 2012-07-18 | 西安电子科技大学 | Complete self-adaptive notch filter for satellite navigation system and notch filtering method of same |
| CN102694607A (en) * | 2011-03-25 | 2012-09-26 | 北京海曼无限信息技术有限公司 | Networked software radio signal monitoring method aiming at mobile interference source and system thereof |
| CN103001586A (en) * | 2012-12-12 | 2013-03-27 | 上海航天测控通信研究所 | Broadband two-channel digital down converter |
| CN206331109U (en) * | 2016-12-13 | 2017-07-14 | 九江精密测试技术研究所 | A kind of radar range finding circuit |
-
2017
- 2017-09-21 CN CN201710860957.7A patent/CN107659272A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1283057A (en) * | 1999-08-26 | 2001-02-07 | 深圳市中兴通讯股份有限公司 | Single-carrier-frequeney transmitter of GSM base station |
| CN101197606A (en) * | 2006-12-04 | 2008-06-11 | 京信通信技术(广州)有限公司 | Digital intermediate frequency conversion method and system used in repeater |
| CN101349741A (en) * | 2008-08-29 | 2009-01-21 | 西安电子科技大学 | Phased array digital multi-beam forming machine for electron reconnaissance |
| CN201533308U (en) * | 2009-10-30 | 2010-07-21 | 陕西烽火宏声科技有限责任公司 | Medium-long wave digital spread-spectrum communication apparatus |
| CN102694607A (en) * | 2011-03-25 | 2012-09-26 | 北京海曼无限信息技术有限公司 | Networked software radio signal monitoring method aiming at mobile interference source and system thereof |
| CN102590829A (en) * | 2012-03-14 | 2012-07-18 | 西安电子科技大学 | Complete self-adaptive notch filter for satellite navigation system and notch filtering method of same |
| CN103001586A (en) * | 2012-12-12 | 2013-03-27 | 上海航天测控通信研究所 | Broadband two-channel digital down converter |
| CN206331109U (en) * | 2016-12-13 | 2017-07-14 | 九江精密测试技术研究所 | A kind of radar range finding circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504972A (en) * | 2019-08-30 | 2019-11-26 | 航天恒星科技有限公司 | A kind of sampling rate converting method based on FPGA, device and digital-analog convertion method, device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102798840B (en) | Broadband channelization reception system of radar with external radiation source and FPGA (Field Programmable Gate Array) implementation method | |
| CN107749762A (en) | A kind of multiphase filtering digital channelizing implementation method | |
| CN101945490A (en) | Software radio-based wireless communication system terminal equipment | |
| CN105024650B (en) | Multibeam signals interleaved Digital down conversion method based on ultrahigh speed analog-to-digital conversion | |
| CN103647529A (en) | Multimode signal generating device and signal generating method thereof | |
| CN103905368A (en) | High-speed communication parallel digital modulation method applicable to FPGA achievement | |
| Datta et al. | FPGA implementation of high performance digital down converter for software defined radio | |
| CN201887751U (en) | Software radio development platform | |
| CN107659272A (en) | A kind of new up-converter circuit | |
| CN101594159B (en) | Method and device for digital front-end filtering | |
| CN102063075A (en) | Onboard real-time digital signal processing (DSP) system for intermediate frequency acquisition card | |
| Laddomada et al. | A PC-based software receiver using a novel front-end technology | |
| CN208112611U (en) | A kind of adjustable signal generator of intermediate frequency of signal-to-noise ratio | |
| Muller et al. | A 7-bit 18th order 9.6 GS/s FIR up-sampling filter for high data rate 60-GHz wireless transmitters | |
| CN105634439A (en) | Design method of asynchronous shaping filter | |
| CN103269222B (en) | Implementation method and the device of variable symbol rate vector signal | |
| CN101207593B (en) | System and method for implementing modem intermediate frequency numeralization in wireless communication | |
| Li | Analysis and design of software defined radio | |
| Tiwari | A low power high speed dual data rate acquisition system using FPGA | |
| CN203896321U (en) | Multi-mode signal generating device | |
| Kolankar et al. | A review on FPGA Implementation of Low Power QPSK Modulator by using Hardware Co-Simulation | |
| CN101272209A (en) | Method and equipment for filtering multicenter multiplexing data | |
| CN104301265B (en) | Ultrawide band signal digital quadrature demodulation real-time processing method | |
| CN212785349U (en) | Digital module and modulation-demodulation system for piggyback radio transceiver | |
| S Naghmash | Design and implementation of programmable multi-mode digital modulator for SDR using FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180202 |