CN103001898A - Quad-channel I/Q signal source - Google Patents
Quad-channel I/Q signal source Download PDFInfo
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Abstract
The invention discloses a quad-channel I/Q signal source which comprises a personal computer (PC), a field programmable gate array (FPGA), signal generators and a single chip microcomputer. The quad-channel I/Q signal source is characterized in that the signal generators include an I+ signal generator, an I- signal generator, a Q+ signal generator, and a Q- signal generator, wherein I+ signals output by the I+ signal generator and I- signals output by the I- signal generator are a pair of differential signals; Q+ signals output by the Q+ signal generator and Q- signals output by the Q- signal generator are a pair of differential signals; and signals output by the I+ signal generator and Q+ signals output by the Q+ signal generator are a pair of synchronous orthogonal signals. Each of the signal generators comprises a direct digital synthesizer (DDS) circuit, a frequency-selecting filter amplifier and a direct current bias circuit. The ad-channel I/Q signal source can output four channels of DC-700MHz I+ signals, I- signals Q+ signals and Q- signals, the frequency, the phase and the amplitude of output signals can be directly subjected to program-controlled modification through a PC interface, the operation is simple, the cost is low, the performance is good, and good application prospects are provided.
Description
Technical field
The present invention relates to signal source, be specifically related to four-way i/q signal source.
Background technology
Along with the develop rapidly of modern communications, radar and ECM (Electronic Countermeasures), the integrated modulator of research and development is more and more higher to the signal source index request, and needing the i/q signal incoming frequency is DC～600MHz.But the i/q signal output frequency of the external signal source of selling on the market mostly can't reach this frequency requirement, and expensive, difficult in maintenance.The domestic technical bottleneck that when high-frequency, multiple signals are exported synchronously, runs into.
The signal source of selling on the market adopts built-in base band generator mode, produce i/q signal output, but output frequency is low, does not satisfy the product test requirement.
Summary of the invention
Technical problem to be solved by this invention is to provide four-way i/q signal source.
In order to solve the problems of the technologies described above, technical scheme of the present invention is that a kind of four-way i/q signal source comprises PC, FPGA, signal generator and single-chip microcomputer; Be characterized in: signal generator comprises I+ signal generator, I-signal generator, Q+ signal generator and Q-signal generator; Wherein, the I-signal of the I+ signal of I+ signal generator output and the output of I-signal generator is a pair of differential signal; The Q-signal of the Q+ signal of Q+ signal generator output and the output of Q-signal generator is a pair of differential signal; The Q+ signal of the signal of I+ signal generator output and the output of Q+ signal generator is a pair of synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and dc bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, the phase data control signal, output signal is to described FPGA after carrying out calculation process, control DDS circuit produces frequency and the phase place of signal, initial phase and the frequency of 4 road signals are consistent, and, single-chip microcomputer one judges whether the phase difference of 4 road signals of signal source output meets the demands, when not satisfying, output signal is to described FPGA, adjust the phase place that the DDS circuit produces signal, the phase difference of 4 road signals is met the demands, making I+ signal and I-signal is a pair of differential signal, Q+ signal and Q-signal are a pair of differential signal, and I+ signal and Q+ signal are a pair of synchronized orthogonal signal;
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal is specified the filtering frequency range to 4 road frequency-selective filtering amplifiers for the frequency-selective filtering amplifier respectively, improves the Spurious Free Dynamic Range of output signal; Simultaneously, described single-chip microcomputer two difference output signals are controlled described numerical-control attenuator the signal of receiving are carried out the amplitude adjustment to 4 way controlling attenuation devices; And, single-chip microcomputer two judges whether the amplitude difference of 4 road signals of signal source output satisfies set point, and when not satisfying, output signal is to 4 way controlling attenuation devices, control 4 way controlling attenuation devices and respectively the signal of receiving is carried out the amplitude adjustment, make the amplitude difference of 4 road signals satisfy set point; Improved the IQ signal accuracy of output;
Described FPGA receives the data that single-chip microcomputer one transmits in real time by the shift register of inside, and reset, synchronously, frequency and phase information output to respectively 4 DDS circuit by state machine, 4 DDS circuit output signals of control synchronously, frequency and phase place;
4 described DDS circuit receive FPGA simultaneously by the information of state machine output, receive simultaneously reference clock signal, 4 DDS circuit produce respectively the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal, output to respectively corresponding frequency-selective filtering amplifier;
Described frequency-selective filtering amplifier can be selected filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives respectively the signal of corresponding DDS circuit output, and the signal of receiving is outputed to respectively corresponding numerical-control attenuator after selecting filtering to process under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives respectively the signal of corresponding frequency-selective filtering amplifier output, and is subjected to the control of single-chip microcomputer two output signals, after the signal of receiving is carried out the amplitude adjustment and processes, exports by dc bias circuit respectively;
Each described dc bias circuit receives respectively the signal of corresponding described numerical-control attenuator output, for external equipment provides the direct current biasing output signal.
The present invention adopts PC directly program control, easy to use, directly perceived to the frequency of signal source, phase place, amplitude etc.; By single-chip microcomputer one control FPGA, and then control DDS circuit produces frequency and the phase place of signal, IQ four road signals that the DDS circuit produces pass through four independently frequency-selecting filters, adjustable attenuator and dc bias circuit output, the amplitude of output signal is by single-chip microcomputer two controls, concrete control procedure is: the frequency that receives PC output by single-chip microcomputer one, the phase data control signal, output signal is to described FPGA after carrying out calculation process, control DDS circuit produces frequency and the phase place of signal, and receive frequency and the amplitude data control signal of PCs output by single-chip microcomputer two, after carrying out calculation process, output signal is to 4 road frequency-selective filtering amplifiers and 4 way controlling attenuation devices respectively, specify the filtering frequency range for the frequency-selective filtering amplifier, improve the Spurious Free Dynamic Range of output signal; And control 4 way controlling attenuation devices and respectively the signal of receiving is carried out amplitude control; And single-chip microcomputer one judges whether the phase difference of 4 road signals of signal source output meets the demands, and when not satisfying, output signal is adjusted the phase place that the DDS circuit produces signal to described FPGA, and the phase difference of 4 road signals is met the demands; Single-chip microcomputer two judges whether the amplitude difference of 4 road signals of signal source output satisfies set point, when not satisfying, output signal is controlled 4 way controlling attenuation devices and respectively the signal of receiving is carried out the amplitude adjustment to 4 way controlling attenuation devices respectively, makes the amplitude difference of 4 road signals satisfy set point; Improved the precision of signal source output signal.
A kind of preferred version according to four-way i/q signal of the present invention source is provided with parameter in the described PC interface is set, and is directly program control to frequency, phase place, the amplitude of signal source output signal.
A kind of preferred version according to four-way i/q signal of the present invention source, described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two links to each other with PC by serial ports two and obtains the instruction that PC sends, link to each other with the control end of 4 frequency-selective filtering amplifiers and the control end of 4 numerical-control attenuators respectively by the IO input/output port, for the frequency-selective filtering amplifier is specified the filtering frequency range, and the pad value of control numerical-control attenuator, reach by stepping control signal amplitude, optimize the Spurious Free Dynamic Range target.
A kind of preferred version according to four-way i/q signal of the present invention source, described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer is connected and obtains the instruction of PC transmission with PC by serial ports one, be connected with FPGA by the IO input/output port, and FPGA is sent instruction.
The beneficial effect in four-way i/q signal of the present invention source is: the present invention can export I+ signal, I-signal, Q+ signal and the Q-signal of 4 road DC～700MHz, the Spurious Free Dynamic Range of output signal is wide, the frequency range of output signal is wide, and output signal accuracy is high; And the frequency of output signal, phase place, amplitude all can arrange directly program control and modification of interface, intuitive display, simple to operate by the PC parameter; It is low that the present invention also has a cost, and the characteristics that performance is excellent can be widely used in the fields such as modern communications, radar and electronic countermeasures.
Description of drawings
Fig. 1 is the schematic diagram in four-way i/q signal of the present invention source.
Fig. 2 is DDS circuit control schematic diagram.
Fig. 3 is that the PC parameter arranges the interface schematic diagram.
Fig. 4 is the theory diagram of single-chip microcomputer two.
Fig. 5 is the theory diagram of numerical-control attenuator.
Fig. 6 is the program flow chart of single-chip microcomputer one.
Fig. 7 is the program flow chart of single-chip microcomputer two.
Embodiment
Referring to Fig. 1, a kind of four-way i/q signal source comprises PC, FPGA, signal generator, serial ports one, serial ports two, single-chip microcomputer one and single-chip microcomputer two; Wherein: signal generator comprises I+ signal generator 1, I-signal generator 2, Q+ signal generator 3 and Q-signal generator 4; Wherein, the I-signal of the I+ signal of I+ signal generator 1 output and 2 outputs of I-signal generator is a pair of differential signal; The Q-signal of the Q+ signal of Q+ signal generator 3 outputs and 4 outputs of Q-signal generator is a pair of differential signal; The Q+ signal of the signal of I+ signal generator 1 output and 3 outputs of Q+ signal generator is a pair of synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and dc bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, the phase data control signal, output signal is to described FPGA after carrying out calculation process, control DDS circuit produces frequency and the phase place of signal, initial phase and the frequency of 4 road signals are consistent, and, single-chip microcomputer one judges whether the phase difference of 4 road signals of signal source output meets the demands, when not satisfying, output signal is to described FPGA, adjust the phase place that the DDS circuit produces signal, the phase difference of 4 road signals is met the demands, making I+ signal and I-signal is a pair of differential signal, Q+ signal and Q-signal are a pair of differential signal, and I+ signal and Q+ signal are a pair of synchronized orthogonal signal;
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal is specified the filtering frequency range to 4 road frequency-selective filtering amplifiers for the frequency-selective filtering amplifier respectively, improves the Spurious Free Dynamic Range of output signal; Simultaneously, described single-chip microcomputer two difference output signals are controlled described numerical-control attenuator the signal of receiving are carried out the amplitude adjustment to 4 way controlling attenuation devices; And, single-chip microcomputer two judges whether the amplitude difference of 4 road signals of signal source output satisfies set point, and when not satisfying, output signal is to 4 way controlling attenuation devices, control 4 way controlling attenuation devices and respectively the signal of receiving is carried out the amplitude adjustment, make the amplitude difference of 4 road signals satisfy set point; Improved the IQ signal accuracy of output;
Described FPGA receives the data that single-chip microcomputer one transmits in real time by the shift register of inside, and reset, synchronously, frequency and phase information output to respectively 4 DDS circuit by state machine, 4 DDS circuit output signals of control synchronously, frequency and phase place;
4 described DDS circuit receive FPGA simultaneously by the information of state machine output, receive simultaneously reference clock signal, 4 DDS circuit produce respectively the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal, output to respectively corresponding frequency-selective filtering amplifier;
Described frequency-selective filtering amplifier can be selected filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives respectively the signal of corresponding DDS circuit output, and the signal of receiving is outputed to respectively corresponding numerical-control attenuator after selecting filtering to process under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives respectively the signal of corresponding frequency-selective filtering amplifier output, and is subjected to the control of single-chip microcomputer two output signals, after the signal of receiving is carried out the amplitude adjustment and processes, exports by dc bias circuit respectively;
Each described dc bias circuit receives respectively the signal of corresponding described numerical-control attenuator output, for external equipment provides the direct current biasing output signal.
Referring to Fig. 4, Fig. 5, described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two links to each other with PC by serial ports two and obtains the instruction that PC sends, link to each other with the control end of 4 frequency-selective filtering amplifiers and the control end of 4 numerical-control attenuators respectively by the IO input/output port, for the frequency-selective filtering amplifier is specified the filtering frequency range, and the pad value of control numerical-control attenuator, reach by targets such as 0.5dB stepping control signal amplitude, optimization Spurious Free Dynamic Range.Described single-chip microcomputer two specifically can adopt the single-chip microcomputers such as ATmega8515, ATmega8535, wherein, the PA6 of single-chip microcomputer (AD6), PA7 (AD7) are connected MISO with PB6) end is connected with the control end of 4 frequency-selective filtering amplifiers simultaneously, specify the filtering frequency range for the frequency-selective filtering amplifier, optimize Spurious Free Dynamic Range; The PAO of single-chip microcomputer (AD0) holds with the V1 to V6 of one of them numerical-control attenuator respectively to PA5 (AD5) end and is connected; PCO (A8) is connected with V1 to the V6 end of another numerical-control attenuator wherein respectively to PC5 (A13) end, PBO to PB5 end is connected with V1 to the V6 end of the 3rd numerical-control attenuator wherein respectively, PD2 to PD7 end is connected with V1 to the V6 end of the 4th numerical-control attenuator wherein respectively, the pad value of control numerical-control attenuator reaches by stepping control signal amplitude.
Described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer is connected and obtains the instruction of PC transmission with PC by serial ports one, be connected with FPGA by the IO input/output port, and FPGA is sent instruction, this instruction is sent to the DDS circuit by FPGA, the indexs such as the frequency of control IQ signal output, phase place.Described single-chip microcomputer one can adopt the single-chip microcomputers such as 89C2051, and wherein, the DDS circuit can adopt the DS875 cake core; FPGA can adopt the EP1C6F256C6 type.
Referring to Fig. 5, the minimum control precision of numerical-control attenuator is 0.5dB, 6 control words; Can adopt HMC472LP4 numerical-control attenuator chip.
Dc bias circuit can adopt the JEBT_4R2GW chip.
Described frequency-selective filtering amplifier requires the centre frequency frequency deviation 20MHz Out-of-band rejection index of each frequency range greater than 40dB, and squareness factor is less than 1.2, and passband fluctuation is less than 1dB, and three dB bandwidth is greater than 10MHz.
During implementation, because signal source need to be exported 4 tunnel frequencies simultaneously up to the I/Q orthogonal signalling of 700MHz, reference clock signal adopts 2800MHZ; Be the I/Q orthogonal signalling of 600MHz such as output signal frequency, reference clock signal adopts 2000MHZ; And 4 road signals of output are synchronous, frequency is identical, phase place is adjustable separately, to this, adopt based on the DDS frequency synthesis technique, to reference edge and FPGA clock common source, frequency and the phase place of signal source controlled separately, realize that 4 DDS chips export synchronously.
Because frequency control word and the phase control words of DDS chip are the concurrent working mode, the control pin that needs is many, in order to realize the effective control to frequency and phase place, uses FPGA the DDS chip to be controlled in real time DDS control chart such as Fig. 2.
Referring to Fig. 3, at PC, adopt the PC interface software of Delphi language development, the user can arrange the information such as frequency that the interface directly arranges output signal, phase place, amplitude in the PC parameter, PC sends to single-chip microcomputer one and single-chip microcomputer two through serial ports with relevant information, power supply, frequency, phase place, amplitude to signal source are directly program control, and intuitive display is easy to use.
The present invention receives the order of PC by single-chip microcomputer one, and reset, synchronously, the information such as frequency and phase place send to FPGA, FPGA receives the data that single-chip microcomputer transmits in real time by the shift register of inside, and reset, synchronously, the information exchanges such as frequency and the phase place mode of crossing state machine controls DDS output orthogonal signal and differential signal, its single-chip microcomputer one program flow diagram is as shown in Figure 6.
Concrete control flow is: IQ four road signals are by being total to reference source to four DDS, the initial phase that realizes four tunnel output signals is consistent, and the signal phase on each road all can be controlled separately by PC, during control, whether the phase difference of at first determining I+ signal and Q+ signal satisfies 89 °～91 °, if do not satisfy, adjust Q+ signal output phase, the phase difference of I+ signal and Q+ signal is met the demands, and then judge whether the phase difference of adjusting between I+ signal and the I-signal satisfies 179 °～180 °, if do not satisfy, adjust I-signal output phase, the phase difference of I-signal and I+ signal is met the demands, judge again whether the phase difference between Q+ signal and the Q-signal satisfies 179 °～180 °, if do not satisfy, adjust Q-signal output phase, the phase difference of Q-signal and Q+ signal is met the demands, finally realize the output of signal IQ quadrature.
The state machine of FPGA is divided into 4 states, when state machine is in reset mode, and the circular wait enabling signal, in case enabling signal is effective, state machine is started working.State machine part control routine is as follows:
Single-chip microcomputer two receives the PC order, and frequency-selecting filter and programmable attenuator are controlled, and its amplitude control program flow process as shown in Figure 7.
The major control flow process is: adjust the attenuated output signal amplitude; Be that the frequency-selective filtering amplifier is specified the filtering frequency range according to output signal frequency; Judge that whether the amplitude difference of I+ signal and Q+ signal is less than 0.5dB, if do not satisfy, adjust Q+ signal output amplitude, the amplitude difference of I+ signal and Q+ signal is met the demands, and then judge whether the amplitude difference of adjusting between I+ signal and the I-signal satisfies 0.5dB, if do not satisfy, adjust I-signal output amplitude, the amplitude difference of I-signal and I+ signal is met the demands, judge again whether the amplitude difference between I+ signal and the Q-signal satisfies 0.5dB, if do not satisfy, adjust Q-signal output amplitude, the amplitude difference of Q-signal and I+ signal is met the demands, and final realization output IQ signal amplitude error is 0.5dBm.
According to above-mentioned execution mode, use the vector network analyzer of Agilent company to phase place and the amplitude measurement of i/q signal source output signal, the signal source quadrature phase error is ± 1 °, range error is 0.5dBm.
The above is described the specific embodiment of the present invention, still, and the scope that is not limited only to embodiment of the present invention's protection.
Claims (4)
1. a four-way i/q signal source comprises PC, FPGA, signal generator and single-chip microcomputer; It is characterized in that: signal generator comprises I+ signal generator (1), I-signal generator (2), Q+ signal generator (3) and Q-signal generator (4); Wherein, the I-signal of the I+ signal of I+ signal generator (1) output and I-signal generator (2) output is a pair of differential signal; The Q-signal of the Q+ signal of Q+ signal generator (3) output and Q-signal generator (4) output is a pair of differential signal; The Q+ signal of the signal of I+ signal generator (1) output and Q+ signal generator (3) output is a pair of synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and dc bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, the phase data control signal, output signal is to described FPGA after carrying out calculation process, control DDS circuit produces frequency and the phase place of signal, initial phase and the frequency of 4 road signals are consistent, and, single-chip microcomputer one judges whether the phase difference of 4 road signals of signal source output meets the demands, when not satisfying, output signal is to described FPGA, adjust the phase place that the DDS circuit produces signal, the phase difference of 4 road signals is met the demands, making I+ signal and I-signal is a pair of differential signal, Q+ signal and Q-signal are a pair of differential signal, and I+ signal and Q+ signal are a pair of synchronized orthogonal signal;
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal is to 4 road frequency-selective filtering amplifiers respectively, for the frequency-selective filtering amplifier is specified the filtering frequency range, simultaneously, described single-chip microcomputer two respectively output signal is controlled described numerical-control attenuator the signal of receiving is carried out the amplitude adjustment to 4 way controlling attenuation devices; And, single-chip microcomputer two judges whether the amplitude difference of 4 road signals of signal source output satisfies set point, and when not satisfying, output signal is to 4 way controlling attenuation devices, control 4 way controlling attenuation devices and respectively the signal of receiving is carried out the amplitude adjustment, make the amplitude difference of 4 road signals satisfy set point;
Described FPGA receives the data that single-chip microcomputer one transmits in real time by the shift register of inside, and reset, synchronously, frequency and phase information output to respectively 4 DDS circuit by state machine, 4 DDS circuit output signals of control synchronously, frequency and phase place;
4 described DDS circuit receive FPGA simultaneously by the information of state machine output, receive simultaneously reference clock signal, 4 DDS circuit produce respectively the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal, output to respectively corresponding frequency-selective filtering amplifier;
Described frequency-selective filtering amplifier can be selected filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives respectively the signal of corresponding DDS circuit output, and the signal of receiving is outputed to respectively corresponding numerical-control attenuator after selecting filtering to process under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives respectively the signal of corresponding frequency-selective filtering amplifier output, and is subjected to the control of single-chip microcomputer two output signals, after the signal of receiving is carried out the amplitude adjustment and processes, exports by dc bias circuit respectively;
Each described dc bias circuit receives respectively the signal of corresponding described numerical-control attenuator output, for external equipment provides the direct current biasing output signal.
2. four-way i/q signal according to claim 1 source is characterized in that: is provided with parameter in the described PC interface is set, and directly program control to frequency, phase place, the amplitude of signal source output signal.
3. four-way i/q signal according to claim 1 and 2 source, it is characterized in that: described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two links to each other with PC by serial ports two and obtains the instruction that PC sends, link to each other with the control end of 4 frequency-selective filtering amplifiers and the control end of 4 numerical-control attenuators respectively by the IO input/output port, for the frequency-selective filtering amplifier is specified the filtering frequency range, and the pad value of control numerical-control attenuator.
4. four-way i/q signal according to claim 3 source, it is characterized in that: described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer is connected and obtains the instruction of PC transmission with PC by serial ports one, be connected with FPGA by the IO input/output port, and FPGA is sent instruction.
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