CN103001898B - Four-way i/q signal source - Google Patents
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Abstract
The invention discloses a kind of four-way i/q signal source, comprise PC, FPGA, signal generator and single-chip microcomputer; It is characterized in that: signal generator comprises I+ signal generator, I-signal generator, Q+ signal generator and Q-signal generator; Wherein, the I+ signal that exports of I+ signal generator and the I-signal that exports of I-signal generator are a pair differential signal; The Q+ signal that Q+ signal generator exports and the Q-signal that Q-signal generator exports are a pair differential signal; The signal that I+ signal generator exports and the Q+ signal that Q+ signal generator exports are a pair synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and DC bias circuit; The present invention can export the I+ signal of 4 road DC ~ 700MHz, I-signal, Q+ signal and Q-signal, and the frequency of output signal, phase place, amplitude are all by the direct program control amendment in PC interface, and simple to operate, cost is low, and performance is excellent, has a good application prospect.
Description
Technical field
The present invention relates to signal source, be specifically related to four-way i/q signal source.
Background technology
Along with the develop rapidly of modern communications, radar and ECM (Electronic Countermeasures), the integrated modulator of research and development is more and more higher to signal source index request, needs i/q signal incoming frequency to be DC ~ 600MHz.But the i/q signal output frequency of the external signal source of commercial type mostly cannot reach this frequency requirement, and expensive, difficult in maintenance.Domesticly run into technical bottleneck when high-frequency, multiple signals synchronism output.
The signal source of commercial type adopts built-in base band generator mode, produce i/q signal and export, but output frequency is low, does not meet product test requirement.
Summary of the invention
Technical problem to be solved by this invention is to provide four-way i/q signal source.
In order to solve the problems of the technologies described above, technical scheme of the present invention is, a kind of four-way i/q signal source, comprises PC, FPGA, signal generator and single-chip microcomputer; Be characterized in: signal generator comprises I+ signal generator, I-signal generator, Q+ signal generator and Q-signal generator; Wherein, the I+ signal that exports of I+ signal generator and the I-signal that exports of I-signal generator are a pair differential signal; The Q+ signal that Q+ signal generator exports and the Q-signal that Q-signal generator exports are a pair differential signal; The signal that I+ signal generator exports and the Q+ signal that Q+ signal generator exports are a pair synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and DC bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, phase data control signal, after carrying out calculation process, output signal is to described FPGA, the frequency of control DDS circuit generates signals and phase place, the initial phase of 4 road signals and frequency are consistent, and, single-chip microcomputer one judges whether the phase difference of the 4 road signals that signal source exports meets the demands, when not meeting, output signal is to described FPGA, the phase place of adjustment DDS circuit generates signals, the phase difference of 4 road signals is met the demands, I+ signal and I-signal is made to be a pair differential signal, Q+ signal and Q-signal are a pair differential signal, I+ signal and Q+ signal are a pair synchronized orthogonal signal,
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal 4 road frequency-selective filtering amplifiers respectively, for filtering frequency range specified by frequency-selective filtering amplifier, improve the Spurious Free Dynamic Range of output signal; Meanwhile, described single-chip microcomputer two outputs signal 4 road numerical-control attenuators respectively, controls described numerical-control attenuator and carries out amplitude adjustment to the signal received; And, single-chip microcomputer two judges whether the amplitude difference of the 4 road signals that signal source exports meets set point, when not meeting, outputs signal 4 road numerical-control attenuators, control 4 road numerical-control attenuators and respectively amplitude adjustment is carried out to the signal received, make the amplitude difference of 4 road signals meet set point; Improve the I/Q signal precision of output;
The data real-time reception that described FPGA is transmitted single-chip microcomputer one by inner shift register, and resetting, synchronous, frequency and phase information output to 4 DDS circuit respectively by state machine, controls synchronous, frequency and the phase place of 4 DDS circuit output signals;
4 described DDS circuit receive the information that FPGA is exported by state machine simultaneously, receive reference clock signal simultaneously, 4 DDS circuit produce the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal respectively, output to corresponding frequency-selective filtering amplifier respectively;
Described frequency-selective filtering amplifier can carry out Choose filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives the signal that corresponding DDS circuit exports respectively, respectively outputs to corresponding numerical-control attenuator after carrying out Choose filtering process to the signal received under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives the signal that corresponding frequency-selective filtering amplifier exports respectively, and by the control that single-chip microcomputer two outputs signal, after carrying out amplitude adjustment process, exports respectively by DC bias circuit the signal received;
Each described DC bias circuit receives the signal that corresponding described numerical-control attenuator exports respectively, for external equipment provides direct current biasing to output signal.
The present invention adopts the frequency, phase place, amplitude etc. of PC to signal source directly program control, easy to use, directly perceived, by single-chip microcomputer one control FPGA, and then the frequency of control DDS circuit generates signals and phase place, the IQ tetra-road signal that DDS circuit produces passes through four independently frequency-selecting filters, adjustable attenuator and DC bias circuit export, the amplitude of output signal is controlled by single-chip microcomputer two, concrete control procedure is: the frequency being received PC output by single-chip microcomputer one, phase data control signal, after carrying out calculation process, output signal is to described FPGA, the frequency of control DDS circuit generates signals and phase place, and frequency and the amplitude data control signal of PC output is received by single-chip microcomputer two, after carrying out calculation process, output signal 4 road frequency-selective filtering amplifiers and 4 road numerical-control attenuators respectively, for filtering frequency range specified by frequency-selective filtering amplifier, improve the Spurious Free Dynamic Range of output signal, and control 4 road numerical-control attenuators and respectively amplitude control is carried out to the signal received, further, single-chip microcomputer one judges whether the phase difference of the 4 road signals that signal source exports meets the demands, and when not meeting, output signal is to described FPGA, and the phase place of adjustment DDS circuit generates signals, makes the phase difference of 4 road signals meet the demands, single-chip microcomputer two judges whether the amplitude difference of the 4 road signals that signal source exports meets set point, when not meeting, output signal 4 road numerical-control attenuators respectively, control 4 road numerical-control attenuators and respectively amplitude adjustment is carried out to the signal received, make the amplitude difference of 4 road signals meet set point, improve the precision of signal source output signal.
According to a kind of preferred version in four-way i/q signal source of the present invention, in described PC, be provided with optimum configurations interface, directly program control to the frequency of signal source output signal, phase place, amplitude.
According to a kind of preferred version in four-way i/q signal source of the present invention, described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two to be connected with PC by serial ports two and to obtain the instruction that PC sends, be connected with the control end of 4 numerical-control attenuators with the control end of 4 frequency-selective filtering amplifiers respectively by IO input/output port, for filtering frequency range specified by frequency-selective filtering amplifier, and control the pad value of numerical-control attenuator, reach by step motion control signal amplitude, optimize Spurious Free Dynamic Range target.
According to a kind of preferred version in four-way i/q signal source of the present invention, described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer to be connected with PC by serial ports one and to obtain the instruction that PC transmits, and is connected, sends instruction to FPGA by IO input/output port with FPGA.
The beneficial effect in four-way i/q signal source of the present invention is: the present invention can export the I+ signal of 4 road DC ~ 700MHz, I-signal, Q+ signal and Q-signal, the Spurious Free Dynamic Range of output signal is wide, the frequency range of output signal is wide, and output signal accuracy is high; Further, the frequency of output signal, phase place, amplitude are all by the directly program control and amendment of PC optimum configurations interface, intuitive display, simple to operate; It is low that the present invention also has cost, the feature that performance is excellent, can be widely used in the fields such as modern communications, radar and electronic countermeasures.
Accompanying drawing explanation
Fig. 1 is the schematic diagram in four-way i/q signal source of the present invention.
Fig. 2 is DDS control circui schematic diagram.
Fig. 3 is PC optimum configurations interface schematic diagram.
Fig. 4 is the theory diagram of single-chip microcomputer two.
Fig. 5 is the theory diagram of numerical-control attenuator.
Fig. 6 is the program flow chart of single-chip microcomputer one.
Fig. 7 is the program flow chart of single-chip microcomputer two.
Embodiment
See Fig. 1, a kind of four-way i/q signal source, comprises PC, FPGA, signal generator, serial ports one, serial ports two, single-chip microcomputer one and single-chip microcomputer two; Wherein: signal generator comprises I+ signal generator 1, I-signal generator 2, Q+ signal generator 3 and Q-signal generator 4; Wherein, the I+ signal that exports of I+ signal generator 1 and the I-signal that exports of I-signal generator 2 are a pair differential signal; The Q+ signal that Q+ signal generator 3 exports and the Q-signal that Q-signal generator 4 exports are a pair differential signal; The signal that I+ signal generator 1 exports and the Q+ signal that Q+ signal generator 3 exports are a pair synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and DC bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, phase data control signal, after carrying out calculation process, output signal is to described FPGA, the frequency of control DDS circuit generates signals and phase place, the initial phase of 4 road signals and frequency are consistent, and, single-chip microcomputer one judges whether the phase difference of the 4 road signals that signal source exports meets the demands, when not meeting, output signal is to described FPGA, the phase place of adjustment DDS circuit generates signals, the phase difference of 4 road signals is met the demands, I+ signal and I-signal is made to be a pair differential signal, Q+ signal and Q-signal are a pair differential signal, I+ signal and Q+ signal are a pair synchronized orthogonal signal,
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal 4 road frequency-selective filtering amplifiers respectively, for filtering frequency range specified by frequency-selective filtering amplifier, improve the Spurious Free Dynamic Range of output signal; Meanwhile, described single-chip microcomputer two outputs signal 4 road numerical-control attenuators respectively, controls described numerical-control attenuator and carries out amplitude adjustment to the signal received; And, single-chip microcomputer two judges whether the amplitude difference of the 4 road signals that signal source exports meets set point, when not meeting, outputs signal 4 road numerical-control attenuators, control 4 road numerical-control attenuators and respectively amplitude adjustment is carried out to the signal received, make the amplitude difference of 4 road signals meet set point; Improve the I/Q signal precision of output;
The data real-time reception that described FPGA is transmitted single-chip microcomputer one by inner shift register, and resetting, synchronous, frequency and phase information output to 4 DDS circuit respectively by state machine, controls synchronous, frequency and the phase place of 4 DDS circuit output signals;
4 described DDS circuit receive the information that FPGA is exported by state machine simultaneously, receive reference clock signal simultaneously, 4 DDS circuit produce the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal respectively, output to corresponding frequency-selective filtering amplifier respectively;
Described frequency-selective filtering amplifier can carry out Choose filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives the signal that corresponding DDS circuit exports respectively, respectively outputs to corresponding numerical-control attenuator after carrying out Choose filtering process to the signal received under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives the signal that corresponding frequency-selective filtering amplifier exports respectively, and by the control that single-chip microcomputer two outputs signal, after carrying out amplitude adjustment process, exports respectively by DC bias circuit the signal received;
Each described DC bias circuit receives the signal that corresponding described numerical-control attenuator exports respectively, for external equipment provides direct current biasing to output signal.
See Fig. 4, Fig. 5, described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two to be connected with PC by serial ports two and to obtain the instruction that PC sends, be connected with the control end of 4 numerical-control attenuators with the control end of 4 frequency-selective filtering amplifiers respectively by IO input/output port, for filtering frequency range specified by frequency-selective filtering amplifier, and control the pad value of numerical-control attenuator, reach by 0.5dB step motion control signal amplitude, optimize the targets such as Spurious Free Dynamic Range.Described single-chip microcomputer two specifically can adopt the single-chip microcomputers such as ATmega8515, ATmega8535, wherein, PA6 (AD6), the PA7 (AD7) of single-chip microcomputer are connected with the control end of 4 frequency-selective filtering amplifiers with PB6 (MISO) end simultaneously, for filtering frequency range specified by frequency-selective filtering amplifier, optimize Spurious Free Dynamic Range; PAO (AD0) to PA5 (AD5) end of single-chip microcomputer is held with the V1 to V6 of one of them numerical-control attenuator respectively and is connected; PCO (A8) to PC5 (A13) end is held with the wherein V1 to V6 of another numerical-control attenuator respectively and is connected, PBO to PB5 end is held with the wherein V1 to V6 of the 3rd numerical-control attenuator respectively and is connected, PD2 to PD7 end is held with the wherein V1 to V6 of the 4th numerical-control attenuator respectively and is connected, control the pad value of numerical-control attenuator, reach by step motion control signal amplitude.
Described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer to be connected with PC by serial ports one and to obtain the instruction that PC transmits, and is connected, sends instruction to FPGA by IO input/output port with FPGA, this instruction is sent to DDS circuit by FPGA, controls the index such as frequency, phase place that I/Q signal exports.Described single-chip microcomputer one can adopt the single-chip microcomputers such as 89C2051, and wherein, DDS circuit can adopt DS875 cake core; FPGA can adopt EP1C6F256C6 type.
See Fig. 5, the minimum control precision of numerical-control attenuator is 0.5dB, 6 control words; HMC472LP4 numerical-control attenuator chip can be adopted.
DC bias circuit can adopt JEBT_4R2GW chip.
The centre frequency frequency deviation 20MHz Out-of-band rejection index of each frequency range of described frequency-selective filtering amplifier requirements is greater than 40dB, and squareness factor is less than 1.2, and passband fluctuation is less than 1dB, and three dB bandwidth is greater than 10MHz.
During concrete enforcement, because signal source needs to export the I/Q orthogonal signalling of 4 tunnel frequencies up to 700MHz simultaneously, reference clock signal adopts 2800MHZ; As the I/Q orthogonal signalling that output signal frequency is 600MHz, reference clock signal adopts 2000MHZ; And the 4 road signals exported are synchronous, frequency is identical, phase place is adjustable separately, to this, adopts based on DDS frequency synthesis technique, to reference edge and FPGA clock common source, the frequency of signal source and phase place are controlled separately, realize 4 DDS chip synchronization and export.
Because the frequency control word of DDS chip and phase control words are concurrent working mode, the control pin of needs is many, and in order to realize the effective control to frequency and phase place, use FPGA to control in real time DDS chip, DDS control chart is as Fig. 2.
See Fig. 3, at PC, adopt the PC interface software of Delphi language development, user directly can arrange the information such as frequency, phase place, amplitude of output signal at PC optimum configurations interface, relevant information is sent to single-chip microcomputer one and single-chip microcomputer two through serial ports by PC, directly program control to the power supply of signal source, frequency, phase place, amplitude, intuitive display, easy to use.
The present invention receives the order of PC by single-chip microcomputer one, and resetting, the information such as synchronous, frequency and phase place sends to FPGA, the data real-time reception that FPGA is transmitted single-chip microcomputer by inner shift register, and resetting, the information such as synchronous, frequency and phase place by the mode control DDS output orthogonal signal of state machine and differential signal, its single-chip microcomputer one program flow diagram is as shown in Figure 6.
Concrete control flow is: IQ tetra-road signal is by being total to reference source to four DDS, the initial phase realizing four tunnel output signals is consistent, and the signal phase on each road all controls separately by PC, during control, first determine whether the phase difference of I+ signal and Q+ signal meets 89 ° ~ 91 °, if do not meet, adjustment Q+ signal exports phase place, the phase difference of I+ signal and Q+ signal is met the demands, and then judge whether the phase difference adjusted between I+ signal and I-signal meets 179 ° ~ 180 °, if do not meet, adjustment I-signal exports phase place, the phase difference of I-signal and I+ signal is met the demands, judge whether the phase difference between Q+ signal and Q-signal meets 179 ° ~ 180 ° again, if do not meet, adjustment Q-signal exports phase place, the phase difference of Q-signal and Q+ signal is met the demands, finally realize the orthogonal output of signal IQ.
The state machine of FPGA is divided into 4 states, and when state machine is in reset mode, circular wait enabling signal, once enabling signal is effective, state machine is started working.State machine part control routine is as follows:
Single-chip microcomputer two receives PC order, controls frequency-selecting filter and programmable attenuator, and its amplitude control program flow process as shown in Figure 7.
Major control flow process is: adjustment attenuated output signal amplitude, be that filtering frequency range specified by frequency-selective filtering amplifier according to output signal frequency, judge whether the amplitude difference of I+ signal and Q+ signal is less than 0.5dB, if do not meet, adjustment Q+ signal output amplitude, the amplitude difference of I+ signal and Q+ signal is met the demands, and then judge whether the amplitude difference adjusted between I+ signal and I-signal meets 0.5dB, if do not meet, adjustment I-signal output amplitude, the amplitude difference of I-signal and I+ signal is met the demands, judge whether the amplitude difference between I+ signal and Q-signal meets 0.5dB again, if do not meet, adjustment Q-signal output amplitude, the amplitude difference of Q-signal and I+ signal is met the demands, it is 0.5dBm that final realization exports I/Q signal range error.
According to above-mentioned execution mode, the phase place using the vector network analyzer of Agilent company to output signal i/q signal source and amplitude measurement, signal source quadrature phase error is ± 1 °, and range error is 0.5dBm.
Above the specific embodiment of the present invention is described, but, the scope being not limited only to embodiment of the present invention's protection.
Claims (4)
1. a four-way i/q signal source, comprises PC, FPGA, signal generator and single-chip microcomputer; It is characterized in that: signal generator comprises I+ signal generator (1), I-signal generator (2), Q+ signal generator (3) and Q-signal generator (4); Wherein, the I-signal that the I+ signal that exports of I+ signal generator (1) and I-signal generator (2) export is a pair differential signal; The Q+ signal that Q+ signal generator (3) exports and the Q-signal that Q-signal generator (4) exports are a pair differential signal; The signal that I+ signal generator (1) exports and the Q+ signal that Q+ signal generator (3) exports are a pair synchronized orthogonal signal; Each signal generator includes DDS circuit, frequency-selective filtering amplifier, numerical-control attenuator and DC bias circuit;
Single-chip microcomputer one receives the frequency of PC output by serial ports one, phase data control signal, after carrying out calculation process, output signal is to described FPGA, the frequency of control DDS circuit generates signals and phase place, the initial phase of 4 road signals and frequency are consistent, and, single-chip microcomputer one judges whether the phase difference of the 4 road signals that signal source exports meets the demands, when not meeting, output signal is to described FPGA, the phase place of adjustment DDS circuit generates signals, the phase difference of 4 road signals is met the demands, I+ signal and I-signal is made to be a pair differential signal, Q+ signal and Q-signal are a pair differential signal, I+ signal and Q+ signal are a pair synchronized orthogonal signal,
Single-chip microcomputer two receives frequency and the amplitude data control signal of PC output by serial ports two, after carrying out calculation process, output signal 4 road frequency-selective filtering amplifiers respectively, for filtering frequency range specified by frequency-selective filtering amplifier, simultaneously, described single-chip microcomputer two outputs signal 4 road numerical-control attenuators respectively, controls described numerical-control attenuator and carries out amplitude adjustment to the signal received; And, single-chip microcomputer two judges whether the amplitude difference of the 4 road signals that signal source exports meets set point, when not meeting, outputs signal 4 road numerical-control attenuators, control 4 road numerical-control attenuators and respectively amplitude adjustment is carried out to the signal received, make the amplitude difference of 4 road signals meet set point;
The data real-time reception that described FPGA is transmitted single-chip microcomputer one by inner shift register, and resetting, synchronous, frequency and phase information output to 4 DDS circuit respectively by state machine, controls synchronous, frequency and the phase place of 4 DDS circuit output signals;
4 described DDS circuit receive the information that FPGA is exported by state machine simultaneously, receive reference clock signal simultaneously, 4 DDS circuit produce the consistent I+ signal of initial phase, I-signal, Q+ signal and Q-signal respectively, output to corresponding frequency-selective filtering amplifier respectively;
Described frequency-selective filtering amplifier can carry out Choose filtering according to different frequency ranges, each described frequency-selective filtering amplifier receives the signal that corresponding DDS circuit exports respectively, respectively outputs to corresponding numerical-control attenuator after carrying out Choose filtering process to the signal received under single-chip microcomputer two designated frequency band;
Each described numerical-control attenuator receives the signal that corresponding frequency-selective filtering amplifier exports respectively, and by the control that single-chip microcomputer two outputs signal, after carrying out amplitude adjustment process, exports respectively by DC bias circuit the signal received;
Each described DC bias circuit receives the signal that corresponding described numerical-control attenuator exports respectively, for external equipment provides direct current biasing to output signal.
2. four-way i/q signal source according to claim 1, is characterized in that: be provided with optimum configurations interface in described PC, directly program control to the frequency of signal source output signal, phase place, amplitude.
3. four-way i/q signal source according to claim 1 and 2, it is characterized in that: described single-chip microcomputer two adopts 8 single-chip microcomputers, single-chip microcomputer two to be connected with PC by serial ports two and to obtain the instruction that PC sends, be connected with the control end of 4 numerical-control attenuators with the control end of 4 frequency-selective filtering amplifiers respectively by IO input/output port, for filtering frequency range specified by frequency-selective filtering amplifier, and control the pad value of numerical-control attenuator.
4. four-way i/q signal source according to claim 3, it is characterized in that: described single-chip microcomputer one adopts 8 single-chip microcomputers, this single-chip microcomputer to be connected with PC by serial ports one and to obtain the instruction that PC transmits, and is connected, sends instruction to FPGA by IO input/output port with FPGA.
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| CN202931369U (en) * | 2012-11-27 | 2013-05-08 | 重庆西南集成电路设计有限责任公司 | Four-channel I/Q signal source of high precision |
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