CN107422780B - Arbitrary waveform generator based on instruction framework - Google Patents
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- G06F1/02—Digital function generators
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Abstract
The invention discloses an arbitrary waveform generator based on an instruction framework, and provides a waveform synthesis instruction set controller to replace a sequence generator aiming at the characteristic of tight coupling of an address generator and the sequence generator in the traditional complex sequence waveform synthesis method, so that the waveform synthesis instruction and waveform segment waveform data reading time-sharing scheduling are realized, the hardware complexity is reduced, and complex sequence waves are synthesized and generated quickly and efficiently.
Description
Technical Field
The invention relates to the technical field of arbitrary waveform generators, in particular to an arbitrary waveform generator based on an instruction framework to generate complex sequence waves.
Background
An Arbitrary Waveform Generator (AWG) is a type of signal source which is rapidly developed in recent years, and it can generate not only standard waveforms such as sine waves and square waves generated by a general signal source, but also various modulation signals such as frequency shift modulation and amplitude modulation, and has the characteristics of continuous phase of output Waveform, stable Waveform quality, high bandwidth, and the like. Therefore, the arbitrary waveform generator is widely applied to the fields of disk drive testing, serial data communication, baseband/IF modulation testing, automobile anti-lock, engine control, frequency converters, biomedical simulation and the like.
In US patent No. US8166283B2 entitled "Generator of automatic with Adjustable waveform", issued 24/04/2012, An arbitrary waveform Generator with An instruction architecture is proposed, however, the instructions of the arbitrary waveform Generator are too loose and coupled to be suitable for synthesis of only simple waveforms, which is not favorable for fast and efficient synthesis and generation of complex sequence waves.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an arbitrary waveform generator based on an instruction architecture so as to quickly and efficiently synthesize and generate a complex sequence wave.
To achieve the above object, the present invention provides an arbitrary waveform generator based on an instruction architecture, comprising:
the upper computer is used for generating a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sending the corresponding waveform synthesis instruction to the lower computer;
the lower computer is used for carrying out waveform synthesis according to the received waveform synthesis instruction and outputting a complex sequence wave;
the lower computer comprises a waveform synthesis instruction set controller, a memory, a storage control module, a DMA control module, an FIFO module, an output control module, a digital-to-analog conversion module and an output conditioning module;
the waveform synthesis instruction sent to the lower computer by the upper computer is received by the waveform synthesis instruction set controller, and the waveform synthesis instruction controller analyzes the waveform synthesis instruction after receiving the waveform synthesis instruction, sends the analyzed trigger control command to the output control module, and simultaneously sends the analyzed DMA command to the DMA control module;
the DMA control module analyzes the received DMA command into a waveform data reading control command; sending the analyzed waveform data reading control command to a storage control module; the storage control module carries out addressing operation on the memory according to the waveform data reading control command, waveform section waveform data of a corresponding address is read into the FIFO module through the DMA control module, and the waveform data is sent to the output control module after being cached by the FIFO module;
the output control module finishes the trigger function processing of the waveform data point according to the trigger signal and the trigger control command and then continuously sends the waveform data of the waveform section to the digital-to-analog conversion module; waveform data of the waveform section is converted into an analog signal through a digital-to-analog conversion module, and the functions of amplification, attenuation and the like of the analog signal are completed through an output conditioning module, so that the generation of the waveform is completed;
the waveform synthesis instruction set controller comprises an instruction buffer, an instruction resolver, an instruction address generator and a DMA (direct memory access) command FIFO memory; the command buffer is used for storing a waveform synthesis command sent by the upper computer, taking out the waveform synthesis command which needs to be executed currently according to a command address sent by the command address generator, and sending the waveform synthesis command to the command analyzer; the command analyzer analyzes the waveform synthesis command, sends a command control command to the command address generator, sends the DMA command to the DMA command FIFO memory if the analyzed DMA command is the DMA command, and sends the trigger control command to the output control module if the analyzed DMA command is the trigger control command; the instruction address generator generates an instruction address of the next waveform synthesis instruction in the instruction cache to complete sequential execution of the waveform synthesis instruction or jump execution according to the instruction control command; the DMA command FIFO memory caches the DMA command sent by the command parser, and sends the DMA command to the DMA control module to complete the waveform data reading control of the waveform section;
the instruction address generator includes: an instruction counter, a waveform segment repetition number counter and a sequence wave repetition number counter; the instruction counter generates a storage address, namely an instruction address, in the instruction buffer of the next waveform synthesis instruction according to the logic judgment of the execution instruction control command; the waveform segment repetition frequency counter and the sequence wave repetition frequency counter are both readable and writable registers and are used for realizing a conditional jump instruction, wherein the waveform segment repetition frequency counter counts the synthesis frequency of a waveform segment, and the sequence wave repetition frequency counter counts the synthesis frequency of a sequence wave;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control instruction and sends the instruction control instruction to the instruction address generator; the instruction address generator judges the instruction control command, if the operation code corresponds to the operation code of the waveform segment, the target operation counter is a waveform segment repetition number counter, if the operation code corresponds to the operation code of the sequence wave, the target operation counter is a sequence wave repetition number counter, the conditional jump is performed, when the command is executed, the count value of the corresponding target operation counter is increased by 1 and then is compared with the jump number, and if the jump number is less than the jump number, the assignment of the instruction counter is a jump instruction address, namely, the jump instruction address of the jump instruction control command is taken; if the number of the jump is equal to the number of the jump, adding 1 to an instruction counter in an instruction address generator, namely sequentially taking out the next instruction from an instruction buffer, and clearing the counter of a target operation counter.
The object of the invention is thus achieved.
The invention provides an arbitrary waveform generator based on an instruction framework, and aims at the characteristic that an address generator and a sequence generator in the traditional complex sequence waveform synthesis method are tightly coupled, a waveform synthesis instruction set controller is used for replacing the sequence generator, the waveform synthesis instruction and waveform segment waveform data reading time-sharing scheduling are realized, the hardware complexity is reduced, and therefore, complex sequence waves are synthesized and generated quickly and efficiently.
Drawings
FIG. 1 is a schematic block diagram of an embodiment of an arbitrary waveform generator based on an instruction architecture;
FIG. 2 is a functional block diagram of one embodiment of the waveform synthesis instruction set controller shown in FIG. 1;
FIG. 3 is a functional block diagram of one embodiment of the instruction address generator of FIG. 2;
FIG. 4 is a functional block diagram of one embodiment of the output control module shown in FIG. 1.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
FIG. 1 is a schematic block diagram of an embodiment of an arbitrary waveform generator based on an instruction architecture.
In this embodiment, as shown in fig. 1, the arbitrary waveform generator based on the instruction framework of the present invention includes an upper computer 1 and a lower computer 2.
The upper computer 1 generates a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sends the corresponding waveform synthesis instruction to the lower computer 2.
In this embodiment, the upper computer 1 includes a control computer 101 and a bus interface unit 102, and the control computer 101 converts the waveform characteristics input by the user into corresponding waveform synthesis instructions and sends the corresponding waveform synthesis instructions to the lower computer 2 through the bus interface unit 102.
The lower computer 2 performs waveform synthesis according to the received waveform synthesis instruction and outputs a complex sequence wave.
The lower computer 2 includes a waveform synthesis instruction set controller 201, a memory 202, a storage control module 203, a DMA control module 204, a FIFO module 205, an output control module 206, a digital-to-analog conversion module 207, and an output conditioning module 208.
As shown in fig. 1, analysis of the waveform synthesis command by the waveform synthesis command controller 201 constitutes a command control path. The waveform synthesis instruction sent from the upper computer 1 to the lower computer 2 is received by the waveform synthesis instruction set controller 201, and after receiving the waveform synthesis instruction, the waveform synthesis instruction controller 201 parses the instruction, sends the parsed trigger control command to the output control module 206, and sends the parsed DMA command to the DMA control module 204.
As shown in fig. 1, the memory 202, the memory control module 203, the DMA control module 204, the FIFO module 205, the output control module 206, the digital-to-analog conversion module 207, and the output conditioning module 208 form a data control path. The DMA control module 204 parses the received DMA command into a waveform data read control command; sending the analyzed waveform data read control command to the storage control module 203; the storage control module 203 performs an addressing operation on the memory 202 according to the waveform data reading control command, reads waveform segment waveform data of a corresponding address into the FIFO module 205 through the DMA control module 204, and sends the waveform data to the output control module 206 after the waveform data is cached by the FIFO module 205. The output control module 206 continuously sends waveform segment waveform data to the digital-to-analog conversion module 207 after completing the trigger function processing on the waveform data points according to the trigger signal and the trigger control command; the waveform data of the waveform segment is converted into an analog signal by the digital-to-analog conversion module 207, and the analog signal is amplified and attenuated by the output conditioning module 208, so that the generation of a complex sequence waveform is completed.
Fig. 2 is a schematic block diagram of an embodiment of the waveform synthesis instruction set controller shown in fig. 1.
In the present embodiment, as shown in fig. 2, the waveform synthesis instruction set controller 201 includes an instruction buffer 2011, an instruction parser 2012, an instruction address generator 2013, and a DMA command FIFO memory 2014. The instruction buffer 201 is configured to store a waveform synthesis instruction sent by the upper computer, fetch a waveform synthesis instruction currently required to be executed according to an instruction address sent by the instruction address generator 2013, and send the waveform synthesis instruction to the instruction parser 2012; the command parser 2012 parses the waveform synthesis command, and sends a command control command to the command address generator 2013, and if the parsed command is a DMA command, sends the DMA command to the DMA command FIFO memory 2014, and if the parsed command is a trigger control command, sends the trigger control command to the output control module 206. The instruction address generator 2013 generates an instruction address of the next waveform synthesis instruction in the instruction buffer 2011, and completes sequential execution of the waveform synthesis instruction or jump execution according to an instruction control command; the DMA command FIFO memory buffers the DMA command sent by the command parser 2012 and sends the DMA command to the DMA control module 204, thereby completing the waveform segment waveform data read control.
As shown in fig. 3, the instruction address generator 2013 includes: an instruction counter, a waveform segment repetition number counter and a sequence wave repetition number counter. The instruction counter generates a storage address, namely an instruction address, in the instruction buffer of the next waveform synthesis instruction according to the logic judgment of the execution instruction control command; the waveform segment repetition frequency counter and the sequence wave repetition frequency counter are both readable and writable registers and are used for realizing a conditional jump instruction, wherein the waveform segment repetition frequency counter counts the synthesis frequency of the waveform segment, and the sequence wave repetition frequency counter counts the synthesis frequency of the sequence wave.
The instruction control command comprises an operation code, a jump instruction address and jump times, and when the waveform synthesis instruction is a jump instruction, the instruction resolver 2012 resolves the instruction to obtain an instruction control command and sends the instruction control command to the instruction address generator 2013; the instruction address generator 2013 judges the instruction control command, if the operation code corresponds to the operation code of the waveform segment, the target operation counter is a waveform segment repetition number counter, if the operation code corresponds to the operation code of the sequence wave, the target operation counter is a sequence wave repetition number counter, the condition skipping is adopted, when the command is executed, the count value of the corresponding target operation counter is increased by 1 and then is compared with the skipping number, and if the count value is less than the skipping number, the assignment of the instruction counter is a skipping instruction address, namely, a skipping instruction address fetching instruction of the skipping instruction control command is carried out; if the number of jumps is equal to the number of jumps, the instruction counter in the instruction address generator is incremented by 1, that is, the next instruction is sequentially fetched from the instruction buffer 2011, and the counter of the destination operation counter is cleared.
In the specific implementation process, the number of corresponding repetition counter and the conditional jump instruction can be increased according to the complexity of the sequence wave generated as required, that is, the device also comprises a plurality of repetition counters which are readable and writable registers and are used for counting more complex waveform sequences and realizing the nested calling of the waveform sequences in the complex sequence wave.
In the present embodiment, as shown in fig. 4, the output control module 206 includes a waveform segment total data point memory 2061, a waveform segment trigger flag FIFO memory 2062, a waveform data point output counter 2063, and an output controller 2064. The command parser 2012 sends the parsed trigger control command to the output control module 206, where the trigger control command is composed of a total data point of the waveform segment, i.e. (the total waveform data length corresponding to a waveform segment synthesis command, the trigger control command includes the operand, i.e. P), and a waveform segment trigger flag, the total data point of the waveform segment FIFO 2061 caches the total data point of the waveform segment, and the waveform segment trigger flag FIFO 2062 caches the waveform segment trigger flag; the waveform data point output counter 2063 counts the number of data points output by the current waveform segment, when the count value is equal to the total number of data points of the waveform segment currently taken out by the waveform segment total data point FIFO memory 2061, a waveform segment synthesizing instruction is completed, then, the waveform segment total data point FIFO memory 2061 takes out the total number of data points of the next waveform segment, the waveform segment trigger flag FIFO memory 2061 takes out the trigger flag of the next waveform segment, and the count value of the waveform data point output counter 2063 is cleared; the output controller 2064 controls the FIFO module 205 to send the on/off of the waveform data to the digital-to-analog conversion module 207 according to the waveform segment trigger flag currently taken out by the waveform segment trigger flag FIFO memory: the output controller 2064 first determines the waveform segment trigger flag currently taken out by the waveform segment trigger flag FIFO memory, when the waveform segment trigger flag is a non-trigger flag, the output controller 2064 opens the waveform data transmission path, and the waveform segment waveform data cached by the FIFO module 205 is sent to the digital-to-analog conversion module 207 through the output controller 2064; when the waveform segment trigger flag is the trigger flag, the output controller 2064 suspends the FIFO module 205 from sending the waveform segment waveform data to the digital-to-analog conversion module 207 until the trigger signal arrives, and restarts the FIFO module 205 to send the waveform segment waveform data to the digital-to-analog conversion module 207 through the output controller 2064, thereby implementing the trigger function.
The arbitrary waveform generator based on instruction architecture applies a dedicated instruction set processor technique to the field of waveform synthesis, in this example, the instruction set of its waveform synthesis instruction set includes: a waveform segment synthesis instruction, two conditional jump instructions, an unconditional jump instruction and a trigger control instruction.
The waveform segment synthesis instruction format is as follows:
SEGMENT DataAddress Length
SEGMENT is an operation code for identifying the instruction, and comprises two operands, namely DataAddress and Length, wherein the DataAddress is an initial address of waveform data of a waveform SEGMENT stored in the memory 202, the operand Length is the waveform data Length of the waveform SEGMENT, when the instruction is executed, the instruction analyzer analyzes the operands, namely DataAddress and Length, into a DMA instruction for controlling waveform data reading and sends the DMA instruction to a DMA command FIFO memory, meanwhile, an instruction counter in the instruction address generator 2013 is added by 1, a next waveform synthesis instruction is sequentially taken out from the instruction buffer 2011, and the waveform synthesis instruction is sequentially executed;
the conditional jump instruction includes: the waveform segment repeat output command and the sequence wave repeat output command.
The waveform segment repeated output instruction format is as follows:
SEGMENT_JUMP InstructionAddress M
the instruction is used for realizing repeated output of a waveform SEGMENT M times, SEGMENT _ JUMP is an operation code, InstructionAddress and M are operands, InstructionAddress is a JUMP address, and M is the repetition number. When the instruction is executed, adding 1 to the count value of the waveform segment repeated sub-counter, comparing and judging the count value with M, when the count value is smaller than M, assigning the instruction counter to InstructionADDRESS, taking out a waveform synthesis instruction with the address of InstructionADDRESS from the instruction buffer 201, and skipping to execute the waveform synthesis instruction; when the count value is equal to M, the instruction counter in the instruction address generator 2013 is incremented by 1, the next waveform synthesis instruction is sequentially fetched from the instruction buffer 201, the waveform synthesis instruction is sequentially executed, and the count value of the waveform segment repetition counter is cleared.
Wherein, the sequence wave repeat output instruction format is as follows:
SEQUENCE_JUMP InstructionAddress N
the instruction is used for realizing repeated output of the SEQUENCE wave for N times, SEQUENCE _ JUMP is an operation code, InstructionAddress and N are operands, InstructionAddress is a JUMP address, and N is the repetition number. When the instruction is executed, adding 1 to the count value of the sequence wave repetition counter, comparing and judging the count value with N, when the count value is smaller than N, assigning the instruction counter to InstructionADDRESS, taking out the instruction with the InstructionADDRESS address from the instruction buffer 201, and jumping to execute the instruction; when the count value is greater than or equal to N, the instruction counter in the instruction address generator 2013 is incremented by 1, the next waveform synthesis instruction is sequentially fetched out from the instruction storage unit, the waveform synthesis instruction is sequentially executed, and the count value of the sequential wave repetition counter is cleared.
The unconditional jump instruction format is as follows:
JUMP InstructionAddress
the instruction is used for realizing infinite repeated output of waveform segments, sequence waves and enhanced sequence waves, JUMP is an operation code, InstructionAddress is an operand, when the instruction is executed, an instruction counter is assigned to InstructionAddress, a waveform synthesis instruction with the address of InstructionAddress is taken out from an instruction buffer 201 and sent to an instruction parser, namely, the waveform synthesis instruction with the address of InstructionAddress in the instruction buffer 201 is executed in a JUMP mode.
The trigger control instruction has an instruction format as follows:
SET_TRIGGER P F
the instruction is used for setting the TRIGGER function of a waveform section, SET _ TRIGGER is an operation code, P and F are both operands, wherein the operand P is the total data point number of a repeatedly output waveform section, and F is a waveform section TRIGGER mark; when the waveform segment trigger flag F is 0, the waveform segment output does not need triggering of a trigger signal; when the waveform segment trigger flag F is 1, it indicates that the waveform segment outputs a trigger requiring a trigger signal.
Detailed description of the invention
Suppose that an enhanced sequence wave Z with wireless repetitive output needs to be synthesized, and the enhanced sequence wave Z is formed by combining a sequence wave a with 2 repetitive outputs and a sequence wave B with 3 repetitive outputs. The sequence wave A consists of a waveform segment a repeated 3 times and a waveform segment B repeatedly output 1 time, the waveform segment B needs a trigger signal to be sent, and the sequence wave B consists of a waveform segment c repeatedly output 5 times and a waveform segment d repeatedly output 2 times. The data start address of the waveform segment a is DataAddress1, the data length is 1000, and the data are repeated for 3 times; the data start address of the waveform segment b is DataAddress2, the data length is 2000, and the data is repeated for 1 time; the data start address of the waveform segment c is DataAddress3, the data length is 500, and the data are repeated for 4 times; the waveform segment d has a data start address of DataAddress4 and a data length of 5000, and is repeated 1 time.
In the present embodiment, the waveform synthesis instruction to generate enhanced sequence wave Z is as follows:
TABLE 1
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (2)
1. An arbitrary waveform generator based on an instruction architecture, comprising:
the upper computer is used for generating a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sending the corresponding waveform synthesis instruction to the lower computer;
the lower computer is used for carrying out waveform synthesis according to the received waveform synthesis instruction and outputting a complex sequence wave;
the lower computer comprises a waveform synthesis instruction set controller, a memory, a storage control module, a DMA control module, an FIFO module, an output control module, a digital-to-analog conversion module and an output conditioning module;
the waveform synthesis instruction sent to the lower computer by the upper computer is received by the waveform synthesis instruction set controller, and the waveform synthesis instruction controller analyzes the waveform synthesis instruction after receiving the waveform synthesis instruction, sends the analyzed trigger control command to the output control module, and simultaneously sends the analyzed DMA command to the DMA control module;
the DMA control module analyzes the received DMA command into a waveform data reading control command; sending the analyzed waveform data reading control command to a storage control module; the storage control module carries out addressing operation on the memory according to the waveform data reading control command, waveform section waveform data of a corresponding address is read into the FIFO module through the DMA control module, and the waveform data is sent to the output control module after being cached by the FIFO module;
the output control module finishes the trigger function processing of the waveform data point according to the trigger signal and the trigger control command and then continuously sends the waveform data of the waveform section to the digital-to-analog conversion module; the waveform data of the waveform section is converted into an analog signal through a digital-to-analog conversion module, and the amplification and attenuation functions of the analog signal are completed through an output conditioning module to complete the generation of the waveform;
the waveform synthesis instruction set controller comprises an instruction buffer, an instruction resolver, an instruction address generator and a DMA (direct memory access) command FIFO memory; the command buffer is used for storing a waveform synthesis command sent by the upper computer, taking out the waveform synthesis command which needs to be executed currently according to a command address sent by the command address generator, and sending the waveform synthesis command to the command analyzer; the command analyzer analyzes the waveform synthesis command, sends a command control command to the command address generator, sends the DMA command to the DMA command FIFO memory if the analyzed DMA command is the DMA command, and sends the trigger control command to the output control module if the analyzed DMA command is the trigger control command; the instruction address generator generates an instruction address of the next waveform synthesis instruction in the instruction cache to complete sequential execution of the waveform synthesis instruction or jump execution according to the instruction control command; the DMA command FIFO memory caches the DMA command sent by the command parser, and sends the DMA command to the DMA control module to complete the waveform data reading control of the waveform section;
the instruction address generator comprises an instruction counter, a waveform segment repetition frequency counter and a sequence wave repetition frequency counter; the instruction counter generates a storage address, namely an instruction address, in the instruction buffer of the next waveform synthesis instruction according to the logic judgment of the execution instruction control command; the waveform segment repetition frequency counter and the sequence wave repetition frequency counter are both readable and writable registers and are used for realizing a conditional jump instruction, wherein the waveform segment repetition frequency counter counts the synthesis frequency of a waveform segment, and the sequence wave repetition frequency counter counts the synthesis frequency of a sequence wave;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control instruction and sends the instruction control instruction to the instruction address generator; the instruction address generator judges the instruction control command, if the operation code corresponds to the operation code of the waveform segment, the target operation counter is a waveform segment repetition number counter, if the operation code corresponds to the operation code of the sequence wave, the target operation counter is a sequence wave repetition number counter, the conditional jump is performed, when the command is executed, the count value of the corresponding target operation counter is increased by 1 and then is compared with the jump number, and if the jump number is less than the jump number, the assignment of the instruction counter is a jump instruction address, namely, the jump instruction address of the jump instruction control command is taken; if the number of the jump is equal to the number of the jump, adding 1 to an instruction counter in an instruction address generator, namely sequentially taking out the next instruction from an instruction buffer, and clearing the counter of a target operation counter.
2. The arbitrary waveform generator of claim 1, wherein the command address generator comprises a plurality of corresponding repetition counter and is a readable and writable register for counting more complex waveform sequences and implementing nested calling of waveform sequences in complex-sequence waves;
the instruction set of the waveform synthesis instruction includes: a waveform segment synthesis instruction, two conditional jump instructions, an unconditional jump instruction and a trigger control instruction;
the waveform segment synthesis instruction format is as follows:
SEGMENT DataAddress Length
SEGMENT is an operation code for identifying the instruction, and comprises two operands, namely DataAddress and Length, wherein the DataAddress is an initial address of waveform data of a waveform section stored in a memory, the operand Length is the waveform data Length of the waveform section, when the instruction is executed, an instruction analyzer analyzes the operands, namely DataAddress and Length, into a DMA instruction for controlling waveform data reading and sends the DMA instruction to a DMA command FIFO memory, meanwhile, an instruction counter in an instruction address generator is added by 1, the next waveform synthesis instruction is sequentially taken out from an instruction buffer, and the waveform synthesis instruction is sequentially executed;
the conditional jump instruction includes: a waveform segment repetitive output instruction and a sequence wave repetitive output instruction;
the waveform segment repeated output instruction format is as follows:
SEGMENT_JUMP InstructionAddress M
the instruction is used for realizing repeated output of a waveform SEGMENT M times, SEGMENT _ JUMP is an operation code, InstructionAddress and M are operands, InstructionAddress is a JUMP address, and M is the repetition number; when the instruction is executed, adding 1 to the count value of the waveform segment repeated sub-counter, comparing and judging the count value with M, when the count value is smaller than M, assigning the instruction counter to InstructionADDRESS, taking out a waveform synthesis instruction with the address of InstructionADDRESS from the instruction buffer, and skipping to execute the waveform synthesis instruction; when the count value is equal to M, adding 1 to an instruction counter in an instruction address generator, sequentially taking out the next waveform synthesis instruction from an instruction buffer, sequentially executing the waveform synthesis instruction, and simultaneously clearing the count value of a waveform segment repeated time counter;
wherein, the sequence wave repeat output instruction format is as follows:
SEQUENCE_JUMP InstructionAddress N
the instruction is used for realizing repeated output of the SEQUENCE wave for N times, SEQUENCE _ JUMP is an operation code, InstructionADDRESS and N are operands, InstructionADDRESS is a JUMP address, and N is the repetition number; when the instruction is executed, adding 1 to the count value of the sequence wave repeating time counter, comparing and judging the count value with N, when the count value is smaller than N, assigning the instruction counter to InstructionADDRESS, taking out the instruction with the InstructionADDRESS address from the instruction buffer, and jumping to execute the instruction; when the count value is more than or equal to N, adding 1 to an instruction counter in the instruction address generator, sequentially taking out the next waveform synthesis instruction from the instruction storage unit, sequentially executing the waveform synthesis instruction, and simultaneously clearing the count value of the sequential wave repeated time counter;
the unconditional jump instruction format is as follows:
JUMP InstructionAddress
the instruction is used for realizing infinite repeated output of a basic waveform segment, a sequence wave and an enhanced sequence wave, JUMP is an operation code, InstructionAddress is an operand, when the instruction is executed, an instruction counter is assigned to InstructionAddress, a waveform synthesis instruction with the address of InstructionAddress is taken out from an instruction buffer and sent to an instruction parser, namely, the waveform synthesis instruction with the address of InstructionAddress in the instruction buffer is executed in a JUMP mode;
the trigger control instruction has an instruction format as follows:
SET_TRIGGER P F
the instruction is used for setting the TRIGGER function of a waveform section, SET _ TRIGGER is an operation code, P and F are both operands, wherein the operand P is the total data point number of a repeatedly output waveform section, and F is a waveform section TRIGGER mark; when the waveform segment trigger flag F is 0, the waveform segment output does not need triggering of a trigger signal; when the waveform segment trigger flag F is 1, it indicates that the waveform segment outputs a trigger requiring a trigger signal.
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| CN103580653A (en) * | 2012-07-27 | 2014-02-12 | 特克特朗尼克公司 | Waveform generation circuit for waveform generator |
| CN102788891A (en) * | 2012-07-30 | 2012-11-21 | 电子科技大学 | Complex waveform sequence generator |
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| CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
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