CN107402596B - Arbitrary waveform generator based on instruction framework - Google Patents
Arbitrary waveform generator based on instruction framework Download PDFInfo
- Publication number
- CN107402596B CN107402596B CN201710669268.8A CN201710669268A CN107402596B CN 107402596 B CN107402596 B CN 107402596B CN 201710669268 A CN201710669268 A CN 201710669268A CN 107402596 B CN107402596 B CN 107402596B
- Authority
- CN
- China
- Prior art keywords
- instruction
- waveform
- command
- jump
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electrophonic Musical Instruments (AREA)
Abstract
The invention discloses an arbitrary waveform generator based on an instruction framework, and provides a waveform synthesis instruction set controller to replace a sequence generator aiming at the characteristic of tight coupling of an address generator and the sequence generator in the traditional complex sequence waveform synthesis method, so that the waveform synthesis instruction and waveform segment waveform data reading time-sharing scheduling are realized, the hardware complexity is reduced, and complex sequence waves are synthesized and generated quickly and efficiently.
Description
Technical Field
The invention relates to the technical field of arbitrary waveform generators, in particular to an arbitrary waveform generator based on an instruction framework to generate complex sequence waves.
Background
An Arbitrary Waveform Generator (AWG) is a type of signal source which is rapidly developed in recent years, and it can generate not only standard waveforms such as sine waves and square waves generated by a general signal source, but also various modulation signals such as frequency shift modulation and amplitude modulation, and has the characteristics of continuous phase of output Waveform, stable Waveform quality, high bandwidth, and the like. Therefore, the arbitrary waveform generator is widely applied to the fields of disk drive testing, serial data communication, baseband/IF modulation testing, automobile anti-lock, engine control, frequency converters, biomedical simulation and the like.
In US patent No. US8166283B2 entitled "Generator of automatic with Adjustable waveform", issued 24/04/2012, An arbitrary waveform Generator based on instruction architecture is proposed, however, the instructions of the arbitrary waveform Generator are too loose and coupled to be suitable for synthesis of only simple waveforms, which is not favorable for fast and efficient synthesis and generation of complex sequence waves.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an arbitrary waveform generator based on an instruction architecture so as to quickly and efficiently synthesize and generate a complex sequence wave.
To achieve the above object, the present invention provides an arbitrary waveform generator based on an instruction architecture, comprising:
the upper computer is used for generating a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sending the corresponding waveform synthesis instruction to the lower computer;
the lower computer is used for carrying out waveform synthesis according to the received waveform synthesis instruction and outputting a complex sequence wave;
the lower computer comprises a waveform synthesis instruction set controller, a memory, a storage control module, a DMA control module, an FIFO module, an output control module, a digital-to-analog conversion module and an output conditioning module;
the waveform synthesis instruction sent to the lower computer by the upper computer is received by the waveform synthesis instruction set controller, and the waveform synthesis instruction controller analyzes the waveform synthesis instruction after receiving the waveform synthesis instruction, sends the analyzed trigger control command to the output control module, and simultaneously sends the analyzed DMA command to the DMA control module;
the DMA control module analyzes the received DMA command into a waveform data reading control command; sending the analyzed waveform data reading control command to a storage control module; the storage control module carries out addressing operation on the memory according to the waveform data reading control command, waveform section waveform data of a corresponding address is read into the FIFO module through the DMA control module, and the waveform data is sent to the output control module after being cached by the FIFO module;
the output control module finishes the trigger function processing of the waveform data point according to the trigger signal and the trigger control command and then continuously sends the waveform data of the waveform section to the digital-to-analog conversion module; waveform data of the waveform section is converted into an analog signal through a digital-to-analog conversion module, and the functions of amplification, attenuation and the like of the analog signal are completed through an output conditioning module, so that the generation of the waveform is completed;
the waveform synthesis instruction set controller comprises an instruction buffer, an instruction parser, an instruction address generator and a data address generator;
the command buffer is used for storing a waveform synthesis command sent by the upper computer, taking out the waveform synthesis command which needs to be executed currently according to a command address sent by the command address generator, and sending the waveform synthesis command to the command analyzer; the command analyzer analyzes the waveform synthesis command, sends the analyzed command control command to the command address generator, sends the analyzed waveform segment control command to the data address generator, and sends the analyzed trigger control command to the output control module;
the instruction address generator generates an instruction address of the next waveform synthesis instruction in the instruction cache to complete sequential execution of the waveform synthesis instruction or jump execution according to the instruction control command; the data address generator generates a DMA command according to the waveform segment control command sent by the command parser and sends the DMA command to the DMA control module;
the instruction address generator comprises: an instruction counter and repetition number counter 0;
the instruction counter generates a storage address, namely an instruction address, in the instruction buffer of the next waveform synthesis instruction according to the logic judgment of the execution instruction control command, and sends the storage address to the instruction resolver, and the repetition counter 0 is a readable and writable register and is used for realizing the conditional jump of the instruction and counting the frequency of the sequential wave synthesis;
the instruction control command is divided into a conditional jump command and an unconditional jump command;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control command and sends the command to the instruction address generator; the instruction address generator judges the instruction control command, if the condition is skip, the count value of the repetition number counter 0 is added with 1, then the condition is compared with the skip number, the judgment is further carried out, if the count value is less than the skip number, the instruction counter is assigned as a skip instruction address, namely, the skip instruction address appointed by the instruction control command is skipped to, if the count value is equal to the skip number, the instruction counter in the instruction address generator is added with 1, namely, the next instruction is taken out from the instruction buffer in sequence, and meanwhile, the count value of the repetition number counter 0 is cleared;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control instruction and sends the instruction control instruction to the instruction address generator; and the instruction address generator judges the instruction control command, and if the instruction control command is unconditional jumping, the instruction counter is assigned as a jump instruction address, namely, the jump instruction address specified by the instruction control command is jumped to.
The object of the invention is thus achieved.
The invention provides an arbitrary waveform generator based on an instruction framework, and aims at the characteristic that an address generator and a sequence generator in the traditional complex sequence waveform synthesis method are tightly coupled, a waveform synthesis instruction set controller is used for replacing the sequence generator, the waveform synthesis instruction and waveform segment waveform data reading time-sharing scheduling are realized, the hardware complexity is reduced, and therefore, complex sequence waves are synthesized and generated quickly and efficiently.
Drawings
FIG. 1 is a schematic block diagram of an embodiment of an arbitrary waveform generator based on an instruction architecture;
FIG. 2 is a functional block diagram of one embodiment of the waveform synthesis instruction set controller shown in FIG. 1;
FIG. 3 is a functional block diagram of one embodiment of the instruction address generator of FIG. 2;
FIG. 4 is a functional block diagram of one embodiment of the data address generator shown in FIG. 2;
FIG. 5 is a functional block diagram of one embodiment of the output control module shown in FIG. 1.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
FIG. 1 is a schematic block diagram of an embodiment of an arbitrary waveform generator based on an instruction architecture.
In this embodiment, as shown in fig. 1, the arbitrary waveform generator based on the instruction framework of the present invention includes an upper computer 1 and a lower computer 2.
The upper computer 1 generates a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sends the corresponding waveform synthesis instruction to the lower computer 2.
In this embodiment, the upper computer 1 includes a control computer 101 and a bus interface unit 102, and the control computer 101 converts the waveform characteristics input by the user into corresponding waveform synthesis instructions and sends the corresponding waveform synthesis instructions to the lower computer 2 through the bus interface unit 102.
The lower computer 2 performs waveform synthesis according to the received waveform synthesis instruction and outputs a complex sequence wave.
The lower computer 2 includes a waveform synthesis instruction set controller 201, a memory 202, a storage control module 203, a DMA control module 204, a FIFO module 205, an output control module 206, a digital-to-analog conversion module 207, and an output conditioning module 208.
As shown in fig. 1, analysis of the waveform synthesis command by the waveform synthesis command controller 201 constitutes a command control path. The waveform synthesis instruction sent from the upper computer 1 to the lower computer 2 is received by the waveform synthesis instruction set controller 201, and after receiving the waveform synthesis instruction, the waveform synthesis instruction controller 201 parses the instruction, sends the parsed trigger control command to the output control module 206, and sends the parsed DMA command to the DMA control module 204.
As shown in fig. 1, the memory 202, the memory control module 203, the DMA control module 204, the FIFO module 205, the output control module 206, the digital-to-analog conversion module 207, and the output conditioning module 208 form a data control path. The DMA control module 204 parses the received DMA command into a waveform data read control command; sending the analyzed waveform data read control command to the storage control module 203; the storage control module 203 performs an addressing operation on the memory 202 according to the waveform data reading control command, reads waveform segment waveform data of a corresponding address into the FIFO module 205 through the DMA control module 204, and sends the waveform data to the output control module 206 after the waveform data is cached by the FIFO module 205. The output control module 206 continuously sends waveform segment waveform data to the digital-to-analog conversion module 207 after completing the trigger function processing on the waveform data points according to the trigger signal and the trigger control command; the waveform data of the waveform segment is converted into an analog signal by the digital-to-analog conversion module 207, and the analog signal is amplified and attenuated by the output conditioning module 208, so that the generation of a complex sequence waveform is completed.
Fig. 2 is a schematic block diagram of an embodiment of the waveform synthesis instruction set controller shown in fig. 1.
In the present embodiment, as shown in fig. 2, the waveform synthesis instruction set controller 201 includes an instruction buffer 2011, an instruction parser 2012, an instruction address generator 2013, and a data address generator 2014. The instruction buffer 201 is configured to store a waveform synthesis instruction sent by the upper computer, fetch a waveform synthesis instruction currently required to be executed according to an instruction address sent by the instruction address generator 2013, and send the waveform synthesis instruction to the instruction parser 2012; the parsed command parser 2012 parses the waveform synthesis command, sends a command control command to the command address generator 2013, sends a parsed waveform segment control command to the data address generator 2014, and sends a parsed trigger control command to the output control module 206;
the instruction address generator 2013 generates an instruction address of the next waveform synthesis instruction in the instruction register 2011, and completes sequential execution of the waveform synthesis instruction or jump execution according to an instruction control command; the data address generator 2014 generates a DMA command according to the waveform segment control command sent by the command parser 2012, and sends the DMA command to the DMA control module 204, thereby completing the waveform segment waveform data read control.
As shown in fig. 3, the instruction address generator 2013 includes: an instruction counter and a repetition counter 0. Wherein, the instruction counter generates a storage address in the instruction buffer of the next waveform synthesis instruction, i.e. an instruction address, according to the logic judgment of the execution instruction control command, and sends the storage address to the instruction resolver 2012; the repetition counter 0 is a readable and writable register and is used for realizing the conditional jump of the instruction and counting the frequency of the sequence wave synthesis;
the instruction control command is divided into a conditional jump command and an unconditional jump command
When the waveform synthesis instruction is a jump instruction, the instruction resolver 2012 resolves the instruction to obtain an instruction control command and sends the command to the instruction address generator 2013; the instruction address generator 2013 determines the instruction control command, and if the condition is a conditional jump, the count value of the repetition counter 0 is incremented by 1, and then the conditional jump is compared with the jump times, and further determines that if the count value is smaller than the jump times, the instruction counter is assigned as a jump instruction address, that is, the jump instruction address specified by the instruction control command is jumped to, and if the count value is equal to the jump times, the instruction counter in the instruction address generator is incremented by 1, that is, the next instruction is sequentially fetched from the instruction buffer 2011, and the count value of the repetition counter 0 is cleared at the same time.
When the waveform synthesis instruction is a jump instruction, the instruction resolver 2012 resolves the jump instruction to obtain an instruction control instruction and sends the instruction control instruction to the instruction address generator 2013; the instruction address generator 2013 judges the instruction control command, and if the instruction control command is unconditional jumping, the instruction counter is assigned as a jump instruction address, namely, the jump instruction address specified by the instruction control command is jumped to.
In the specific implementation process, the number of corresponding repetition counter can be increased according to the complexity of the sequence wave generated as required, that is, the device also can comprise a plurality of repetition counters and is a readable and writable register, and the device is used for counting more complex waveform sequences and realizing the nested calling of the waveform sequences in the complex sequence wave.
In this embodiment, the JUMP instruction feature instruction format is condition _ JUMP instruction address KN, and the JUMP instruction is used to implement unconditional JUMP and conditional JUMP of a waveform synthesis instruction, where JUMP is an opcode of the JUMP instruction, instruction address, K and N are operands, instruction address is a JUMP instruction address, K is a repeat counter number in the instruction address generator 2013, and N is a JUMP number. When a jump instruction is executed, adding 1 to the count value of the repeated counter K, comparing the count value with the jump number N, assigning the count value to a jump instruction address InstructionAddress when the count value is smaller than the jump number N, and taking out an instruction with the jump instruction address InstructionAddress from the instruction buffer 2011; when the count value is equal to the jump number N, the instruction counter increments by 1, that is, the next instruction is sequentially fetched from the instruction buffer 2011, and the count value of the repeat counter K is cleared.
In this embodiment, as shown in fig. 4, the data address generator 2014 includes: a waveform segment control command FIFO memory 20141, a waveform segment controller 20142, a waveform segment repetition number counter 20143, and a DMA command FIFO memory 20144. The waveform segment control command FIFO 20141 caches the waveform segment control command sent by the command parser 2012, and the waveform segment control command sent by the command parser 2012 includes a waveform segment waveform data start address, a waveform segment data length and waveform segment repetition frequency information; the waveform segment controller 20142 takes out and analyzes the waveform segment control instruction from the waveform segment control instruction FIFO memory, the obtained waveform segment waveform data starting address, the waveform segment data length and the waveform segment repetition number M are stored in the waveform segment controller, a DNA command is produced according to the waveform segment data starting address and the waveform segment data length, the DMA command is sent to the DMA instruction FIFO memory 20144, 1 is added to the count value of the waveform segment repetition number counter 20143 every time the DMA command is sent, when the count value of the waveform segment repetition number counter 20143 is equal to the waveform segment repetition number M, the count value of the waveform segment repetition number counter 20143 is cleared, and meanwhile, the next waveform segment control instruction is taken out from the waveform segment control instruction FIFO memory 20141 to enter the synthesis of the next waveform segment; the DMA command FIFO memory buffers the DMA command sent by the waveform segment controller, and when the DMA control module 204 completes the sending of a waveform segment synthesis control command, the next DMA instruction is fetched from the DMA command FIFO memory.
In the present embodiment, as shown in fig. 5, the output control module 206 includes a waveform segment total data point memory 2061, a waveform segment trigger flag FIFO memory 2062, a waveform data point output counter 2063, and an output controller 2064. The command parser 2012 sends the parsed trigger control command to the output control module 206, where the trigger control command is composed of a total data point of a waveform segment, i.e., Length × M (a total waveform data Length corresponding to a waveform segment synthesis command), and a waveform segment trigger flag, the total data point of the waveform segment is cached in the waveform segment FIFO memory 2061, and the waveform segment trigger flag is cached in the waveform segment FIFO memory 2062; the waveform data point output counter 2063 counts the number of data points output by the current waveform segment, when the count value is equal to the total number of data points of the waveform segment currently taken out by the waveform segment total data point FIFO memory 2061, a waveform segment synthesizing instruction is completed, then, the waveform segment total data point FIFO memory 2061 takes out the total number of data points of the next waveform segment, the waveform segment trigger flag FIFO memory 2061 takes out the trigger flag of the next waveform segment, and the count value of the waveform data point output counter 2063 is cleared; the output controller 2064 controls the FIFO module 205 to send the on/off of the waveform data to the digital-to-analog conversion module 207 according to the waveform segment trigger flag currently taken out by the waveform segment trigger flag FIFO memory: the output controller 2064 first determines the waveform segment trigger flag currently taken out by the waveform segment trigger flag FIFO memory, when the waveform segment trigger flag is a non-trigger flag, the output controller 2064 opens the waveform data transmission path, and the waveform segment waveform data cached by the FIFO module 205 is sent to the digital-to-analog conversion module 207 through the output controller 2064; when the waveform segment trigger flag is the trigger flag, the output controller 2064 suspends the FIFO module 205 from sending the waveform segment waveform data to the digital-to-analog conversion module 207 until the trigger signal arrives, and restarts the FIFO module 205 to send the waveform segment waveform data to the digital-to-analog conversion module 207 through the output controller 2064, thereby implementing the trigger function.
In this embodiment, the present invention is based on an arbitrary waveform generator of an instruction architecture, and an instruction set of a waveform synthesis instruction includes a waveform segment synthesis instruction, a conditional jump instruction, and an unconditional jump instruction.
The instruction format of the waveform segment synthesis instruction is as follows:
SEGMENT DataAddress Length M F
the command is a waveform synthesis control command and is used for outputting a waveform SEGMENT for M times, wherein whether the waveform SEGMENT needs to be triggered and output can be set, SEGMENT is an operation code for identifying the command, DataAddress, Length, M and F are operands, DataAddress is an initial address of waveform SEGMENT waveform data, Length is the Length of the waveform SEGMENT waveform data, M is the repetition frequency of the waveform SEGMENT, and F is a waveform SEGMENT trigger mark; when the waveform segment trigger flag F is 0, the waveform segment output does not need triggering of a trigger signal; when the waveform segment trigger flag F is 1, the waveform segment is triggered to output a trigger signal required by the waveform segment;
the instruction format of the conditional jump instruction is:
CONDITION_JUMP InstructionAddress K N
the CONDITION _ JUMP is an operation code of the instruction, and InstructionAddress, K and N are operands, wherein InstructionAddress is an instruction JUMP address, K is a repeat counter number in an instruction address generator, and N is a JUMP number. When the instruction is executed, adding 1 to the count value of the repetition number counter K, comparing and judging the count value with the jump number N, when the count value is smaller than the jump number N, assigning the count value to InstructionAddress by the instruction counter, taking a waveform synthesis instruction with the address of InstructionAddress from the instruction storage unit, and jumping to execute the waveform synthesis instruction; when the count value is equal to the jump time N, adding 1 to an instruction counter in an instruction address generator, sequentially taking out the next waveform synthesis instruction from an instruction storage unit, sequentially executing the waveform synthesis instruction, and clearing the count value of a repetition time counter K;
wherein the unconditional jump instruction is characterized by: the instruction format is:
JUMP InstructionAddress
the instruction is used to realize infinite repeated output of a waveform segment, a sequential wave and an enhanced sequential wave, where JUMP is an operation code, and insensitaddress is an operand, and when the instruction is executed, an instruction counter is assigned to insensitaddress, and a waveform synthesis instruction with an address of insensitaddress is taken out from the instruction buffer 2011, that is, a waveform synthesis instruction with an address of insensitaddress in the JUMP execution instruction buffer 2011.
Detailed description of the invention
Synthesizing a complex sequence wave F for infinite repeated output, wherein the complex sequence wave F consists of an enhanced sequence wave Z and an enhanced sequence wave Y, the enhanced sequence wave Z is repeated twice, and the enhanced sequence wave Y is repeated three times;
wherein the enhanced sequence wave Z is formed by combining a sequence wave A repeatedly output for 2 times and a sequence wave B repeatedly output for 3 times. The sequence wave A consists of a waveform segment a repeated 3 times and a waveform segment B repeatedly output 1 time, the waveform segment B needs a trigger signal to be sent, and the sequence wave B consists of a waveform segment c repeatedly output 5 times and a waveform segment d repeatedly output 2 times. The data start address of the waveform segment a is DataAddress1, the data length is 1000, and the data are repeated for 3 times; the data start address of the waveform segment b is DataAddress2, the data length is 2000, and the data is repeated for 1 time; the data start address of the waveform segment c is DataAddress3, the data length is 500, and the data are repeated for 4 times; the waveform segment d has a data start address of DataAddress4 and a data length of 5000, and is repeated 1 time.
Wherein the enhanced sequence wave Y is formed by combining a sequence wave C repeatedly output for 2 times and a sequence wave D repeatedly output for 3 times. The sequence wave A is composed of a waveform segment e which is repeatedly output for 3 times and a waveform segment f which is repeatedly output for 4 times, and the sequence wave D is composed of a waveform segment h which is repeatedly output for 5 times and a waveform segment i which is repeatedly output for 2 times. The data start address of the waveform segment e is DataAddress5, the data length is 1000, and the data are repeated for 3 times; the data start address of the waveform segment f is DataAddress6, the data length is 2000, and the data is repeated for 1 time; the data start address of the waveform segment h is DataAddress7, the data length is 500, and the data are repeated for 4 times; the waveform segment i has a data start address of DataAddress8 and a data length of 5000, and is repeated 2 times.
In the present embodiment, the waveform synthesis instruction to generate the complex-sequence wave F is as follows:
TABLE 1
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (2)
1. An arbitrary waveform generator based on an instruction architecture, comprising:
the upper computer is used for generating a corresponding waveform synthesis instruction according to the waveform characteristics input by the user and sending the corresponding waveform synthesis instruction to the lower computer;
the lower computer is used for carrying out waveform synthesis according to the received waveform synthesis instruction and outputting a complex sequence wave;
the lower computer comprises a waveform synthesis instruction set controller, a memory, a storage control module, a DMA control module, an FIFO module, an output control module, a digital-to-analog conversion module and an output conditioning module;
the waveform synthesis instruction sent to the lower computer by the upper computer is received by the waveform synthesis instruction set controller, and the waveform synthesis instruction controller analyzes the waveform synthesis instruction after receiving the waveform synthesis instruction, sends the analyzed trigger control command to the output control module, and simultaneously sends the analyzed DMA command to the DMA control module;
the DMA control module analyzes the received DMA command into a waveform data reading control command; sending the analyzed waveform data reading control command to a storage control module; the storage control module carries out addressing operation on the memory according to the waveform data reading control command, waveform section waveform data of a corresponding address is read into the FIFO module through the DMA control module, and the waveform data is sent to the output control module after being cached by the FIFO module;
the output control module finishes the trigger function processing of the waveform data point according to the trigger signal and the trigger control command and then continuously sends the waveform data of the waveform section to the digital-to-analog conversion module; the waveform data of the waveform section is converted into an analog signal through a digital-to-analog conversion module, and the amplification and attenuation functions of the analog signal are completed through an output conditioning module to complete the generation of the waveform;
the waveform synthesis instruction set controller comprises an instruction buffer, an instruction parser, an instruction address generator and a data address generator;
the command buffer is used for storing a waveform synthesis command sent by the upper computer, taking out the waveform synthesis command which needs to be executed currently according to a command address sent by the command address generator, and sending the waveform synthesis command to the command analyzer; the command analyzer analyzes the waveform synthesis command, sends the analyzed command control command to the command address generator, sends the analyzed waveform segment control command to the data address generator, and sends the analyzed trigger control command to the output control module;
the instruction address generator generates an instruction address of the next waveform synthesis instruction in the instruction buffer to complete sequential execution of the waveform synthesis instruction or jump execution according to the instruction control command; the data address generator generates a DMA command according to the waveform segment control command sent by the command parser and sends the DMA command to the DMA control module;
the instruction address generator comprises: an instruction counter and repetition number counter 0;
the instruction counter generates a storage address, namely an instruction address, in the instruction buffer of the next waveform synthesis instruction according to the logic judgment of the execution instruction control command, and sends the storage address to the instruction resolver, and the repetition counter 0 is a readable and writable register and is used for realizing the conditional jump of the instruction and counting the frequency of the sequential wave synthesis;
the instruction control command is divided into a conditional jump command and an unconditional jump command;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control command and sends the command to the instruction address generator; the instruction address generator judges the instruction control command, if the condition is skip, the count value of the repetition number counter 0 is added with 1, then the condition is compared with the skip number, the judgment is further carried out, if the count value is less than the skip number, the instruction counter is assigned as a skip instruction address, namely, the skip instruction address appointed by the instruction control command is skipped to, if the count value is equal to the skip number, the instruction counter in the instruction address generator is added with 1, namely, the next instruction is taken out from the instruction buffer in sequence, and meanwhile, the count value of the repetition number counter 0 is cleared;
when the waveform synthesis instruction is a jump instruction, the instruction resolver resolves the instruction to obtain an instruction control instruction and sends the instruction control instruction to the instruction address generator; and the instruction address generator judges the instruction control command, and if the instruction control command is unconditional jumping, the instruction counter is assigned as a jump instruction address, namely, the jump instruction address specified by the instruction control command is jumped to.
2. The arbitrary waveform generator according to claim 1, wherein the instruction address generator includes a plurality of repetition number counters and is a readable and writable register;
the instruction set of the waveform synthesis instruction comprises a waveform segment synthesis instruction, a conditional jump instruction and an unconditional jump instruction;
the instruction format of the waveform segment synthesis instruction is as follows:
SEGMENT DataAddress Length M F
the command is a waveform synthesis control command and is used for outputting a waveform SEGMENT for M times, wherein whether the waveform SEGMENT needs to be triggered and output can be set, SEGMENT is an operation code for identifying the command, DataAddress, Length, M and F are operands, DataAddress is an initial address of waveform SEGMENT waveform data, Length is the Length of the waveform SEGMENT waveform data, M is the repetition frequency of the waveform SEGMENT, and F is a waveform SEGMENT trigger mark; when the waveform segment trigger flag F is 0, the waveform segment output does not need triggering of a trigger signal; when the waveform segment trigger flag F is 1, the waveform segment is triggered to output a trigger signal required by the waveform segment;
the instruction format of the conditional jump instruction is:
CONDITION_JUMP InstructionAddress K N
the CONDITION _ JUMP is an operation code of the instruction, and InstructionAddress, K and N are operands, wherein InstructionAddress is an instruction JUMP address, K is a repeat counter number in an instruction address generator, and N is a JUMP number; when the instruction is executed, adding 1 to the count value of the repetition number counter K, comparing and judging the count value with the jump number N, when the count value is smaller than the jump number N, assigning the count value to InstructionAddress by the instruction counter, taking a waveform synthesis instruction with the address of InstructionAddress from the instruction storage unit, and jumping to execute the waveform synthesis instruction; when the count value is equal to the jump time N, adding 1 to an instruction counter in an instruction address generator, sequentially taking out the next waveform synthesis instruction from an instruction storage unit, sequentially executing the waveform synthesis instruction, and clearing the count value of a repetition time counter K;
wherein the unconditional jump instruction is characterized by: the instruction format is:
JUMP InstructionAddress
the instruction is used for realizing infinite repeated output of a basic waveform segment, a sequential wave and an enhanced sequential wave, JUMP is an operation code, InstructionAddress is an operand, when the instruction is executed, an instruction counter is assigned to InstructionAddress, a waveform synthesis instruction with the address of InstructionAddress is taken out from an instruction buffer, namely the waveform synthesis instruction with the address of InstructionAddress in an instruction buffer is executed in a JUMP mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710669268.8A CN107402596B (en) | 2017-08-08 | 2017-08-08 | Arbitrary waveform generator based on instruction framework |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710669268.8A CN107402596B (en) | 2017-08-08 | 2017-08-08 | Arbitrary waveform generator based on instruction framework |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107402596A CN107402596A (en) | 2017-11-28 |
| CN107402596B true CN107402596B (en) | 2020-03-24 |
Family
ID=60402069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710669268.8A Active CN107402596B (en) | 2017-08-08 | 2017-08-08 | Arbitrary waveform generator based on instruction framework |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107402596B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402596B (en) * | 2017-08-08 | 2020-03-24 | 电子科技大学 | Arbitrary waveform generator based on instruction framework |
| CN109933126B (en) * | 2017-12-15 | 2023-05-23 | 彩优微电子(昆山)有限公司 | Digital waveform signal generating device |
| TWI683202B (en) * | 2017-12-27 | 2020-01-21 | 大陸商彩優微電子（昆山）有限公司 | Digital waveform signal generation device |
| CN109462385B (en) * | 2018-10-26 | 2021-01-19 | 西安交通大学 | Device and method for compiling high-voltage pulse parameters |
| CN109696572A (en) * | 2019-01-23 | 2019-04-30 | 济南浪潮高新科技投资发展有限公司 | A kind of waveform generator and Waveform output method of PCIE interface |
| CN117631752B (en) * | 2024-01-25 | 2024-05-07 | 深圳市鼎阳科技股份有限公司 | Waveform sequence creation method, display method and waveform sequence generator |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4649783A (en) * | 1983-02-02 | 1987-03-17 | The Board Of Trustees Of The Leland Stanford Junior University | Wavetable-modification instrument and method for generating musical sound |
| CN1159637A (en) * | 1995-12-21 | 1997-09-17 | 雅马哈株式会社 | Method and device for musical tone |
| CN102904550A (en) * | 2012-09-26 | 2013-01-30 | 北京工业大学 | Multi-channel synchronous waveform generator based on AD9959 |
| CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
| CN203422426U (en) * | 2013-06-09 | 2014-02-05 | 广州飞机维修工程有限公司 | Universal comprehensive automatic test system of airborne computer of civilian airliner |
| US9100030B1 (en) * | 2014-06-30 | 2015-08-04 | Keysight Technologies, Inc. | Real-time modification of waveform characteristics in arbitrary waveform generator |
| CN107402596A (en) * | 2017-08-08 | 2017-11-28 | 电子科技大学 | A kind of AWG based on instruction architecture |
-
2017
- 2017-08-08 CN CN201710669268.8A patent/CN107402596B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4649783A (en) * | 1983-02-02 | 1987-03-17 | The Board Of Trustees Of The Leland Stanford Junior University | Wavetable-modification instrument and method for generating musical sound |
| CN1159637A (en) * | 1995-12-21 | 1997-09-17 | 雅马哈株式会社 | Method and device for musical tone |
| US6040515A (en) * | 1995-12-21 | 2000-03-21 | Yamaha Corporation | Method and device for generating a tone |
| CN102904550A (en) * | 2012-09-26 | 2013-01-30 | 北京工业大学 | Multi-channel synchronous waveform generator based on AD9959 |
| CN203422426U (en) * | 2013-06-09 | 2014-02-05 | 广州飞机维修工程有限公司 | Universal comprehensive automatic test system of airborne computer of civilian airliner |
| CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
| US9100030B1 (en) * | 2014-06-30 | 2015-08-04 | Keysight Technologies, Inc. | Real-time modification of waveform characteristics in arbitrary waveform generator |
| CN107402596A (en) * | 2017-08-08 | 2017-11-28 | 电子科技大学 | A kind of AWG based on instruction architecture |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107402596A (en) | 2017-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107402596B (en) | Arbitrary waveform generator based on instruction framework | |
| CN107436618B (en) | Arbitrary waveform generator based on instruction framework | |
| CN101799705B (en) | High-speed DDS signal generator | |
| JP5840994B2 (en) | Matrix operation unit | |
| US20070067123A1 (en) | Advanced arbitrary waveform generator | |
| CN107422780B (en) | Arbitrary waveform generator based on instruction framework | |
| CN107589410B (en) | A kind of no breakpoint Multiple Target Signals synthetic method | |
| CA1186079A (en) | Digital scan converter with randomized decay function | |
| CN110018449B (en) | Signal synthesis method using envelope information | |
| CN112987047B (en) | Satellite navigation signal capturing system and method based on time division multiplexing technology | |
| CN104935304A (en) | Broadband repetition arbitrary waveform generator and generation method | |
| CN102520760A (en) | Processor for arbitrary waveform generating system | |
| CN103389413A (en) | Real-time statistical method for frequency spectrum histogram | |
| CN101901130B (en) | Instruction distributing and instruction decode preprocessing device | |
| US20180183412A1 (en) | Realtime streaming control of an arbitrary waveform generator | |
| CN114442055A (en) | Radar electromagnetic situation perception simulation test method and system in complex electromagnetic environment | |
| KR20110097478A (en) | Test mode signal generation circuit | |
| JP2001243018A (en) | Data converting device | |
| JP2004510248A (en) | FIFO write / LIFO read trace buffer with software and hardware loop compression | |
| JPH11313328A (en) | Image processing unit | |
| CN220455517U (en) | Linear frequency modulation MIMO radar signal processor | |
| KR100968090B1 (en) | Programable sound synthesis apparatus and programable sound synthesis method | |
| CN112091425B (en) | Laser control method, device and medium | |
| JP4703052B2 (en) | Simulated underwater acoustic signal generator | |
| CN116500568B (en) | Method and system for generating long-time dynamic multi-target overlapping signals |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |