TWI683202B - Digital waveform signal generation device - Google Patents

Abstract

A digital waveform signal generation device is provided, which includes a memory unit, event processors and an arbiter. The memory unit is configured to store compiled instruction data. The event processors are configured to access the memory unit and generate and output a waveform signal according to the compiled instruction data. The arbiter is configured to determine priorities of the event processors for accessing the memory unit.

Description

Digital waveform signal generating device

The invention relates to a digital waveform signal generating device, and in particular to a universal programmable digital waveform signal generating device.

Today's common waveform generators are mainly register-configured waveform generators, microprocessor (MCU) waveform generators and softcore (softcore) processor waveform generators. The register configuration waveform generator uses different registers to set the cycle length, high and low potential switching time point and high and low potential duration, etc., so for a more complex waveform sequence, a large number of temporary registers are often required Corresponding to each change position. In addition, the number of registers is not easy to adjust after the manufacture of the register-configured waveform generator is completed, and when encountering the waveform that cannot be output, it is necessary to modify the metal mask or redesign the integrated circuit Adjustments such as code, which significantly increase hardware and/or time costs. On the other hand, the waveform generator of the microprocessor and the waveform generator of the soft core processor, etc. must drive the input/output port by reading the program written in advance to generate the waveform signal and output it. Although the waveform generator of the microprocessor/soft core processor realizes the programmable function, it is more flexible than the waveform generator of the register configuration type, but there are many problems in practical application. First of all, the general soft core processor is for general purpose, which contains many other and input /Output and instruction extraction have nothing to do with the function, these unused functions occupy a lot of area in the integrated circuit. Secondly, general-purpose processors also have problems such as slower instruction execution speed and data failures that may occur during the instruction execution pipeline, and the processor may cause its internal timer to generate an interrupt and generate an uncertain delay in response to the interrupt. Due to the above factors, the microprocessor/soft-core processor waveform generator cannot generate fast waveforms. Furthermore, the number of waveform output channels of the processor is limited by the number of input/output ports in the fixed architecture of the processor, so the configuration that requires a large number of output channels will be more complicated. Finally, because the microprocessor/soft-core processor waveform generator uses a common instruction set, the code of the waveform generator is easily cracked, making it difficult for the programmer's intellectual property rights to be protected.

The object of the present invention is to provide a digital waveform signal generation device that uses a dedicated waveform event streaming command instruction set and compiler, which can save hardware layout space, increase design flexibility, generate fast waveform signals, and improve design data. safety.

According to the above object of the present invention, a digital waveform signal generating device is proposed. The digital waveform signal generating device includes a memory unit, a plurality of event processors and an arbiter. The memory unit is used to store compilation instruction data. These event processors are used to access the memory unit and generate and output at least one waveform signal according to the compiled instruction data. The arbiter is used to determine the order in which these event processors read memory cells.

According to one or more embodiments of the present invention, each of these event processors includes a memory access unit, a command fetch unit, and a command Decoding unit, branch prediction unit and command execution unit. The memory access unit is used to read compilation instruction data from the memory unit according to the current address. The command extraction unit is used to extract at least one instruction from the compilation instruction data. The command decoding unit is used to parse out the command type and the number of command operations from the command. The branch prediction unit is used to determine whether the instruction type is a continuous address or a jump address. The command execution unit is used to execute commands to update the waveform signal. One or more of the instructions belong to the dedicated waveform event streaming command instruction set. The dedicated waveform event streaming command instruction set includes absolute time point command operation instructions and relative time period command operation instructions.

According to one or more embodiments of the present invention, the absolute time point command operation instruction includes a waveform change absolute position and a waveform change relative position.

According to one or more embodiments of the present invention, the above-mentioned relative time period command operation instruction includes the waveform changing the relative position.

According to one or more embodiments of the present invention, the priority of these event processors is set by user programs or hardware.

According to one or more embodiments of the present invention, the above-mentioned event processors multiplex the time-sharing shared memory unit.

According to one or more embodiments of the invention, the aforementioned event processors are configured to execute in parallel.

According to one or more embodiments of the present invention, the memory unit is a static random access memory (SRAM), an electrically erasable programmable read only memory (EEPROM) , One-time programmable (one-time programmable; OTP) memory or electronic programmable read only memory (erasable programmable read only memory; EPROM).

According to one or more embodiments of the present invention, the above-mentioned digital waveform signal generating device further includes a compiler, which is used to compile the memory symbol code into compilation instruction data.

According to one or more embodiments of the present invention, the aforementioned digital waveform signal generating device is universally programmable.

Compared with the registered configurator waveform generator, microprocessor waveform generator and soft core processor waveform generator, the digital waveform signal generating device of the present invention can modify the code of the memory symbol without changing the hardware, and The space occupied by the hardware and the amount of memory used are low, so it can generate faster waveform signals. In addition, the digital waveform signal generation device of the present invention adopts a parallel architecture, which is suitable for outputting multiple waveform signals at the same time. It is easier for programmers to edit the memory symbol codes, and the dedicated instruction set and compiler used by them can avoid such a slight The programs of the processor waveform generator and the soft core processor waveform generator can be easily cracked, so the intellectual property rights of the programmer or company can be further protected.

100‧‧‧Digital waveform signal generating device

110‧‧‧Hardware

112‧‧‧ block memory

114(1)~114(N), 200‧‧‧event processor

116‧‧‧Arbiter

122‧‧‧ compiler

124‧‧‧ memory symbol encoding

202‧‧‧ State Machine

204‧‧‧Memory Access Unit

206‧‧‧Command extraction unit

208‧‧‧Command decoding unit

210‧‧‧ branch prediction unit

212‧‧‧ Command execution unit

Pin_1~Pin_N‧‧‧wave signal

t1~t7‧‧‧time

For a more complete understanding of the embodiment and its advantages, reference is now made to the following description made in conjunction with the accompanying drawings, where: [FIG. 1] is a schematic diagram of a digital waveform signal generating device according to some embodiments of the invention; [FIG. 2] is a schematic diagram of an event processor according to some embodiments of the present invention; and [FIG. 3] is a waveform signal output result of an example of memory symbol encoding.

The embodiments of the present invention are discussed in detail below. However, it can be understood that the embodiments provide many applicable inventive concepts that can be implemented in a variety of specific contents. The specific embodiments discussed are for illustration only and are not intended to limit the scope of the invention.

As used herein, the term "coupled" may refer to two or more elements making direct physical or electrical contact with each other, or indirectly making physical or electrical contact with each other, and "coupling" may also refer to two or Multiple elements interoperate or act.

Please refer to FIG. 1, which is a schematic diagram of a digital waveform signal generating device 100 according to some embodiments of the present invention. The digital waveform signal generating device 100 is universally programmable and different from the registered configurator, microprocessor waveform generator and soft core processor waveform generator, it does not need to configure a large number of registers, and it uses dedicated waveform event stream instructions To generate faster waveform signals. The hardware portion 110 of the digital waveform signal generating device 100 includes a memory unit 112, event processors 114(1) to 114(N), and an arbiter 116. The memory unit 112 is used to store compilation instruction data, and it may be static random access memory (SRAM), electronically erasable programmable read only memory (EEPROM), One-time programmable (OTP) memory or electrical Erasable programmable read only memory (EPROM), but not limited to this. The event processors 114(1)-114(N) are used to access the memory unit 112 and generate and output waveform signals Pin_1~Pin_N according to the compiled instruction data, respectively. The event processors 114(1) to 114(N) have a parallel structure, that is, the event processors 114(1) to 114(N) are executed in parallel and independently, and they do not affect each other. The number N of the event processors 114(1) to 114(N) can be correspondingly determined according to actual requirements (such as the number of waveform signal output channels). In addition, the event processors 114(1) to 114(N) can be operated at different times, that is, the number of event processors actually operated in the same time period can be less than the number N. The arbiter 116 is coupled to the event processors 114(1)-114(N) and the memory unit 112, and is used to determine the order in which the event processors 114(1)-114(N) read the memory unit 112. For example, under the default settings, if there are two event processors 114 in the event processors 114(1) to 114(N) that want to read instructions at the same time, the event processor with a lower address is given priority to read the instructions After the reading is completed, the event processor with a higher address is accessed to read the instruction again. In addition, the arbiter 116 can also configure the event processors 114(1) to 114(N) to execute in parallel. The priority of the event processors 114(1)~114(N) can be set by user program or hardware, but not limited to this. In addition, the event processors 114(1) to 114(N) can share the memory unit 112 in multiplexed time-sharing.

In addition to the hardware part, the digital waveform signal generating device 100 further includes a compiler 122 for compiling the memory symbol code 124 to convert the content in the memory symbol code 124 into the compiled instruction data in the binary machine code format . During the compilation process, the compiler 122 will jump to The relative jump addresses used in the commands (such as the loop instruction and the xlppp instruction) are converted to absolute addresses, and are uniformly assigned to the event processor entry address and code length corresponding to each output channel. In addition, the editor 122 also has the function of detecting command errors and adding comments, which facilitates programmers to edit the content of the memory symbol code 124. The memory symbol code 124 can be edited by the programmer through the input device.

Please refer to FIG. 2, which is a schematic diagram of an event processor 200 according to some embodiments of the present invention. The event processor 200 of FIG. 2 is any one of the event processors 114(1) to 114(N) of FIG. The event processor 200 includes a state machine 202, a memory access unit 204, a command extraction unit 206, a command decoding unit 208, a branch prediction unit 210, and a command execution unit 212. The state machine 202 is used to record the current execution state of the event processor 200. The memory access unit 204 is used to read compilation instruction data from the memory unit 112 according to the current address. The command extraction unit 206 is used to extract at least one instruction from the compilation instruction data. The command decoding unit 208 is used to parse out the command type and the number of command operations from the command. The branch prediction unit 210 is used to determine whether the instruction type is a continuous address or a jump address. The command execution unit 212 is used to execute commands to update the waveform signal.

其中，包含指令記憶符號fppi的指令為絕對時間點命令操作指令，包含指令記憶符號appi或s-appi的指令為相對時間段命令操作指令，而包含指令記憶符號loop或xloop的指令為跳轉位址命令操作指令。在上述指令格式中，level為高電位或低電位，ret_addr為返回位址，p-position為波形改變絕對位置，p-displacement和h-displacement為波形改變相對位置(其中p-和h-分別代表精細值和粗略值)，而repeat_num為重複進行次數。 The digital waveform signal generating device 100 uses a dedicated waveform event streaming command instruction set, which includes a waveform event command and a waveform period command, where the waveform event command also includes an absolute time point command operation command (also called a relative time period command operation command) and The fixed event position command operation instruction (also called the cumulative event position command operation instruction), and the waveform cycle command includes the jump address command operation instruction. For example, the command format used by the digital waveform signal generating device 100 may include the following (the first column is the command type):

Among them, the instruction including the instruction memory symbol fppi is an absolute time point command operation instruction, the instruction including the instruction memory symbol appi or s-appi is a relative time period command operation instruction, and the instruction including the instruction memory symbol loop or xloop is the jump address Command operation instructions. In the above instruction format, level is high or low, ret_addr is the return address, p-position is the absolute position of the waveform change, p-displacement and h-displacement are the relative positions of the waveform change (where p- and h- represent respectively Fine value and rough value), and repeat_num is the number of repetitions.

The following is the command format and the corresponding fields and bit numbers according to the first embodiment of the present invention: long fppi command: 3 bytes 2 bits (01) 1 bit (level) 9 bits (p-position) 12 Bit (h-displacement) fppi instruction: 2 bytes 2 bits (00) 1 bit (level) 1 bit (fppi index) 8 bits (v-displacement) 4 bits (h-displacement) short fppi command: 1 byte 2 bits (01) 1 bit (level) 1 bit (short fppi index) 4 bits (h-displacement) loop command: 2 bytes 2 bits (11) 6 bits Yuan (return address/negative number/relative value) 8 bits (return times) extern loop instruction: 2 bytes 2 bits (10) 8 bits (return address/negative number/relative value) 6 bits (return frequency) Among them, the absolute point-in-time command operation instructions include long fppi instructions, fppi instructions and short fppi instructions. The main difference is that the lengths are 3 bytes, 2 bytes and 1 byte respectively. In addition, the jump address command operation instructions include loop instructions and extern loop (ie x-loop) instructions and other operation instructions. The number of bytes is the same but the number of bytes returned by the return address/negative number/relative value and the number of return times is different. .

The following is the command format and corresponding fields and bit numbers according to the second embodiment of the present invention: fppi command: 3 bytes 2 bits (01) 1 bit (level) 9 bits (p-position) 12 bits H-displacement appi instruction: 2 bytes 2 bits (00) 1 bit (level) 1 bit (short appi index) 8 bits (v-displacement) 4 bits (h-displacement) short appi command: 1 byte 2 bits (00) 1 bit (level) 1 bit (ultra-short ppi index) 4 bits (h-displacement) loop command: 2 bytes 2 bits (11) 6 Bit (return address/negative number/relative value) 8 bits (return times) extern loop instruction: 2 bytes 2 bits (10) 8 bits (return address/negative number/relative value) 6 bits ( Return times)

The main difference between the instruction format of the second embodiment and the instruction format of the first embodiment is that the absolute time command operation instruction only includes the fppi instruction with a length of 3 bytes, while the relative time period command operation instruction includes the length of 2 bits. The tuple's appi instruction and the 1-byte s-appi instruction.

經由編譯器122對上述記憶符號編碼124的實例進行編譯後，輸出之編譯指令資料的二位元機器碼格式如下：

此些輸出的編譯指令資料儲存於記憶體單元112中。接著，事件處理器114(1)透過仲裁器116從記憶體單元112下載並執行此些編譯指令資料，以對應輸出波形訊號Pin_1。 The above instruction format can be compiled into two-bit machine code by the compiler 122. For example, the following is an example of the memory symbol code 124:

After compiling the above example of the memory symbol encoding 124 via the compiler 122, the output binary code format of the compiled instruction data is as follows:

The output compiled instruction data is stored in the memory unit 112. Then, the event processor 114(1) downloads and executes the compiled instruction data from the memory unit 112 through the arbiter 116 to correspond to the output waveform signal Pin_1.

The following is the command format and corresponding fields and bit numbers according to the third embodiment of the present invention: fppi command: 3-bit 3-bit (101) 1-bit (level) 8-bit (p-position) 12-bit H-displacement appi command: 3-bit 3-bit (000) 1-bit (level) 9-bit (p-displacement) 11-bit (h-displacement) short appi command: 2-byte 3 Bit (100) 1 bit (level) 9 bit (p-displacement) 3 bit (h-displacement) loop instruction: 2 bytes 3 bits (111) 5 bits (return address) 8 bits Yuan (return times) extern loop instruction: 2 bytes 3 bits (110) 7 bits (return address) 6 bits (return times)

The main difference between the instruction format of the third embodiment and the instruction format of the second embodiment is that, in the instruction format of the third embodiment, the instruction type The number of occupied bits is 3 bits, and the field in some instruction formats is reduced by 1 bit, for example, p-ppsition in the fppi operation instruction.

The following uses two event processors 114(1) and 114(2) as an example to illustrate the relationship between the memory symbol code 124 and the corresponding output waveform signals Pin_1 and Pin_2. An example of the memory symbol code 124 is as follows:

The waveform signal output corresponding to the above example is shown in Figure 3. For the waveform signal Pin_1, at time t1, the first fppi operation instruction is executed to initialize the signal level corresponding to the 8th position in the second column to 0. Next, at time t2, an appi operation instruction is executed to set the signal level of the 8th position in the second column to 1. After that, at time t3, the first s-appi operation instruction is executed, and the signal level of the current position is set to 0 for 8 time units. Then, at time t4, the inner loop of 100p1 is repeated, that is, the above-mentioned appi operation instruction and the first s-appi operation instruction are repeated twice until the execution of the third s-appi operation instruction ends. At a point in time At t5, the second s-appi operation instruction is executed, and the signal level of the current position is set to 1 for 18 time units. Then, at time t6, the outer loop of loop1 is repeated, that is, the inner loop of loop1 and the second s-appi operation instruction are repeated three times until the execution of the fourth second s-appi operation instruction is completed. Finally, execute the second s-appi operation command to set the signal level of the current position to 0 and continue until the end of the current waveform frame.

As for the waveform signal Pin_2, because the difference between the corresponding memory symbol encoding and the memory signal encoding corresponding to the waveform signal Pin_1 is only in the first fppi operation instruction, the signal level of the ninth position in the second row is initialized to 0 . It can be seen that the waveform signal Pin_2 is the rightward translation of the waveform signal Pin_1, and the waveform change of the two is the same when the translation is ignored.

The digital waveform signal generating device of the present invention has at least the following advantages. First of all, compared with the registered configurator waveform generator, microprocessor waveform generator and soft core processor waveform generator, the digital waveform signal generating device of the present invention can modify the code of the memory symbol without changing the hardware And the space occupied by its hardware and the amount of memory used are low, so it can generate faster waveform signals. In addition, the digital waveform signal generation device of the present invention adopts a parallel architecture, which is suitable for outputting multiple waveform signals at the same time. It is easier for programmers to edit the memory symbol codes, and the dedicated instruction set and compiler used by them can avoid such a slight The programs of the processor waveform generator and soft core processor waveform generator can be easily cracked, so the intellectual property rights of the programmer or company can be further protected. However, the application of the present invention is not limited to the field of integrated circuits, it can also be applied to motor drive, variable frequency drive, industrial control and other suitable fields.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100‧‧‧Digital waveform signal generating device

110‧‧‧Hardware

112‧‧‧Memory unit

114(1)~114(N)‧‧‧Event processor

116‧‧‧Arbiter

122‧‧‧ compiler

124‧‧‧ memory symbol encoding

Pin_1~Pin_N‧‧‧wave signal

Claims (9)

A digital waveform signal generating device includes: a memory unit for storing a compilation instruction data; a plurality of event processors for accessing the memory unit and generating and outputting at least one waveform signal according to the compilation instruction data, The event processors are of a parallel structure, and each of the event processors includes: a memory access unit for reading the compiled instruction data from the memory unit according to a current address; and a command extraction unit , Used to extract at least one instruction from the compiled instruction data; an instruction decoding unit, used to parse out the instruction type and the number of instruction operations from the at least one instruction; a branch prediction unit, used to determine the at least one instruction The instruction type is a continuous address or a jump address; and a command execution unit for executing the at least one instruction to update the waveform signal; and an arbiter for determining that the event processors read the memory unit Sequence; wherein, one or more of the at least one instruction belongs to a dedicated waveform event streaming command instruction set, the dedicated waveform event streaming command instruction set includes an absolute time point command operation instruction and a relative time period command operation instruction. The digital waveform signal generating device as described in item 1 of the patent application scope, wherein the absolute time point command operation instruction includes a waveform change absolute position and a waveform change relative position. The digital waveform signal generating device as described in item 1 of the patent application scope, wherein the relative time period command operation instruction includes a waveform to change the relative position. The digital waveform signal generating device as described in item 1 of the patent application scope, wherein the priority of the event processors is set by a user program or a hardware. The digital waveform signal generating device as described in item 1 of the scope of the patent application, wherein the event processors share the memory unit in multiple time-sharing. The digital waveform signal generating device as described in item 1 of the patent application scope, wherein the event processors are configured to execute in parallel. The digital waveform signal generating device as described in item 1 of the patent scope, wherein the memory unit is a static random access memory (SRAM), an electronic erasable programmable read-only memory ( electrically erasable programmable read only memory (EEPROM), a one-time programmable (OTP) memory or An electronic programmable read only memory (erasable programmable read only memory; EPROM). The digital waveform signal generating device as described in item 1 of the patent scope further includes a compiler for compiling a memory symbol code into the compilation instruction data. The digital waveform signal generating device as described in item 1 of the patent application scope, wherein the digital waveform signal generating device is universally programmable.

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