CN102214123B - Test method, computer device using test method and computer test system using test method - Google Patents
Test method, computer device using test method and computer test system using test method Download PDFInfo
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- CN102214123B CN102214123B CN2010101552754A CN201010155275A CN102214123B CN 102214123 B CN102214123 B CN 102214123B CN 2010101552754 A CN2010101552754 A CN 2010101552754A CN 201010155275 A CN201010155275 A CN 201010155275A CN 102214123 B CN102214123 B CN 102214123B
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Abstract
The invention discloses a test method, a computer device using the test method and a computer test system using the test method. By the test method, a system time signal of the computer device to be tested can be tested precisely; and the test method comprises the following steps of: firstly, recording a first clock period parameter and a second clock period parameter of an operation clock signal (central processing unit (CPU) Clock) respectively by reference to a first triggering edge and a second triggering edge which are triggered by an external reference time signal; then determining a reference clock period parameter according to the first clock period parameter and the second clock period parameter; recording a third clock period parameter and a fourth clock period parameter of the operation clock signal respectively by reference to a third triggering edge and a fourth triggering edge which are triggered by the system time signal; then determining a clock period parameter to be tested according to the third clock period parameter and the fourth clock period parameter; and finally, calculating error information of the system time signal according to the clock period parameter to be tested and the reference clock period parameter.
Description
Technical field
The present invention relates to a kind of method of testing, and a kind of method of testing of the signal of the system time for the measuring and calculation machine particularly.
Background technology
In the epoch now of making rapid progress in development in science and technology, computer installation has become Important Platform indispensable in people's daily life and enterprise operation.In the prior art, computer installation inside is provided with the system time circuit, in order to produce the system time signal of computer installation.In general, the system time circuit comprises oscillator, and the oscillator signal produced according to correspondence produces the system time signal.Yet oscillator all can have a little error in manufacturing process, make the corresponding system time signal produced produce some errors compared to the standard time.
At present industry is can not surpass ± 1 second in one day to the standard of the system time signal of computer installation, in other words, and namely ± 11.57 hundred unit of errors (Parts Per Million, ppm) very much.Therefore, how designing test macro that whether measuring and calculation machine effectively meet the aforementioned error criterion of industry is one of direction of constantly endeavouring of industry.
Summary of the invention
The present invention relates to a kind of computer testing system, comprise a computer installation, the computer testing system that the present invention is relevant carries out the degree of accuracy test in order to the system time signal to this computer installation to be tested and surveys.The computer testing system that the present invention is relevant is applied a Measurer so far computer installation of external reference time signal is provided.The relevant computer testing system of the present invention is also carried out a method of testing through computer installation thus, with the operation clock signal according to computer installation, outside reference time signal and this system time signal are sampled, obtained respectively corresponding cycle times to be tested and reference clock cycle parameter; And to be tested and this reference clock cycle times is estimated the control information of this system time signal according to this.Accordingly, compared to legacy test system, whether the relevant computer testing system of the present invention can be effectively meets its relevant criterion to the system time signal of computer installation is checked on.
According to a first aspect of the invention, propose a kind of computer testing system, comprise Measurer and computer installation.Measurer provides the external reference time signal, so that the time reference benchmark to be provided.Computer installation comprises that central processing unit and computer-readable medium central processing unit have operation clock signal (CPU Clock).Central processing unit reads computer-readable medium and carries out method of testing, with the system time signal for the treatment of the measuring and calculation machine, carries out the degree of accuracy test.Method of testing comprises following step.At first first and second triggering with reference to the external reference time signal triggers along (Triggering edge), records respectively first and second clock period parameter of operation clock signal.Then according to first and second clock period parameter, determine the reference clock cycle parameter, with the indication operation clock signal, in first and second, trigger the cycle times triggered between edge.Then the 3rd and the 4th of the triggering of frame of reference time signal the trigger edge, record respectively the 3rd and the 4th clock period parameter of operation clock signal.Then according to the 3rd and the 4th clock period parameter, determine clock period parameter to be tested, with the indication operation clock signal, in the 3rd and the 4th, trigger the cycle times triggered between edge.Calculate afterwards the control information of system time signal according to clock period parameter to be tested and reference clock cycle parameter.
According to a second aspect of the invention, provide a kind of computer installation, comprising central processing unit and computer-readable medium.Central processing unit has operation clock signal.Central processing unit reads computer-readable medium and carries out method of testing, with the system time signal for the treatment of the measuring and calculation machine, carries out the degree of accuracy test.Method of testing comprises following step.At first first and second triggering with reference to the external reference time signal triggers along (Triggering edge), records respectively first and second clock period parameter of operation clock signal.Then according to first and second clock period parameter, determine the reference clock cycle parameter, with the indication operation clock signal, in first and second, trigger the cycle times triggered between edge.Then the 3rd and the 4th of the triggering of frame of reference time signal the trigger edge, record respectively the 3rd and the 4th clock period parameter of operation clock signal.Then according to the 3rd and the 4th clock period parameter, determine clock period parameter to be tested, with the indication operation clock signal, in the 3rd and the 4th, trigger the cycle times triggered between edge.Calculate afterwards the control information of system time signal according to clock period parameter to be tested and reference clock cycle parameter.
According to a third aspect of the invention we, propose a kind of method of testing, be applied in computer installation to be tested, with the system time signal for the treatment of the measuring and calculation machine, carry out the degree of accuracy test.The measuring and calculation machine comprises central processing unit, and it has operation clock signal.Method of testing comprises following step.At first first and second triggering with reference to the external reference time signal triggers along (Triggering edge), records respectively first and second clock period parameter of operation clock signal.Then according to first and second clock period parameter, determine the reference clock cycle parameter, with the indication operation clock signal, in first and second, trigger the cycle times triggered between edge.Then the 3rd and the 4th of the triggering of frame of reference time signal the trigger edge, record respectively the 3rd and the 4th clock period parameter of operation clock signal.Then according to the 3rd and the 4th clock period parameter, determine clock period parameter to be tested, with the indication operation clock signal, in the 3rd and the 4th, trigger the cycle times triggered between edge.Calculate afterwards the control information of system time signal according to clock period parameter to be tested and reference clock cycle parameter.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
The accompanying drawing explanation
Fig. 1 illustrates the calcspar according to the computer testing system of the embodiment of the present invention.
Fig. 2 illustrates the detailed block diagram into the signal generator of Fig. 1.
Fig. 3 illustrates the coherent signal sequential chart into the signal generator 114 of Fig. 2.
Fig. 4 illustrates the process flow diagram according to the method for testing of the embodiment of the present invention.
Fig. 5 illustrates the part process flow diagram according to the method for testing of the embodiment of the present invention.
Fig. 6 illustrates the part process flow diagram according to the method for testing of the embodiment of the present invention.
Fig. 7 illustrates another process flow diagram according to the method for testing of the embodiment of the present invention.
Fig. 8 illustrates another calcspar according to the Measurer of the embodiment of the present invention.
Fig. 9 illustrates the calcspar again according to the Measurer of the embodiment of the present invention.
[main element symbol description]
1: computer testing system
10,20,30: Measurer
12: computer installation
L: communication path
112,212,312: oscillatory circuit
114,214,314: signal generating circuit
116,124,216,316: the input and output interfaces circuit
120: central processing unit
122: computer-readable medium
126: System on Chip/SoC
114a, 214a, 314a, 314e: counter
114b, 114c, 214b, 214c, 314b, 314c: comparer
114d; 214d; 314d: logical-arithmetic unit
218: correcting circuit
318: microprocessor
319: display
Embodiment
The external reference time signal that the computer testing system system of the embodiment of the present invention provides with reference to Measurer is carried out relevant system time signal testing operation.
Please refer to Fig. 1, it illustrates the calcspar according to the computer testing system of the embodiment of the present invention.Computer testing system 1 comprises Measurer 10 and computer installation 12.Measurer 10 is in order to external reference time signal STr to be provided, so that the time reference benchmark to be provided.Computer installation 12 is system to be tested, and it carries out test operation with reference to external reference time signal STr to system time signal CKs own.
Measurer 10 comprises oscillatory circuit 110, signal generating circuit 112 and input and output interfaces circuit 124.Oscillatory circuit 110 is in order to provide reference clock signal CKr.For instance, oscillatory circuit 110 is Thermostatically controlled quartz generator (Oven Controlled Crystal Oscillator, OCXO), it can eliminate the impact of variation of ambient temperature on its oscillation frequency, the reference clock signal CKr of the frequency stability of have to provide ± 0.1 hundred unit of error (Parts Per Million, ppm) very much.In an operational instances, reference clock signal CKr has frequency 10 MHz (Mega Hertz, MHz).
Comparer 114b is count parameter P and comparative parameter C1 relatively, and output corresponds to the control signal SC1 of the first level when count parameter P is more than or equal to comparative parameter C1, and, when count parameter P is less than comparative parameter C1, output corresponds to the control signal SC1 of second electrical level.Comparer 114c is count parameter P and comparative parameter C2 relatively, and output corresponds to the control signal SC2 of the first level when count parameter P is more than or equal to comparative parameter C2, and, when count parameter P is less than comparative parameter C2, output corresponds to the control signal SC2 of second electrical level.For instance, this first level is for example high signal level, and this second electrical level is for example low-signal levels.
Logical-arithmetic unit 114d is in order to the control signal SC1 in response to corresponding to same level and SC2, trigger the triggering of external reference time signal STr along (Triggering Edge), and anti-phase the triggerings edge (Inverse Triggering Edge) of in response to the control signal SC1 that corresponds to varying level and SC2, triggering external reference time signal STr, produce by this external reference time signal STr.For instance, the triggering edge of external reference time signal STr and anti-phase triggering are along being respectively just along (Rising Edge) and negative edge (Falling Edge).
Please refer to Fig. 3, it illustrates the coherent signal sequential chart into the signal generator 114 of Fig. 2.In an operational instances, counter 114a triggers on the just edge in the 1st cycle of reference clock signal CKr the counting operation that time point TP1 starts to carry out count parameter P, and comparative parameter C1 and C2 equal respectively numerical value (5000000)
10And (10000000)
10.So, at 5th * 10 of reference clock signal CKr
6The individual cycle just when triggering time point TP2, control signal SC1 will be promoted to first signal level (being high signal level) from secondary signal level (being low-signal levels); Logical-arithmetic unit 114d triggers the anti-phase triggering of external time reference signal STr along (being negative edge) in response to the control signal SC1 that corresponds to the unlike signal level and SC2.
At the 10th of reference clock signal CKr
7The individual cycle just when triggering time point TP3, control signal SC2 will be promoted to first signal level (being high signal level) from secondary signal level (being low-signal levels), the control counter 114a replacement count parameter P of take is numerical value 0; Comparer 114b and 114c export respectively in response to the count parameter P of numerical value 0 control signal SC1 and the SC2 that corresponds to secondary signal level (being low-signal levels) immediately; Logical-arithmetic unit 114d triggers external time reference signal STr triggering in response to the control signal SC1 that corresponds to the same signal level and SC2 is along (just be along).
Similar in appearance to the operation of aforementioned operation time point TP2 and TP3 also repeatedly trigger respectively operation time point TP4, TP6 in the even number order ... and operation time point TP5, the TP7 of odd number order ..., accordingly, to produce every 5 * 10
6The cycle of individual reference clock signal CKr is triggered once the just external time reference signal STr of edge/negative edge, in other words, is the external time reference signal STr with frequency 1Hz.
In an operational instances, signal generating circuit 114 is with complex programmable logic device (ComplexProgrammable Logic Device, CPLD) circuit is realized, the external time reference signal STr that meets transistor-transistor logic circuit (Transistor-Transistor Logic, TTL) operating voltage specification with output.
Input/output interface circuit 116 exports external reference time signal STr to computer installation 12 via communication path L.For instance, communication path L is network path, and input/output interface circuit 116 comprises and turns suggestion specification 232 by the TTL interface (Recommendation Standard 232, RS232) interface signal converter, to carry out the signal conversion to outside reference time signal STr.
At first as step (a), what central processing unit 120 triggered with reference to external reference time signal STr first for example triggers, along (just be along) and second and for example triggers, along (just be along), record respectively clock period parameters R 1 and the R2 of operation clock signal CPU_CLK, wherein this outside reference time signal STr this first and this second trigger that to take outside reference time signal STr be one period operating period that benchmark was defined along defining, this first and this second trigger along the initial time point of corresponding so far operating period respectively and stop time point.Then as step (b), central processing unit 120 determines reference clock cycle parameter CR1 according to clock period parameters R 1 and R2, the reference clock cycle parameter CR1 indication operation clock signal CPU_CLK triggering cycle times that actual sampling obtains in this period operating period.
Then as step (c), what central processing unit 120 frame of reference time signal STs triggered the 3rd for example triggers, along (just be along) and the 4th and for example triggers, along (just be along), records respectively clock period parameters R 3 and the R4 of operation clock signal CPU_CLK.Wherein this system time signal STs this 3rd and this 4th trigger along defining and take system time signal STs as this period operating period that benchmark was defined, this 3rd and this 4th trigger along the initial time point of corresponding so far operating period respectively and stop time point.Then as step (d), central processing unit 120 determines clock period parameters C R2 to be tested according to clock period parameters R 3 and R4, clock period parameters C R2 to be tested indication operation clock signal CPU_CLK this 3rd and this 4th trigger along between the cycle times that triggers.
As step (e), central processing unit 120 calculates the control information Dfs of system time signal STs according to clock period parameters C R2 to be tested and reference clock cycle parameter CR1 afterwards.For instance, central processing unit 120 is for example carried out the computing of following equation, to obtain control information Dfs:
Wherein control information Dfs be take ppm as unit.
In an example, the step in the method for testing of the present embodiment (a) also comprises step (a1)-(a4), as shown in Figure 5.As step (a1), central processing unit 120 judges whether to detect first of external reference time signal STr and triggers edge; If not, repeated execution of steps (a1); If, execution step (a2), central processing unit 120 is carried out the clock information accessing operation, to obtain clock period parameters R 1.Then as step (a3), central processing unit 120 judges whether to detect second of external reference time signal STr and triggers edge; If not, repeated execution of steps (a3); If, execution step (a4), central processing unit 120 is carried out the clock information accessing operation, to obtain clock period parameters R 2.
In an example, the step in the method for testing of the present embodiment (c) also comprises step (c1)-(c3), as shown in Figure 6.As step (c1), central processing unit 120 judges whether to detect the 3rd of system time signal STs and triggers edge; If not, repeated execution of steps (c1); If, execution step (c2), central processing unit 120 is carried out the clock information accessing operation, to obtain clock period parameters R 3.Then as step (c3), central processing unit 120 judges whether to detect the 4th of system time signal STs and triggers edge; If not, repeated execution of steps (c3); If, execution step (c4), central processing unit 120 is carried out the clock information accessing operation, to obtain clock period parameters R 4.
For instance, central processing unit 120 is carried out poll (Polling) operation, judge whether constantly to detect the triggering edge of external reference time signal STr with in reaching (a3) in step (a1), and judge whether to detect to savings the triggering edge of system time signal STs in step (c1) reaches (c3).For instance, central processing unit 120 is for supporting the processor of x86 instruction set architecture (Instruction Set Architecture), and central processing unit 120 is for example via the time of reading stamp counter (the Read Time Stamp Counter carried out in the x86 instruction set architecture, RDTSC) instruction, to obtain clock period parameters R 1 and R2 in step (a2) and (a4) respectively, and obtain clock period parameters R 3 and R4 in step (c2) and (c4) respectively.
In an example, the method for testing of the present embodiment is in step (a)-(e) step (f) more for example before, as shown in Figure 7.In step (f), the central processing unit all software interruption of 120 disabled (Interrupt), affect central processing unit 120 performed method of testing in step (a)-(e) to avoid other software interruption.In an example, the method of testing of the present embodiment is executed in non-time division multiplexing (Time DivisionMultiplexing, TDM) under system program (Operation System) environment, to avoid each testing procedure because operating delay causes the test result misalignment.
In the present embodiment, though only take situation that Measurer 10 has a circuit structure as shown in Figure 2, explain as example, yet the Measurer 10 of the embodiment of the present invention is not limited to this, and can also have other forms of circuit structure.For instance, in Measurer 20, also can comprise correcting circuit 218, it adjusts comparative parameter C2 according to proofreading and correct numerical value Ad, by this frequency of examining clock signal C Kr is carried out to error correction, as shown in Figure 8.
For instance, when the error of have+0.3ppm of reference clock signal CKr, mean that each 1,000,000 clock period of reference clock signal CKr will have more 0.3 cycle with respect to 10MHz signal accurately, in other words, each second will have more 3 cycles.Accordingly, the numerical value 10 that correcting circuit 218 can be original by it by comparative parameter C2
7Be modified to 10
7-3 (being 9999997), make the external reference time signal STr of the reference clock signal CKr generation of have+0.3ppm of basis still can have accurately the Cycle Length of 1 second, is the frequency that corresponds to 1Hz.Accordingly, can eliminate the frequency error of reference clock signal CKr via the correction operation of 218 pairs of comparison parameters C 2 of correcting circuit, make the corresponding external reference time signal STr produced can precisely correspond to the operating frequency of user design.
In another example, Measurer 30 also can comprise counter 314e and impact damper 314f, and Measurer 30 receives signal STi input time, and it is carried out to relevant accuracy metrology operation, as shown in Figure 9.Counter 214e counts to get count parameter P ' in response to reference clock signal CKr, and in response to input time signal STi triggering along replacement count parameter P '.The count parameter P ' of the temporary rolling counters forward of impact damper 214f, and in response to input time signal STi triggering along latching count parameter P '.
The computer testing system of the present embodiment is applied a Measurer so far computer installation of external reference time signal is provided.The computer testing system of the present embodiment is also carried out a method of testing through computer installation thus, with the operation clock signal according to computer installation, outside reference time signal and this system time signal are sampled, obtained respectively corresponding cycle times to be tested and reference clock cycle parameter; And according to this to be tested and this reference clock week its number of times estimate the control information of this system time signal.Accordingly, compared to legacy test system, whether the computer testing system of the present embodiment can meet its relevant criterion to the system time signal to computer installation is effectively checked on.
In sum, although the present invention with a preferred embodiment openly as above, so it is not in order to limit the present invention.These those skilled in the art, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (9)
1. a computer testing system comprises:
One Measurer, in order to an external reference time signal to be provided, so that the time reference benchmark to be provided; And
One proving installation, be applied in a computer installation to be tested, with the system time signal to this computer installation to be tested, carry out the degree of accuracy test, this computer installation to be tested comprises a central processing unit, this central processing unit has an operation clock signal, and this proving installation comprises:
Edge is triggered on the one first triggering edge and one second that this external reference time signal provided with reference to this Measurer triggers, and records respectively one first clock period parameter of this operation clock signal and the parts of a second clock cycle parameter;
According to this first and this second clock cycle parameter determine the parts of a reference clock cycle parameter, this reference clock cycle parameter indicate this operation clock signal in this first and this second trigger along between the cycle times that triggers;
Edge is triggered on one the 3rd triggering edge and the 4th of triggering with reference to this system time signal, records respectively one the 3rd clock period parameter of this operation clock signal and the parts of one the 4th clock period parameter;
Determine the parts of a clock period parameter to be tested according to the 3rd and the 4th clock period parameter, this clock period parameter to be tested indicates this operation clock signal to trigger in the 3rd and the 4th the cycle times triggered between edge; And
Calculate the parts of a control information of this system time signal according to this clock period parameter to be tested and this reference clock cycle parameter.
2. computer testing system as claimed in claim 1, wherein record this first and the parts of this second clock cycle parameter comprise:
Judge whether to detect the subassembly on this first triggering edge;
In detect this first trigger along the time carry out the subassembly of a clock Information Access operation, to obtain this first clock period parameter;
Judge whether to detect the subassembly on this second triggering edge; And
In detect this second trigger along the time carry out the subassembly of this clock information accessing operation, to obtain this second clock cycle parameter.
3. computer testing system as claimed in claim 1, wherein record the 3rd and the parts of the 4th clock period parameter comprise:
Judge whether to detect the 3rd and trigger the subassembly on edge;
In detect the 3rd trigger along the time carry out the subassembly of a clock Information Access operation, to obtain the 3rd clock period parameter;
Judge whether to detect the 4th and trigger the subassembly on edge; And
In detect the 4th trigger along the time carry out the subassembly of this clock information accessing operation, to obtain the 4th clock period parameter.
4. a proving installation, be applied in a computer installation to be tested, with the system time signal to this computer installation to be tested, carry out the degree of accuracy test, this computer installation to be tested comprises a central processing unit, this central processing unit has an operation clock signal, and this proving installation comprises:
Edge is triggered on the one first triggering edge and one second that the external reference time signal provided with reference to a Measurer triggers, and records respectively one first clock period parameter of this operation clock signal and the parts of a second clock cycle parameter;
According to this first and this second clock cycle parameter determine the parts of a reference clock cycle parameter, this reference clock cycle parameter indicate this operation clock signal in this first and this second trigger along between the cycle times that triggers;
Edge is triggered on one the 3rd triggering edge and the 4th of triggering with reference to this system time signal, records respectively one the 3rd clock period parameter of this operation clock signal and the parts of one the 4th clock period parameter;
Determine the parts of a clock period parameter to be tested according to the 3rd and the 4th clock period parameter, this clock period parameter to be tested indicates this operation clock signal to trigger in the 3rd and the 4th the cycle times triggered between edge; And
Calculate the parts of a control information of this system time signal according to this clock period parameter to be tested and this reference clock cycle parameter.
5. proving installation as claimed in claim 4, wherein record this first and the parts of this second clock cycle parameter comprise:
Judge whether to detect the subassembly on this first triggering edge;
In detect this first trigger along the time carry out the subassembly of a clock Information Access operation, to obtain this first clock period parameter;
Judge whether to detect the subassembly on this second triggering edge; And
In detect this second trigger along the time carry out the subassembly of this clock information accessing operation, to obtain this second clock cycle parameter.
6. proving installation as claimed in claim 4, wherein record the 3rd and the parts of the 4th clock period parameter comprise:
Judge whether to detect the 3rd and trigger the subassembly on edge;
In detect the 3rd trigger along the time carry out the subassembly of a clock Information Access operation, to obtain the 3rd clock period parameter;
Judge whether to detect the 4th and trigger the subassembly on edge; And
In detect the 4th trigger along the time carry out the subassembly of this clock information accessing operation, to obtain the 4th clock period parameter.
7. a method of testing, be applied in a computer installation to be tested, with the system time signal to this computer installation to be tested, carry out the degree of accuracy test, this computer installation to be tested comprises a central processing unit, this central processing unit has an operation clock signal, and this method of testing comprises:
Edge is triggered on the one first triggering edge and one second that the external reference time signal provided with reference to a Measurer triggers, and records respectively one first clock period parameter and a second clock cycle parameter of this operation clock signal;
According to this first and this second clock cycle parameter determine a reference clock cycle parameter, this reference clock cycle parameter indicate this operation clock signal in this first and this second trigger along between the cycle times that triggers;
Edge is triggered on one the 3rd triggering edge and the 4th of triggering with reference to this system time signal, records respectively one the 3rd clock period parameter and one the 4th clock period parameter of this operation clock signal;
Determine a clock period parameter to be tested according to the 3rd and the 4th clock period parameter, this clock period parameter to be tested indicates this operation clock signal to trigger in the 3rd and the 4th the cycle times triggered between edge; And
Calculate a control information of this system time signal according to this clock period parameter to be tested and this reference clock cycle parameter.
8. method of testing as claimed in claim 7, wherein record this first and the step of this second clock cycle parameter also comprise:
Judge whether to detect this first triggering edge;
In detect this first trigger along the time carry out a clock Information Access operation, to obtain this first clock period parameter;
Judge whether to detect this second triggering edge; And
In detect this second trigger along the time carry out this clock information accessing operation, to obtain this second clock cycle parameter.
9. method of testing as claimed in claim 7, wherein record the 3rd and the step of the 4th clock period parameter also comprise:
Judge whether to detect the 3rd and trigger edge;
In detect the 3rd trigger along the time carry out a clock Information Access operation, to obtain the 3rd clock period parameter;
Judge whether to detect the 4th and trigger edge; And
In detect the 4th trigger along the time carry out this clock information accessing operation, to obtain the 4th clock period parameter.
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| CN1294326A (en) * | 1999-10-25 | 2001-05-09 | 威盛电子股份有限公司 | Crystal chip set of computer masterboard referring to different-frequency clocks and its signal processing method |
| CN1790286A (en) * | 2004-12-17 | 2006-06-21 | 上海环达计算机科技有限公司 | PCI test card and test method thereof |
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| CN1294326A (en) * | 1999-10-25 | 2001-05-09 | 威盛电子股份有限公司 | Crystal chip set of computer masterboard referring to different-frequency clocks and its signal processing method |
| CN1790286A (en) * | 2004-12-17 | 2006-06-21 | 上海环达计算机科技有限公司 | PCI test card and test method thereof |
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